Date 20-23 Oct. 2009
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Displaying Results 1 - 25 of 338
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Low power design of vlsi circuits and systems
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PDF (1371 KB)
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Low-power MCML circuit with sleep-transistor
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PDF (3248 KB)
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A systolic architecture with linear space complexity for longest common subsequence problem
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PDF (5703 KB)
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Switching activity calculation of VLSI adders
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PDF (3003 KB)
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Design of multi-valued double-edge-triggered JK flip-flop based on neuron MOS transistor
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PDF (1575 KB)
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T2- TAM:Reusing infrastructure resource to provide parallel testing for NoC based Chip
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PDF (3766 KB)
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Transaction level model of NoC based on SystemC
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PDF (3791 KB)
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Mixed optimization method in design of FC-2
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PDF (4220 KB)


