By Topic

Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on

Date 27-28 Oct. 2009

Filter Results

Displaying Results 1 - 25 of 243
  • [Front cover]

    Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (341 KB)  
    Freely Available from IEEE
  • [Title page i]

    Page(s): i
    Save to Project icon | Request Permissions | PDF file iconPDF (10 KB)  
    Freely Available from IEEE
  • [Title page iii]

    Page(s): iii
    Save to Project icon | Request Permissions | PDF file iconPDF (49 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Page(s): iv
    Save to Project icon | Request Permissions | PDF file iconPDF (104 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): v - xx
    Save to Project icon | Request Permissions | PDF file iconPDF (187 KB)  
    Freely Available from IEEE
  • Preface

    Page(s): xxi
    Save to Project icon | Request Permissions | PDF file iconPDF (64 KB)  
    Freely Available from IEEE
  • Committee Members

    Page(s): xxii - xxv
    Save to Project icon | Request Permissions | PDF file iconPDF (95 KB)  
    Freely Available from IEEE
  • list-reviewer

    Page(s): xxvi - xxviii
    Save to Project icon | Request Permissions | PDF file iconPDF (73 KB)  
    Freely Available from IEEE
  • Agile EDI Framework for B2B Applications

    Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    The unified software development process or unified process is a popular iterative and incremental software development process framework. The best-known and extensively documented refinement of the unified process is the rational unified process (RUP) created by the Rational Software Corporation, a division of IBM. Agile unified process is a simplified version of the RUP developed by Scott Ambler, the Practice Leader for agile development at IBM. It describes a simple, easy to understand approach to developing business application software using agile techniques and concepts yet still remaining true to the RUP. This paper explains the need of applying agile methodologies and agile unified process framework for developing B2B, EDI applications. This paper presents a refined agile unified process framework tailored for EDI (electronic data interchange) and B2B (business-to-business) software projects. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Public Key Cryptosystems Based on Chaotic-Chebyshev Polynomials

    Page(s): 4 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1358 KB) |  | HTML iconHTML  

    Due to rapid developments in limits and possibilities of communications and information transmissions, there is a growing demand of cryptographic techniques, which has spurred a great deal of intensive research activities in the study of cryptography. This paper describes a public key encryption based on Chebyshev polynomials. We discuss the algorithm for textual data and present the cryptanalysis which can be performed on this algorithm for the recovery of encrypted data. We also describe a simple hashing algorithm for making this algorithm more secure, and which can also be used for digital signature. The main scope of this paper is to propose an extension of this algorithm to images and videos and making it secure using multilevel scrambling and hash. Software implementations and experimental results are also discussed in detail. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sender-Side Public Key Deniable Encryption Scheme

    Page(s): 9 - 13
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    Consider a situation in which the transmission of encrypted message is intercepted by an adversary who can later ask the sender to reveal the random choices (and also the secret key, if one exists) used in generating the cipher text, thereby exposing the plaintext. An encryption scheme is deniable if the sender can generate `fake random choice' that will make the cipher text `look like' an encryption of a different plaintext, thus keeping the real plaintext private. Analogous requirements can be formulated with respect to attacking the receiver and with respect to attacking both parties. In this paper we propose a scheme for the sender side deniable encryption. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fuzzy Based Grid Voltage Stabilization in a Wind Farm Using Static VAR Compensator

    Page(s): 14 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    When a squirrel cage induction type wind electric generator (WEG) is connected to power grid, due to variations in load and wind speed, there will be fluctuations in the grid voltage. In this paper, the effect of load and wind speed variations on real power supplied and reactive power consumed by the WEG as well as voltage on the grid are studied. The voltage variation in the grid is controlled by reactive power compensation using shunt connected static VAR compensator (SVC) comprising thyristor controlled reactor (TCR) and fixed capacitor (FC). The TCR is operated automatically by a fuzzy logic controller (FLC). The complete system is modeled using MATLAB SIMULINK. Results show an appreciable improvement in the grid voltage by compensating the reactive power. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ensembling Rule Based Classifiers for Detecting Network Intrusions

    Page(s): 19 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (379 KB) |  | HTML iconHTML  

    An intrusion is defined as a violation of the security policy of the system, and hence, intrusion detection mainly refers to the mechanisms that are developed to detect violations of system security policy. Recently, data mining techniques have gained importance in providing the valuable information which in turn can help to enhance the decision on identifying the intrusions (attacks). In this paper; we evaluate the performance of various rule based classifiers like: JRip, RIDOR, NNge and decision table using ensemble approach in order to build an efficient network intrusion detection system. We use KDDCup'99, intrusion detection benchmark dataset (which is a part of DARPA evaluation program) for our experimentation. It can be observed from the results that the proposed approach is accurate in detecting network intrusions, provides low false positive rate, simple, reliable and faster in building an efficient network intrusion system. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced Biometric Identification on Face, Gender and Age Recognition

    Page(s): 23 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    The face recognition system attains good accuracy in personal identification when they are provided with a large set of training sets. In this paper, we proposed Advanced Biometric Identification on Face, Gender and Age Recognition (ABIFGAR)algorithm for face recognition that yields good results when only small training set is available and it works even with a raining set as small as one image per person. The process is divided into three phases: Pre-processing, Feature Extraction and Classification. The geometric features from a facial image are obtained based on the symmetry of human faces and the variation of gray levels, the positions of eyes, nose and mouth are located by applying the Canny edge operator. The gender and age are classified based on shape and texture information using Posteriori Class Probability and Artificial Neural Network respectively. It is observed that the face recognition is 100%, the gender and age classification is around 98% and 94% respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Novel Flash Analog-to-Digital Converter Design Using Cadence Tool

    Page(s): 28 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (509 KB) |  | HTML iconHTML  

    In this paper, we design a pipelined flash Analog-to-Digital Converter (ADC) to achieve high speed using 0.18 um CMOS technology. The results obtained are presented here. The physical circuit is more compact than the previous design. Power, processing time, and area are all minimized. This design can be used for modern high speed ADC applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Detailed Study and Analysis of OCR Research in South Indian Scripts

    Page(s): 31 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (908 KB) |  | HTML iconHTML  

    This paper provides an overview of the OCR (optical character recognition) research in South Indian languages. OCR reading technology is benefited by the evolution of high-powered desktop computing allowing for the development of more powerful recognition software that can read a variety of common printed fonts and handwritten texts. But still it remains a highly challenging task to implement an OCR that works under all possible conditions and gives highly accurate results. There were a lot of ongoing works in Indian scripts. The aim of this paper is to provide an introduction for the researchers in this field. Since we have only limited facilities for South Indian languages, the area is still promising and indeed it is the need of the society. We have tried to describe the specialties of the scripts, techniques employed in, recognition methods and the result comparison of different OCR methods developed for South Indian languages in this paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of Time Synchronization Protocols in Wireless Sensor Networks

    Page(s): 39 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    Wireless sensor network consists of spatially distributed sensors dedicated to closely observe the real-world phenomena. The sensors that are distributed in an uncontrolled manner needs to configure themselves in a communication network in order to collect information. In case of sensor network data fusion is a basic operation, whereby the collected information from each sensor node needs to be agglomerated in a meaningful manner. Applications of sensor network require integration of data from individual nodes where scope, lifetime, and precision are very critical parameters. And so it is important that message exchanged between the sensors for data fusion are time stamped by each sensor's local clock. This mandates the need for a common notion of time among the sensors. In this paper we explore various time synchronization protocols and present theoretical analysis of protocols based on quantitative and qualitative criteria. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Efficient Bidirectional Frame Prediction Using Particle Swarm Optimization Technique

    Page(s): 42 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    This paper presents a Novel Bidirectional motion estimation technique, which is based on the Particle swarm optimization algorithm. Particle swarm optimization (PSO) is a population based optimization technique which has the potentiality to avoid local minima solution which is usually encountered by the traditional block matching algorithms (BMA) such as the three step search (TSS) and the diamond search (DS). To speed up the search, static macro blocks are found in our method, which is particularly beneficial to those video sequences containing small motion contents. Skipping such static macro blocks from processing can save the computation time and memory also. In the proposed method each time we are finding the best matching macro block in two frames at a time so we can reduce the number of error function calculations and it is faster than if we apply PSO technique to find forward motion vector and backward motion vector separately. The proposed method is applied to a number of benchmark video sequences and the results are compared with those obtained by applying the existing methods. Simulation results shows that the proposed algorithms gives the close match of PSNR values when compared to joint search algorithm with DS. Thus, PSO algorithm for Bidirectional motion estimation is empirically given to reduce computational complexity. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Efficient Approach for Non-Invertible Cryptographic Key Generation from Cancelable Fingerprint Biometrics

    Page(s): 47 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (465 KB) |  | HTML iconHTML  

    The principal drawback of the existing cryptographic algorithms is the maintenance of their key's secrecy. Added with, human users have a difficult time remembering strong but lengthy cryptographic keys. As a result, utilizing individual's biometric features in the generation of strong and repeatable cryptographic keys has gained enormous popularity among researchers. The unpredictability of the user's biometric features, incorporated into the generated cryptographic key, makes the key unguessable to an attacker lacking noteworthy knowledge of the user's biometrics. Nevertheless, if a person's biometric is lost once, it will be compromised forever as it is inherently associated with the user. To overcome the above, cancelable biometrics has been proposed as an effective solution for canceling and re-issuing biometric templates. Here, we propose an innovative and efficient approach to generate a non-invertible cryptographic key from cancelable fingerprint templates. Initially, a one-way transformation is applied on the minutiae points extracted from the fingerprints, to attain a set of transformed points. Subsequently, the transformed points are made use of to form cancelable templates. The cancelable fingerprint templates are then utilized to generate a unique non-invertible key. As the cryptographic key generated is non-invertible, it is highly infeasible to acquire the cancelable fingerprint templates or the original fingerprint from the generated key. The effectiveness of the proposed approach is demonstrated by making use of fingerprints accessible from public sources. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core

    Page(s): 53 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1790 KB) |  | HTML iconHTML  

    Power has become an important aspect in the design of general purpose processors. The conventional RISC processors consume too much power as compared with other processors. The power reduction in these processors is done in the fabrication step itself. But this is a complex process. If we can implement the techniques for power reduction in front end process then we can easily design the low power processors without any complexity. In this paper we are proposing low power design in front end process. There are lot of techniques to reduce the power. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability. This RISC processor is designed using pipelined architecture; through this we can improve the speed of the operation. In this we are using 5-stage pipelining. The 5 stages are Fetch, Decode, Execute, Memory and Write Back. During the design process we are including varies low power techniques in architectural level also we are proved that our proposed methods is more efficient than back-end low power reduction techniques. Low-power embedded processors are used in a wide variety of applications including cars, phones, digital cameras, printers, and other such devices. The reason for their wide use is that they are small; therefore, they do not take up much die area and are cost effective to fabricate. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Checkpointing and Recovery Algorithm Based on Location Distance, Handoff and Stationary Checkpoints for Mobile Computing Systems

    Page(s): 58 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (854 KB) |  | HTML iconHTML  

    In this paper we present a checkpointing and failure recovery algorithm suited to mobile computing systems. A survey of mobile systems and the algorithms that are presently available is made to gather the essential knowledge about how these systems work. This includes study and analysis of existing checkpointing & recovery algorithms to identify their relative advantages & disadvantages. The existing algorithms suffers from problems like overhead involved in taking checkpoints and time to recover from a failure in an attempt to make a trade-off between efficiency and reliability. Hence we have attempted to develop an algorithm to solve these problems as far as possible. Our proposed algorithm has three subparts - a checkpointing scheme, a failure recovery scheme and authentication scheme for a mobile host. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic Leadership Algorithm for Hierarchical Multi-Smart Robot Coordination in Atomic Power plants

    Page(s): 63 - 67
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB) |  | HTML iconHTML  

    A multi smart robot should be able to analyze the situation faster and make appropriate decisions with minimal interference of the human in normal as well as in critical situations for performing various tasks. This is typically designed for the regions where there are high radiation emissions. The use of RFID tags makes the system work in the form of groups under a leader and they communicate among themselves. Pervasive computing provides smartness for the robot in efficient coordination, decision making, monitoring with more leadership quality and common sense reasoning. In this paper a new dynamic leadership algorithm is proposed wherein a leader is elected according to the parameters taken into account. The objective is to make the system more remote, completely independent and more robust for exchanging information with increased degree of freedom. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Quantum Circuit Simulator (QCS)

    Page(s): 68 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (491 KB) |  | HTML iconHTML  

    Quantum logic gate is a circuit, which performs a fixed unitary operation on selected qubits in a fixed period of time. The aim of this paper is to propose a simulator - Quantum Circuit Simulator (QCS) that simulates the quantum logic gates. This is a hardware-based simulator. Normally the quantum computers use quantum gates, which perform the arithmetic operations by means of Quantum Arithmetic And Logic Unit (QALU), which is similar to ALU in conventional computers. This paper presents the structure of quantum gates and their simulation result along with their run time calculation. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of Intensity Modulated Optical Illumination on the Y Parameters of the GaAs MESFET

    Page(s): 71 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (371 KB) |  | HTML iconHTML  

    In this paper the effect of an intensity-modulated optical signal on the Y parameters of a MESFET is studied theoretically. It shows that at a constant gate voltage the drain current of the device can be controlled by the intensity of incident optical power density and the frequency of the modulating signal frequency because the Y parameters of the device change with the intensity of incident optical power density and the frequency of the modulating signal. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Analog to Digital Converter Using CMOS Logic

    Page(s): 74 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB) |  | HTML iconHTML  

    The real world signals are all analog in nature. The digital signals and digital circuits offer greater advantages as compared to analog circuits in processing speed and efficient transmitting. So in order to convert the analog signals to digital efficiently an ldquoAnalog to digital converterrdquo is required. The System on Chip (SoC) forces the analog circuits to be integrated with digital circuits. To follow the scaling down of the SoC trend, analog to digital converter should be operated at low voltages. Thus the idea behind the paper is to design a 3-bit flash ADC using Threshold Inverter Quantization technique with 130 nm CMOS technology for high speed and low voltage applications. Threshold Inverter Quantization (TIQ) is a unique way to generate a comparator for a high speed CMOS flash ADC. To improve further, the fat tree encoder that is highly suitable for the ultrahigh speed flash ADCs. A fat tree encoder that has signal delay of ldquo0rdquo is used for better performance. The speed is improved by almost a factor of 2 when using the fat tree encoder. The fat tree encoder is an effective solution for the bottleneck problem in ultra-high speed ADCs. The proposed A/D converter is suitable for System on Chip (SoC) applications in wireless products and other ultra high speed applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.