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SOI Conference, 2009 IEEE International

Date 5-8 Oct. 2009

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Displaying Results 1 - 25 of 71
  • GC's Welcome

    Publication Year: 2009 , Page(s): 1 - 2
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    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2009 , Page(s): 1
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  • Introduction and history

    Publication Year: 2009 , Page(s): 1 - 5
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  • Committee

    Publication Year: 2009 , Page(s): 1
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  • Conference Committee letter

    Publication Year: 2009 , Page(s): 1 - 2
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  • List of presentations

    Publication Year: 2009 , Page(s): 1 - 7
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  • FDSOI for low power CMOS (invited)

    Publication Year: 2009 , Page(s): 1 - 2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (577 KB) |  | HTML iconHTML  

    As the low power technology is scaled to below 32 nm node, a number of challenges are emerging, that of scaling L (to fit at pitch) and the device leakage (GIDL and junction) . A fully depleted device can enable both L scaling and at the same time keep the GIDL much below the bulk CMOS. Significant progress has been made on FD on thin SOI. They include demonstration of devices with the right threshold (with high K) on SOI films of ~5-6 nm, and L of ~20 nm. It is argued that FDSOI can meet the requirements for a LP technology. View full abstract»

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  • Review of FINFET technology

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    In view of the difficulties in planar CMOS transistor scaling to preserve an acceptable gate to channel control FINFET based multi-gate (MuGFET) devices have been proposed as a technology option for replacing the existing technology. The attractiveness of FINFET consists in the realization of self-aligned double-gate devices with a conventional CMOS process. This allows extending the gate scaling beyond the planar transitor limits, maintaining a steep subthreshold slope, better performance with bias voltage scaling and good matching due to low doping concentration in the channel. There are, however, several challenges and roadblocks that FINFET technology has to face to be competitive with other technology options: high access resistance related to the extremely thin body, Vtau setting, implementation of strain boosters and manufacturability related to the non planar process and very tight process control. View full abstract»

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  • A guided tour of electronic design automation (EDA) for design of silicon on insulator (SOI) SoCs

    Publication Year: 2009 , Page(s): 1 - 2
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    The design of SOI-based SoCs has traditionally been the province of a few companies that could afford very labor-intensive custom design approaches - microprocessor companies looking for performance or aerospace companies looking for rad-hard electronics. In recent years, SOI has become a more attractive option for SoC design teams that have traditionally targeted bulk silicon. With current improvements in SOI substrates, processes, devices, design IP and EDA tools, SoC design in SOI can look and feel essentially the same as design in bulk silicon. Designers can use the same familiar EDA tools and flows for bulk silicon, while achieving better performance and power results that are the hallmark of SOI. View full abstract»

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  • Demonstration of low temperature CMOS devices on SiOG and SOI substrates

    Publication Year: 2009 , Page(s): 1 - 2
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    The fabrication and analysis of CMOS devices fabricated on Silicon-on-Glass (SiOG) and compared to SOI (SIMOX) substrates are presented. Key aspects of the low temperature (< 600degC) fabrication process are described. The devices from the SiOG substrate were observed to be comparable to those fabricated on SOI (SIMOX) with respect to carrier mobility and off-state leakage current. SiOG is viewed as a platform with potential applications in advanced flat panel mobile display modules as well as low-cost, medium performance ASICs. View full abstract»

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  • From silicon direct wafer bonding to surface nano-patterning: a way to innovative substrate elaboration

    Publication Year: 2009 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1686 KB) |  | HTML iconHTML  

    Self-assembled configurations of nanostructures are expected to play an increasingly important role in devices design, as an alternative to conventional microelectronics technology. Conventional techniques are generally limited by the lack of simultaneous control on positioning, density and size uniformity of the nanostructures. To overcome these problems a new substrate based on controlled direct twist wafer bonding and preferential chemical etching has been developed. View full abstract»

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  • High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits

    Publication Year: 2009 , Page(s): 1 - 2
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB) |  | HTML iconHTML  

    A low-cost and high-efficiency monocristalline silicon solar cell embedded in a CMOS circuit is proposed for ULP autonomous circuits. Based on a SOI wafer, a photovoltaic lateral diode is realized in the substrate using the fabrication steps of the FD SOI CMOS process of the superposed active circuitry. In case of front side illumination, we achieve 15% efficiency when no CMOS circuit is present, and 11% with an integrated structure in the silicon thin-film overlayer. An efficiency of 19.5% can be further reached in this last case when a 20 V bias difference is applied between the thin-film layer and the back contact to deplete the buried oxide / Si substrate interface. View full abstract»

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  • Thermal actuation of high frequency micromechanical resonators

    Publication Year: 2009 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB) |  | HTML iconHTML  

    This paper demonstrates the possibility of thermally actuating high-frequency micromechanical resonators. A single-mask fabrication process was used to fabricate high frequency single crystal silicon resonators on SOI substrates. The resonators where operated in a one-port configuration with parts of the resonator structure performing both thermal actuation and piezo-resistive sensing. Quality factors as high as 63,800 and resonance frequencies as high as 5.1 MHz have been demonstrated. It is shown theoretically and experimentally that thermal actuation is a more suitable approach for higher frequency resonators with dimensions in the lower microns and nanometer range. View full abstract»

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  • Overview of SOI technologies in China

    Publication Year: 2009 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB) |  | HTML iconHTML  

    Since the early 1980s, SOI technologies have been developed in China, where SIMOX, BESOI and SIMBOND are three main SOI materials technologies commercialized so far. In order to cut down the production cost, one has been trying to improve SIMOX technology by optimizing dose energy match to obtain high quality low-dose SIMOX wafer. By the end of 2005, BESOI SOI pilot line has been established and a new technology named SIMBOND technology has come to birth. Some innovative structures, like SiGe on insulator (SGOI) material, Strain Silicon on insulator (SSOI), AlN buried layer have also been investigated. Some commercial IC manufacturers start to design and produce SOI-based devices since 2002, when Shanghai Simgui Technology Co.,Ltd., was able to produced 100 mm, 125 mm and 150 mm SIMOX wafers and sold them to the semiconductor industry worldwide. This paper presents an outlook, the recent status and future prospect of SOI technologies in China. View full abstract»

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  • SRAM cell design considerations for SOI technology

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (729 KB) |  | HTML iconHTML  

    The performance and threshold-voltage variability of vertical SOI FinFETs are compared against those of planar fully depleted SOI MOSFETs with thin buried oxide, via three-dimensional device simulation with atomistic doping profiles and gate line-edge roughness, for the 22 nm CMOS technology node (25 nm gate length). Compact modeling is then used to estimate six-transistor SRAM cell performance metrics. Although FinFET technology offers superior performance, it is projected to have lower yield for comparable cell area, due to higher sensitivity to random and process-induced variations. View full abstract»

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  • Investigation of Static Noise Margin of FinFET SRAM cells in sub-threshold region

    Publication Year: 2009 , Page(s): 1 - 2
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    This paper investigates the Static Noise Margin (SNM) of FinFET SRAM cells operating in sub-threshold region using analytical solution of 3D Poisson's equation. An analytical SNM model for sub-threshold FinFET SRAM is demonstrated and validated by TCAD mixed-mode simulations. The stabilities of several novel independently controlled-gate FinFET SRAM cells are examined. Significant nominal RSNM improvements are observed in these novel cells. However, Write-ability is degraded and becomes an important concern for certain configurations in sub-threshold region. Our result indicates that R/W word-line (WL) voltage control technique is more effective than transistor sizing for improving the write-ability of the FinFET sub-threshold SRAM. While 6T cell is not a viable candidate for sub-threshold SRAM and 8T/10T cells must be used in bulk CMOS, our analysis establishes the feasibility and viability of 6T FinFET cells for sub-threshold SRAM applications. View full abstract»

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  • Analyze of temporal and random variability of a 45nm SOI SRAM cell

    Publication Year: 2009 , Page(s): 1 - 2
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    This paper presents the analysis of a 45 nm SOI SRAM cell variability including history effects and random variability. This leads to an accurate margin calculation. View full abstract»

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  • Impact of FinFET technology on 6T-SRAM performance

    Publication Year: 2009 , Page(s): 1 - 2
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    The area penalty, operation stability, and operation speed of the 20-nm-ZG FinFET SRAM were compared to those of the 20-nm-ZG bulk-planar SRAM. The FinFET SRAM with beta-ratio of 1 is expected to realize not only 7% less area penalty, but also the same or superior operational stability to that of the bulk-planar SRAM with beta-ratio of 2 because of less variability of the device performance. Also, it is expected that the operation speed of the FinFET SRAM is twice faster than that of the bulk planar SRAM. View full abstract»

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  • SRAM yield enhancement with thin-BOX FD-SOI

    Publication Year: 2009 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1425 KB) |  | HTML iconHTML  

    The performance and yield of 6-T SRAM cells implemented in thin-BOX FD-SOI technology vs. bulk technology are compared via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation. Performance is enhanced due to the elimination of channel dopants, and variation due to gate-LER and RDF are suppressed, for FD-SOI technology. For the same cell area (~0.07 mum2), comparable SNM can be achieved with 30% higher write current, and SRAM yield is enhanced by >2 sigma. View full abstract»

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  • Analysis of sense margin and reliability of 1T-DRAM fabricated on thin-film UTBOX substrates

    Publication Year: 2009 , Page(s): 1 - 2
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB) |  | HTML iconHTML  

    In this work, we have investigated the impact of back bias on the behavior of UTBOX IT-DRAM. The back bias impacts the behavior of undoped and doped channels differently thereby leading to different optimization schemes. It was also shown that by careful optimization of the bias conditions for both "1" but also "0", the device degradation due to hot carrier stress can be reduced significantly. View full abstract»

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  • Effect of source/drain asymmetry on the performance of Z-RAM® devices

    Publication Year: 2009 , Page(s): 1 - 2
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (459 KB) |  | HTML iconHTML  

    In this paper, the performance of Zero capacitor RAM (Z-RAMreg) devices, developed in a 45 nm SOI CMOS technology, is compared with both symmetric and asymmetric doping schemes. It is shown that the asymmetrically doped Z-RAM (AD) devices offer much better memory performance compared to the symmetrically doped Z-RAM (SD) devices. View full abstract»

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  • Wafer stacking: key technology for 3D integration

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    Wafer stacking technologies are today available for different 3D integration schemes. These are compatible with back end of line CMOS processes and packaging. Smart Stacking technology and copper to copper direct bonding processes were described as key technologies to realize dielectric or metallic bonding at room temperature and without applied pressure and/or additional glue layer. This results in a low stress stacked structure enabling high yield post process. Low temperature Smart Cuttrade is a third way to build 3D structures and bring opportunity to relax some stringent alignment constraints. View full abstract»

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  • Design and fabrication of SOI-based MEMS for mechanical memory storage

    Publication Year: 2009 , Page(s): 1 - 2
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    This paper presents the design and fabrication of SOI-based MEMS for mechanical memory storage (theoretical analysis and FEM) dedicated to reliability irradiative study. The memory data is the position of a mechanical ldquobi-stablerdquo. The data is written with thermal actuators and read with electrostatic comb electrodes. View full abstract»

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  • Effect of substrate rotation on the analog performance of triple-gate FinFETs

    Publication Year: 2009 , Page(s): 1 - 2
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    This paper studies the influence of the 45deg substrate rotation on the analog parameters of n-type and p-type triple-gate FinFETs with HfSiON gate dielectric, TiN gate material and undoped body. Tall triple-gate n-type and p-type FinFETs were fabricated on SOI wafers with 150 nm thick buried oxide. The fin height (HFin) is 65 nm for all devices. It has been demonstrated that the substrate rotation improves the transconductance of narrow nFinFETs increasing the unity gain frequency. The output conductance of nFinFETs is weakly sensitive to substrate rotation. The improvement of the transconductance is marginally transferred to the voltage gain, leading to similar values for both substrate orientations. For the pFinFETs the substrate rotation strongly degrades the carrier mobility and hence the transconductance, independently if narrow or wide devices are used. This degradation affects also the transconductance over drain current ratio and the voltage gain of narrow devices is smaller by 3 dB with respect to standard substrate orientation. View full abstract»

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  • A new technique for localized formation of SOI active regions

    Publication Year: 2009 , Page(s): 1 - 2
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    The oxidation of electrochemically etched porous silicon (PSi) has demonstrated success in the formation of device quality localized SOI for CMOS applications. A primary advantage with a localized SOI formation is the ability to integrate novel device structures and optoelectronics (i.e. optical switches, waveguides) with bulk silicon CMOS. The formation of PSi can be done selectively by controlling the Fermi level in areas to be etched or not etched, which is typically done by adjusting the level of doping. An alternative method is to introduce a reversible donor species such as protons or fluorine (this work) for the selective formation of islands of crystalline silicon surrounded by porous silicon. Implanted fluorine in silicon has demonstrated a donor effect upon annealing at low temperature (600degC), which is reversible as the fluorine outdiffuses during higher temperature annealing (1000degC). Crystalline silicon islands that were fabricated with this technique have a thickness of about 300 nm and are completely surrounded by oxidized porous silicon. Further study will investigate the device quality of the localized SOI structures for microelectronic and optoelectronic applications. View full abstract»

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