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3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date 28-30 Sept. 2009

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Displaying Results 1 - 25 of 83
  • Table of contents

    Publication Year: 2009 , Page(s): 1 - 15
    Save to Project icon | Request Permissions | PDF file iconPDF (79 KB)  
    Freely Available from IEEE
  • First integration of Cu TSV using die-to-wafer direct bonding and planarization

    Publication Year: 2009 , Page(s): 1 - 5
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (753 KB) |  | HTML iconHTML  

    Copper-filled Through-Si Vias (TSV) with diameters from 2 mum to 5 mum have been integrated in a die-to-wafer stack combining direct bonding and a planarization technique. TSVs were processed on chip backside after oxide bonding and substrate thinning. The results were compared to the ones achieved with a wafer-to-wafer test vehicle. It was demonstrated that die-to-wafer process developed for this integration does not impact TSV electrical and morphological properties. Moreover, no damage was observed on the stack during TSV process performed at 400 degC. This demonstration is the first step to validate the industrial compatibility between high density TSV process and die-to-wafer direct bonding and planarization techniques. With a resistance close to 150 mohm and a capacitance of about 30 fF, 3 mum-diameter TSV provides excellent electrical performance to heterogeneous 3D ICs. View full abstract»

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  • Heterogeneous integration technology for MEMS-LSI multi-chip module

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1815 KB) |  | HTML iconHTML  

    We developed novel interconnection technology for heterogeneous integration of MEMS and LSI multi-chip module, in which MEMS and LSI chips would be horizontally integrated on substrate and vertically stacked each others. The cavity chip composed of deep Cu TSV-beam lead wires was developed for interconnecting MEMS chips with high step height of more than 100 um. Fundamental characteristics were successfully obtained from pressure sensing MEMS chip with 360 mum thickness, which was connected to the substrate by the cavity chip. MEMS and LSI chips were vertically integrated by using the cavity chip without changes of chip design and extra processes. This interconnection technology can give strong solution for heterogeneous integration of MEMS and LSI chips multi-chip module. View full abstract»

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  • 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)

    Publication Year: 2009 , Page(s): 1 - 5
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using Die-to-Wafer Hybrid Collective bonding with Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 130 nm CMOS process on 200 mm wafers. The top die is thinned down to 25 mum and bonded to the landing wafer by a combination of polymer bonding and copper to copper thermocompression bonding. Top and landing wafers contain CMOS finished with 2 levels of metal in Copper/Oxide. Ring oscillators consisting of inverters distributed over both top and bottom dies interconnected through up to 40 TSVs are used to demonstrate the process. This paper focuses on integration issues solved during process development and electrical characterization of the obtained TSVs. View full abstract»

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  • 3D integrated circuits for lab-on-chip applications

    Publication Year: 2009 , Page(s): 1 - 8
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1034 KB) |  | HTML iconHTML  

    We present the designs of two new lab-on-chip devices that use 3D integrated circuit technology to support the separation, purification, and assay of biological particles. Our technique is based on a nanoscale implementation of dielectrophoresis. The key feature of our designs is the use of fabrication features found in 3D technology to create on-chip, nanoscale electrode arrays. The capabilities of our designs are demonstrated with multi-physics simulations of the chips sorting heterogeneous mixtures of HSV-1 capsids. View full abstract»

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  • Comparative analysis of two 3D integration implementations of a SAR processor

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (748 KB) |  | HTML iconHTML  

    When designing 3DICs there are five major issues that differ from 2D that must receive special attention: power delivery, thermal density, design for test, clock tree design and floorplanning. Power delivery in 3D must receive special attention as 3D designs have larger supply currents flowing through the package power delivery pins, along with a longer power delivery path than in comparable 2D system. Thermal density is an issue as 3D integrated chips will have more heat density and less capacity to remove heat than a comparable 2D chip. 3D clock tree distribution is much more difficult than in 2D because the most commonly used methodologies and design tools are geared towards 2D designs and process variation between the different tiers makes it harder to keep skew, jitter and power consumption down. Design for test is harder in 3D because 3D vias provide another point of failure and post fabrication repairs such as focused ion beam are more difficult to perform in 3D. Finally, floorplanning is drastically different in 3D than in 2D, and the four aforementioned issues must all be taken into account during 3D floorplanning. In this paper, all five design issues are explored in the context of a high-resolution memory-on-logic synthetic aperture radar (SAR) processor. The SAR processor is chosen specifically as it requires a significant amount of memory bandwidth that is best met with the high I/O bandwidth afforded by a 3D process. The issues are examined in the context of two implementations for two different 3D integration processes. The first implementation was done in MIT Lincoln Laboratory's 3D FDSOI 1.5 V three tier process and is currently in fabrication. The second design is currently in the design stage, and will be fabricated in two tiers of Chartered Semiconductor's 130 nm process 3D integrated with two tiers of high bandwidth DRAM using Tezzaron Semiconductor's vertical interconnection technology. View full abstract»

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  • Developments of novel vertically integrated pixel sensors in the high energy physics community

    Publication Year: 2009 , Page(s): 1 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (658 KB) |  | HTML iconHTML  

    High energy physics experiments at future particle accelerators set very demanding requirements on the performance of sensors and readout electronics. In these applications, silicon pixel detectors have to integrate advanced functionalities in the pixel cell itself, such as amplification, filtering, discrimination, time stamping, zero suppression and analog-to-digital conversion. This paper discusses how 3D vertical integration has the potential of providing a performance breakthrough in particle detection systems, and how the high energy physics community is organizing itself to meet the challenges of designing and fabricating vertically integrated devices. View full abstract»

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  • Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional Devices

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Patents (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    In the NEDO ldquoDream Chip Projectrdquo, ASET has been entrusted a project for developing, ldquoHigh-Density 3D-Integration Technology for Multifunctional Devicesrdquo. In the five year project from 2008 to 2012, development on technologies for design environment, interposer, chip test, cooling and stacking/bonding, thin wafer, and development on demonstration device and process are being performed. View full abstract»

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  • 3-D memory organization and performance analysis for multi-processor network-on-chip architecture

    Publication Year: 2009 , Page(s): 1 - 7
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the hard disk drives (HDD). Recent trends show that the solid state drives (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns. View full abstract»

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  • Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    This paper investigates the effect of the TSV resistance (RTSV) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation. When RTSV is 0 Omega, both the rising time (trise) from 0 V to 15 V and the energy during boosting (Eloss) of the output voltage (VOUT) are 10.6% and 6.6% of the conventional charge pump respectively. In contrast, when RTSV is 200 Omega, for example, trise is 30.1% and Eloss is 22.8% of the conventional charge pump. Besides, VOUT cannot be boosted above 20 V when RTSV is larger than 210 Omega. Therefore, in order to maintain the advantages of the boost converter over the charge pump in terms of trise and Eloss, the reduction of RTSV is very important. View full abstract»

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  • Miniature wireless activity monitor using 3D system integration

    Publication Year: 2009 , Page(s): 1 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (809 KB) |  | HTML iconHTML  

    Unobtrusive and continuous measurement of body parameters such as activity, movement, heartbeat, temperature and oxygen level in blood offers many opportunities in the health and fitness area: distant patient monitoring, rehabilitation support, activity stimulation, improved training programs in sports and even sleep management become possible. Enablers are small wireless body sensors that send the data to a computer or communication device. A key factor in many such applications is unobtrusiveness to the user. This requires miniaturization and, consequently, a high level of integration. Contrary to planar integration, 3D Si-level integration allows reduction of area and combination of different technologies. In the European project e-CUBES, a wireless activity monitor has been developed to demonstrate such a device can be realized by stacking integrated passives, embedded thinned IC's and SMDs. Besides the power management section, which is on the stacked PCB, the circuit is vertically integrated on a Si substrate in four layers: 1. integrated passives made by means of thin film dielectric and metallization processes, 2. embedded thinned (down to 20 mum) active dies and vertical interconnects, 3. re-distribution layer, and 4. SMD and flip-chip components. New in this concept are: combination of integrated passives and embedded active dies, an SMD component on top of an embedded micro processor die, and a one-chip embedded 17 GHz transmitter with a one-chip RF resonator. The antenna is mounted on the silicon backside and is fed by a slot coupling structure in the silicon to eliminate a wired connection to the antenna. Wireless battery charging and wireless on/off switching make it possible to put the system in a sealed package. By using 3D system integration, especially in applications containing RF functions, very low interconnect parasitics are achievable (as compared to wire bonding and even flip chip mounting). A successful demonstrator opens the way for thinni- ng more dies and stacking more layers without using through silicon vias, so standard bare wafers can be used without design changes. View full abstract»

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  • Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits

    Publication Year: 2009 , Page(s): 1 - 7
    Cited by:  Papers (20)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1226 KB) |  | HTML iconHTML  

    Through silicon via (TSV) is considered today as the third dimension interconnect opening new perspectives in term of 3D integration. Design, material and process recommendations are required to achieve 3D stacked dies and evaluate electrical performance of such chips. As a consequence, equivalent models of this incontrovertible key component become more and more mandatory. In this paper, a full parametric and frequency dependent model of high aspect ratio TSV is proposed based on both electromagnetic (EM) simulations and RF measurements. This model enables to extract TSV resistance, self inductance, oxide capacitance and parasitic elements due to the finite substrate resistivity. Its full compatibility with SPICE solvers allows the investigation of TSV impact on circuit performance. View full abstract»

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  • IC-package co-design and analysis for 3D-IC designs

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    The implementation of a 3D IC is typically accomplished by multiple design teams, in multiple geographies, using a variety of design tools. Types of designs include a simple package, with an analog die and a digital die placed side-by-side and more complex designs include die stacks of multiple analog or digital dies in face-to-face configurations connecting with micro bumps. Through-silicon-vias (TSV's) provide an extra level of complexity allowing an individual die to connect to the component below and above it in the stack. Interposers (silicon or organic) provide greater functional density, performance, and reduced cost. Also used in 3D-IC design are package-in-package, and package-on-package design styles. This paper discusses five key ingredients necessary for the successful design of a 3D-IC regardless which method above is used. These five items are (i) logical system-level integration to connect the system of ICs and packages, including support of layout-vs-schematic (LVS) checks (ii) physical co-design across IC and package boundaries through the sharing of component abstracts and cross-fabric functionality (iii) timing, power, and thermal-based design of the 3D-IC system in context of the package (iv) package-aware system simulation of 3D-IC circuitry (v) management of physical and logical engineering change orders (ECO's). View full abstract»

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  • Development of feed-forward design system for rapid SiP design

    Publication Year: 2009 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB) |  | HTML iconHTML  

    This paper proposes a feed-forward type of SiP (System-in-Package) design environment to improve SiP products design. The proposed environment enables accurate performance prediction including signal integrity and thermal dispersion at initial design stages. This design environment is contributes to finding design constraints from initial package layout at early design stages. By feeding these constraints forward to later detailed design stages, extra design iterations can be removed. As the results, we can reduce the whole SiP design period by half with keeping sufficient quality. View full abstract»

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  • Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (798 KB) |  | HTML iconHTML  

    New technologies for manufacturing 3D Stacked ICs offer numerous opportunities for the design of complex and efficient embedded systems. But these technologies also introduce many design options at system/chip design level, hard to grasp during the complete design cycle. Because of the sequential nature of current design practices, designers are often forced to introduce design margins to meet required specifications, resulting in sub-optimal designs. In this paper we introduce new design methodology and practical tool chain, called PathFinding Flow, that can help designers to easily trade-off between different system level design choices, physical design and/or technology options and understand their impact on typical design parameters such as cost, performance and power. Proposed methodology and the tool chain will be demonstrated on a practical case study, involving fairly complex Multi-Processor System-on-Chip using Network-on-Chip for communication medium. With this example we will show how High-Level Synthesis can be used to quickly move from high-level to RTL models, necessary for accurate physical prototyping for both computation and communication. We will also show how the possibility of design iteration, through the mechanism of feedback based on physical information from physical prototyping, can improve design performance. Finally, we will show how we can move in no time from traditional 2D to 3D design and how we can measure benefits of such design choice. View full abstract»

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  • 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1348 KB) |  | HTML iconHTML  

    Networks-on-chip (NoC) is emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoC). In traditional electronic NoCs, high bandwidth can be obtained by increasing the number of parallel metallic wires at the cost of more energy consumption. Optical NoCs are thus proposed to achieve low-power ultra-high-bandwidth data transmission in optical domain. Electronic control technology could be a complement to the optical networks. Besides NoCs, three-dimensional integrated circuits (3D ICs) are another attractive solution for system performance improvement by reducing the interconnect length. The investigation of using 3D IC as a platform for the realization of mixed-technology electronic-controlled optical NoC has not been addressed until recently. In this paper, we propose a 3D electronic-controlled optical NoC implemented in a TSV-based (through-silicon via) two-layer 3D chip. The upper device layer is an optical layer. It integrates an optical data transmission network, which is responsible for optical payload packets transmission. The bottom device layer is an electronic layer. It contains an electronic control network, which is used to route control packets and configure the optical network. We built an 8 times 8 mesh-based 3D optical NoC, with a 45 nm electronic control network. Power comparison with a matched 2D electronic NoC shows that the optical NoC can reduce power consumption significantly. For 2048 B packets, it has a 70% power reduction. End-to-end delay (ETE delay) and network throughput of the two NoCs under varying injection rates were evaluated for comparison. The results show that ETE delay of the optical NoC is much smaller than the electronic NoC when the network becomes congested. Take 4096 B packets for example, it is 18.7 mus in the optical NoC with an injection rate of 0.5, while 33.5 mus in the electronic one. A maximum throughput of 478 Gbps can be offered by the optical NoC using 32 Gbps optical link bandwi- dth. Because of the low resource utilization of circuit switching, the maximum throughput of the optical NoC is slightly lower than the electronic one. View full abstract»

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  • The benefits of 3D networks-on-chip as shown with LDPC decoding

    Publication Year: 2009 , Page(s): 1 - 8
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1297 KB) |  | HTML iconHTML  

    In this work we describe our network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC components built from detailed circuit simulation. It makes use of the architectural evaluator, which performs a detailed global interconnect analysis within the framework of industry-standard design tools. Using low density parity check decoding as a test vehicle, the NoC simulator is used in an NoC design study comparing 2D and 3D integrated circuits, and shows a method by which on-chip networks can be optimized. View full abstract»

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  • A tileable switch module architecture for homogeneous 3D FPGAs

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (4)  |  Patents (45)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    3D technology is an attractive solution for reducing wirelength in a field programmable gate array (FPGA). However, trough silicon vias (TSV) are limited in number. In this paper, we propose a tilable switch module architecture based on the 3D disjoint switch module for 3D FPGAs. Experimental results over 20 MCNC benchmarks show 62% reduction in the number of TSVs on average and small improvements in horizontal channel width and delay compared to the original 3D disjoint SM. View full abstract»

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  • A parallel ADC for high-speed CMOS image processing system with 3D structure

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1037 KB) |  | HTML iconHTML  

    In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-mum CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed in a two-dimensional 0.18-mum CMOS technology. The ADC design, including an 8-bit memory, a 6-bit memory, a subtraction circuit, and a comparator, occupies 100times100 mum2 area and 0.9 mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise. View full abstract»

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  • A capacitive coupling interface with high sensitivity for wireless wafer testing

    Publication Year: 2009 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (706 KB) |  | HTML iconHTML  

    A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver converts the data with various logic thresholds to that with optimum logic threshold. The receiver with the optimum logic threshold achieves the highest sensitivity of 25 mV at the data rate of 2 Gb/s in 0. 18 mum CMOS. The proposed receiver increases the communication distance over 4 times while providing tolerance against the distance-voltage-area variations. View full abstract»

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  • Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

    Publication Year: 2009 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB) |  | HTML iconHTML  

    Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs. View full abstract»

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  • Architectural evaluation of 3D stacked RRAM caches

    Publication Year: 2009 , Page(s): 1 - 4
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB) |  | HTML iconHTML  

    The first memristor, originally theorized by Dr. Leon Chua in 1971, was identified by a team at HP Labs in 2008. This new fundamental circuit element is unique in that its resistance changes as current passes through it, giving the device a memory of the past system state. The immediately obvious application of such a device is in a non-volatile memory, wherein high- and low-resistance states are used to store binary values. A memory array of memristors forms what is called a resistive RAM or RRAM. In this paper, we survey the memristors that have been produced by a number of different research teams and present a point-by-point comparison between DRAM and this new RRAM, based on both existent and expected near-term memristor devices. In particular, we consider the case of a die-stacked 3D memory that is integrated onto a logic die and evaluate which memory is best suited for the job. While still suffering a few shortcomings, RRAM proves itself a very interesting design alternative to well-established DRAM technologies. View full abstract»

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  • Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs

    Publication Year: 2009 , Page(s): 1 - 7
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (666 KB) |  | HTML iconHTML  

    Through-silicon via (TSV) is a critical interconnect element in 3D integration technology. TSVs introduce many new design challenges. In addition to competing with devices for real estate, TSVs can act as a major noise source throughout the substrate. We present in this paper a comprehensive study of TSV-induced noise as a function of several critical design and process parameters including substrate type, signal slew rate, TSV height, ILD thickness, and TSV-to-device and TSV-to-TSV spacing. We create a SPICE model for simulating TSV-to-device and TSV-to-TSV noise couplings in two different types of substrates: a lightly doped bulk substrate, and a lightly doped thin epitaxial layer on top of a heavily doped bulk. Our SPICE model provides small error when compared with a detailed finite element analysis method. Our findings show the importance of using a grounded backplane in reducing noise and how coaxial TSVs further mitigate TSV-induced noise. View full abstract»

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  • Influence of 3D integration on 2D interconnections and 2D self inductors HF properties

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    In this study, effects due to 3D level stack on HF properties of 2D interconnections and 2D self inductors integrated in the back end of line (BEOL) are investigated. Self-inductors are considered as self coupled interconnects around a long loop where the magnetic field is confined. So, simple and coupled 2D interconnections of BEOL are studied in order to determine the influence of the silicon substrate stack on propagation delay, crosstalk and factor quality of 2D interconnects and self-inductors. View full abstract»

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  • Impacts of though-DRAM vias in 3D processor-DRAM integrated systems

    Publication Year: 2009 , Page(s): 1 - 6
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (680 KB) |  | HTML iconHTML  

    As a promising option to address the memory wall problem, 3D processor-DRAM integration has recently received many attentions. Since DRAM tiers must be stacked between the processor tier and package substrate, we must fabricate a large number of through-DRAM through-silicon vias (TSVs) to connect the processor tier and package for power and I/O signal delivery. Although such through-DRAM TSVs will inevitably interfere with DRAM design and induce non-negligible power consumption overhead, little research has been done to study how to allocate these TSVs on the DRAM tiers and analyze their impacts. To address this open issue, this paper first presents a through-DRAM TSV allocation strategy that fits well to the regular DRAM architecture. To demonstrate this design strategy and evaluate trade-offs involved, we develop a CACTI-based modeling tool to carry out extensive simulations over a wide range of design parameters. View full abstract»

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