By Topic

Mixed Design of Integrated Circuits & Systems, 2009. MIXDES '09. MIXDES-16th International Conference

Date 25-27 June 2009

Filter Results

Displaying Results 1 - 25 of 167
  • [Front and back covers]

    Publication Year: 2009 , Page(s): c1 - c2
    Save to Project icon | PDF file iconPDF (131 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2009 , Page(s): 1 - 2
    Save to Project icon | PDF file iconPDF (123 KB)  
    Freely Available from IEEE
  • Preface

    Publication Year: 2009 , Page(s): 3 - 4
    Save to Project icon | Request Permissions | PDF file iconPDF (228 KB)  
    Freely Available from IEEE
  • International Programme Committee

    Publication Year: 2009 , Page(s): 5 - 6
    Save to Project icon | PDF file iconPDF (35 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2009 , Page(s): 7 - 15
    Save to Project icon | PDF file iconPDF (66 KB)  
    Freely Available from IEEE
  • [Blank page]

    Publication Year: 2009 , Page(s): 16
    Save to Project icon | PDF file iconPDF (6 KB)  
    Freely Available from IEEE
  • General invited papers

    Publication Year: 2009 , Page(s): 17 - 18
    Save to Project icon | PDF file iconPDF (10 KB)  
    Freely Available from IEEE
  • A 0.13 µm SiGe BiCMOS technology for mm-wave mixed-signal applications

    Publication Year: 2009 , Page(s): 19 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (369 KB) |  | HTML iconHTML  

    We present a SiGe BiCMOS technology featuring high-speed HBTs with peak transit frequencies fT of 240 GHz and maximum oscillation frequencies fmax of 330 GHz at breakdown voltages of BVCEO = 1.7 V. The high-speed HBTs are integrated in a 0.13 mum RF CMOS process along with high-voltage HBTs (fT = 40 GHz, fmax = 120 GHz, BVCEO = 4.5 V) and a set of passive RF components. CML ring oscillator gate delays of 2.9 ps are demonstrated. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comparison of fault-tolerance techniques for massively defective fine- and coarse-grained nanochips

    Publication Year: 2009 , Page(s): 23 - 30
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (167 KB) |  | HTML iconHTML  

    The fundamental question addressed in this paper is how to maintain the operation dependability of future chips built from forthcoming nano- (or subnano-) technologies characterized by the reduction of component dimensions, the increase of atomic fluctuations and the massive occurrence of physical defects. We focus on fault tolerance at the architectural level, and especially on fault-tolerance approaches, which are based on chip self-diagnosis and self-reconfiguration. We study test and reconfiguration methodologies in massively defective nanoscale devices, either at fine granularity field programmable devices or at coarse granularity multi-core arrays. In particular, we address the important question of up to which point could future chips have self-organizing fault-tolerance mechanisms to autonomously ensure their own dependable operation. In the case of FPGAs, we present known fault tolerant approaches and discuss their limitations in future nanoscale devices. In the case of multicore arrays, we show that such properties as self-diagnosis, self-isolation of faulty elements and self-reorganization of communication routes are possible. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Device level support for emerging CMOS technologies

    Publication Year: 2009 , Page(s): 31 - 32
    Save to Project icon | Request Permissions | PDF file iconPDF (10 KB)  
    Freely Available from IEEE
  • Analysis of 3D current flow in undoped FinFETs and approaches for compact modeling

    Publication Year: 2009 , Page(s): 33 - 38
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (246 KB) |  | HTML iconHTML  

    Current flow in FinFETs is strongly influenced by 3D effects. In this paper, based on 3D TCAD results the current path is analyzed from subthreshold to above threshold operation. A new method to extract the pinch-off point in saturation is presented. Furthermore, based on a 3D analytical model for the electrostatic potential at the barrier threshold conditions and subthreshold slopes at different positions within the channel cross section are analyzed. A way is proposed how 1D current equations can be superposed to result in a semi-empirical model for the channel current. One part of the model dominates the subthreshold behavior, whereas the second part represents the current well above threshold at the silicon surface. This simple model helps to interpret the influence of geometry effects on the channel current. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact device modeling for established and emerging technologies with the Qucs GPL circuit simulator

    Publication Year: 2009 , Page(s): 39 - 44
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (705 KB) |  | HTML iconHTML  

    Current trends in circuit simulation technology suggest a strong movement towards software packages which promote equation-defined compact semiconductor device modeling and circuit macromodeling. Today, the Verilog-A subset of the Verilog-AMS hardware description language is one of the most popular choices of hardware description language for model construction. The ldquoQuite universal circuit simulatorrdquo (Qucs) is a GPL software package supporting the MOS-AK Verilog-A standardization initiative. This paper outlines how equation centered modeling can act as a strong support vehicle for the construction of new device models and circuit macromodels. The material presented in the text explores the relationship between device model specifications, equation-defined devices and Verilog-A code generation. A number of examples demonstrate the capabilities of the model construction tools implemented by the Qucs development team. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Continuous compact model for MuGFETs simulations

    Publication Year: 2009 , Page(s): 45 - 50
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (816 KB) |  | HTML iconHTML  

    This work presents an analytical continuous compact model for FinFETs which is based on the doped symmetrical double gate model. Our model covers a wide range of technological parameters including different doping concentrations from 1 times 1014 to 3 times 1018 cm-3, short channel effects (down to 80 nm) and high temperatures (up to 200degC). Recently, we have also implemented and validated it in a Verilog-A module. Good agreements between device measurements and simulations have been obtained in all operation regions and at different temperatures. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of pixel readout integrated circuits in submicron technology to minimize the mismatch effects

    Publication Year: 2009 , Page(s): 51 - 54
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    Modern pixel detectors working in single photon counting mode require fast, high density readout electronics. The large readout ASIC for these detectors consists of several thousands of readout pixels, while the area of a single pixel containing both analog and digital blocks is often less than 100times100 mum2 with the power consumption limited to a few tens of muW. To ensure the full functionality of a single readout pixel (amplification, filtering and data storage) VLSI designers more often use submicron CMOS technologies (0.25 mum - 90 nm). However, strict power and area limitations for the readout electronics cause that one of the most demanding factors during the design process is the uniformity of analog parameters for large pixel matrix. The transistors in analog blocks often work in weak or moderate inversion where effects of variability of the transistor parameters become more visible. Additionally, in large pixel matrix containing several thousands of pixel cell units (PCU) one has to take into account possible voltage drops on power supply and reference lines. The above effects can be reduced by the careful design of the PCU itself with a strict power limitation, proper power supply and reference distribution together with adding an offset correction circuit working in each channel independently. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FinFET compact modeling and parameter extraction

    Publication Year: 2009 , Page(s): 55 - 60
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (153 KB) |  | HTML iconHTML  

    In this paper, we present a FinFET compact model and its associated parameter extraction methodology. This explicit model accounts for all major small geometry effects and allows accurate simulations of both n- and p-type FinFETs. The model core is physics-based (long-channel model) and some semiempirical corrections are introduced in order to accurately simulate the behavior of ultrashort (L = 25 nm) and ultrathin (WSi = 3 nm) FinFETs. The parameter extraction relies on a software suite allowing an automatic parameter extraction. In this work, the development of our parameter extraction procedure is based on 3-D simulation results. The optimization of parameters related to quantum effects, short-channel effects and channel length modulation illustrates the methodology of parameter extraction. Finally, we compare the FinFET characteristics (drain current and small signal parameters) obtained by our explicit compact model with 3-D numerical simulations for different Fin widths and channel lengths. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fluctuations of electrical characteristics of FinFET devices

    Publication Year: 2009 , Page(s): 61 - 66
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1361 KB) |  | HTML iconHTML  

    FinFET devices are extensively investigated due to the prospects for application in the sub-100 nm CMOS integrated circuits fabrication. Small size of the FinFETs and the properties of technological processes strongly influence their electrical characteristics. The random variations of the characteristics lead to a mismatch effect critical from the viewpoint of design and fabrication. In the paper different types of the variations of FinFET characteristics are discussed. The considerations are illustrated with measurement data of a series of devices and with distributions of the parameters extracted from these data. Possible effect of the parameter variability on digital cell parameters is analyzed. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Global extraction of MOSFET parameters using the EKV model: Some properties of the underlying optimization task

    Publication Year: 2009 , Page(s): 67 - 72
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    We consider global extraction of parameters of the MOSFET structure with the use of the EKV model. The extraction is defined as a task of minimizing the approximation error which is the discrepancy between the measured and model-generated I-V curves. As a result of the minimization, a set of parameter values is obtained where the minimum is observed. These values are treated as the extraction results. In this study we assume certain values of MOSFET parameters, we generate I-V curves, then we treat them as is they were measurements and try to perform extraction. Thus we are able to judge about the quality of results. We study the structure of local minima of the approximation error. We show that the error function has many local minima, and the global minimum appears for true parameter values. We investigate the relation between the approximation error and the error of extracted parameter values. We also show how measurement errors introduce ambiguities in the extraction results. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Risk management of LSI design by spice parameter QA methodology

    Publication Year: 2009 , Page(s): 73 - 76
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (630 KB) |  | HTML iconHTML  

    Determination of Spice model parameter requires significant technology challenges for successful LSI design. Especially, MOSFET model parameters, such as ones used in BSIM, PSP and HiSIM, have to guarantee the physical consistency, experimental accuracy, smoothness of conductance and computational efficiency. To verify these requirements on the Spice parameters, various QA methodology and tools have been proposed and evaluated their ability. However, very few works have been done to conduct such parameter QA works systematically, so far. To address this issue, we have developed the spice parameter QA methodology, and practice it using for plural parameters through spice parameter extraction contest. In this paper, we will show an interesting experiment by spice parameter extraction contest. Six challengers accepted this contest work and provided their original parameters for BSIM4.5. They are actually different parameters, depending on the engineer's carrier and so-on. We have evaluated each of the parameter quality based on our proposed methodology. By ranking the quality fairly and comprehensively, we have analyzed the weakness and strength of the extracted parameter sets. Details of the parameter QA results will be discussed. On the other hand, we suggest that its quantitative results have a potential ability to decrease excessive margin avoiding risk of LSI design. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The surface-potential-based compact model HiSIM-SOI for Silicon-On-Insulator MOSFETs

    Publication Year: 2009 , Page(s): 77 - 81
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    The compact circuit simulation model HiSIM-SOI for silicon-on-insulator (SOI)-MOSFET solves the three surface potentials of the SOI-MOSFET accurately without sacrificing simulation time. Depending on device structure and biasing conditions the SOI-MOSFET device may operate in partially depleted (PD) or fully depleted (FD) modes and a smooth transition between these modes is prerequisite for a good compact model. HiSIM-SOI is verified to fulfill these requirements and to cover all the operational regions of SOI-MOSFETs. It is also demonstrated that the floating-body effect, which determines key SOI-MOSFET properties like the kink effect or the history effect, can be accurately captured within the model calculation in a simple way without introducing an additional node in the compact model. Furthermore, HiSIM-SOI correctly reproduces measured data of both body-contact and floating-body devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Blank page]

    Publication Year: 2009 , Page(s): 82
    Save to Project icon | PDF file iconPDF (6 KB)  
    Freely Available from IEEE
  • EuCard-European coordination for accelerator research and development

    Publication Year: 2009 , Page(s): 83 - 84
    Save to Project icon | Request Permissions | PDF file iconPDF (10 KB)  
    Freely Available from IEEE
  • A novel approach for automatic control of piezoelectric elements used for Lorentz force detuning compensation

    Publication Year: 2009 , Page(s): 85 - 88
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (191 KB) |  | HTML iconHTML  

    Linear accelerators such as free electron lasers (FELs) use superconducting (SC) resonant cavities to accelerate electron beam to high energies. TESLA type resonators are extremely sensitive to detuning induced by mechanical deformations-Lorentz force detuning (LFD), mainly due to the extremely high quality factor (Q) of the 1.3 GHz resonance mode, in the range of 106. The resulting modulation of a resonance frequency of the cavity makes power consumption and stability performances of the low-latency radio frequency (LLRF) control more critical. In order to minimize the RF control efforts and desired stabilities, the fast piezoelectric actuators with digital control systems are commonly used. The paper presents a novel approach for automatic control of piezoelectric actuators used for compensation of Lorentz force detuning, the practical application and carried out tests in accelerating module ACC6 in Free-Electron Laser in Hamburg (FLASH). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compiler-level implementation of single Event Upset errors mitigation algorithms

    Publication Year: 2009 , Page(s): 89 - 92
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (197 KB) |  | HTML iconHTML  

    Single event upset is a common source of failure in microprocessor-based systems working in environment with increased radiation level especially in places like accelerators and synchrotrons, where sophisticated digital devices operate closely to the radiation source. One of the possible solutions to increase the radiation immunity of the microprocessor systems is a strict programming approach known as the software implemented hardware fault tolerance. Unfortunately, a manual implementation of SIHFT algorithms is difficult and can introduce additional problems with program functionality caused by human errors. In this paper author presents new approach to this problem, that is based on the modifications of the source code of the C language compiler. Protection methods are applied automatically during source code processing at intermediate representation of the compiled program. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Development and tests of PWM amplifier for driving the piezoelectric elements

    Publication Year: 2009 , Page(s): 93 - 96
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (303 KB) |  | HTML iconHTML  

    The paper describes the design and research work carried out to prepare the prototype of pulse amplifier. The work was aimed to describe main operational parameters of PWM amplifiers enabling using them to control the piezoelectric actuators used for active compensation of Lorentz force detuning of superconducting cavities. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Diagnostic application for development of custom ATCA Carrier Board for LLRF

    Publication Year: 2009 , Page(s): 97 - 102
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    The Advanced Telecommunications Computing Architecture (ATCA) standard describes a powerful and efficient platform. With multiple integrated solutions like redundancies and intelligent control mechanisms this technology is characterized with reliability estimated at the level of 99.99999 percent. These features make the standard perfect for use in projects like the free electron laser in Hamburg (FLASH) and the X-ray free electron laser (X-FEL) in order to help them meet the requirements of high availability and reliability. The ATCA standard incorporates advanced control systems defined in the intelligent platform management interface (IPMI) specification as one of the key elements. The entire ATCA implementation retains its functionality as long as the IPMI remains operational. The complexity level of the application increases, which results in preparing it to run and debugging being more difficult to perform. At the same time, only scrupulous elimination of any kind of possible deficiencies can enable the ATCA implementation to offer the desired level of reliability. Thus, diagnostics become crucial, which creates a need for additional tools performing these tasks during the preparations of both hardware and software for the ATCA application. The paper presents application aiding in development of the prototype carrier board by enabling the user of external PC station to perform diagnostic and control activities over the board. It helps in examining all its components at the stage of running the board, as well as in further operation analysis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.