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2009 IEEE International Workshop on Memory Technology, Design, and Testing

Date Aug. 31 2009-Sept. 2 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - vi
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  • Foreword

    Publication Year: 2009, Page(s): vii
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  • Organizing Committee

    Publication Year: 2009, Page(s): viii
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  • Program Committee

    Publication Year: 2009, Page(s): ix
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  • list-reviewer

    Publication Year: 2009, Page(s): x
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  • Keynote Speech 1

    Publication Year: 2009, Page(s):xi - xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (151 KB) | HTML iconHTML

    Summary form only given. SRAM designers have recognized that threshold-voltage (Vth) variation is the most serious issue to enable further area and operating-voltage (Vdd) scaling. Various circuit design techniques to address this issue have attracted much attention at leading edge conferences since 65 nm process node, but their extendibility for 22 nm and beyond have not been reviewed and compare... View full abstract»

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  • Keynote Speech 2

    Publication Year: 2009, Page(s):xiii - xv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    With today manufacturing technology, it is not possible to eliminate all defects so that every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. In this situation, the test process consists in identifying defective circuits by applying test vectors in such a way that the presence of the defect can be observed on some... View full abstract»

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  • Invited Talk 1

    Publication Year: 2009, Page(s): xvi
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    Summary form only given. The increasing demands on embedded non-volatile memories in logic circuits spurred many research activities in the development of low-cost, highly scalable and compatible solutions. Besides full compatibility to standard CMOS logic process, low voltage and power operations, small cell size, and fast programming and accessing speed are all desirable features in logic NVMs. ... View full abstract»

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  • Invited Talk 2

    Publication Year: 2009, Page(s): xvii
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    Summary form only given. The complexity of today's applications makes design and scaling of technology ever increasingly difficult and very challenging. The challenges are not just from scaling and improving the performance but also with the increased integration density of devices on a SoC and enabling complex functions. Newer memory technologies need to address to improve the integration density... View full abstract»

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  • Invited Talk 3

    Publication Year: 2009, Page(s): xviii
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    Summary form only given. Next-generation nonvolatile memories and three-dimensional integrated circuits (3DIC) have been the research focus of Electronics and Optoelectronics Research Laboratories at Industrial Technology Research Institute. The planning and some recent progress of nonvolatile memory research, particularly on RRAM and 3DIC at ITRI EOL will be briefly reviewed. View full abstract»

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  • Tutorial

    Publication Year: 2009, Page(s):xx - xxii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (119 KB)

    This tutorial is aimed at the system engineer, who has to deal with DRAMs in an application. DRAMS come in densities from 512 MBit to 4 GBit, operating voltage ranges between 1.35 V and 2.5 V, as components and modules with 4..64 data lines and have a leaky capacitor for storage. The memory interface has data rates from 233 MBit/s/pin up to 2 GBit/s/pin. Fundamentals of memories are covered. Theor... View full abstract»

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  • Voltage-Driven Multilevel Programming in Phase Change Memories

    Publication Year: 2009, Page(s):3 - 6
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB) | HTML iconHTML

    In the multilevel (ML) storage approach, any single cell in a memory array is programmed to one among n>2 predetermined different states. To exploit the ML approach in the case of phase change memories (PCMs), it is necessary to accurately program the active chalcogenide layer to a number of different partially crystallized states so as to precisely allocate the electrical resistance of the cel... View full abstract»

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  • Circuit Design for Bias Compatibility Investigation of Bulk FinFET Based Floating Body RAM

    Publication Year: 2009, Page(s):7 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (647 KB) | HTML iconHTML

    Single transistor Floating Body Random Access Memories (FB-RAMs) are foreseen to bring size and speed benefits and have the potential to replace existing DRAMs. However, the implementation in matrix is complex because the voltages applied to access one cell can disturb the state of other cells. We propose an approach at circuit level to provide compatible bias conditions and to explore further on ... View full abstract»

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  • A New SRAM Cell Design for Both Power and Performance Efficiency

    Publication Year: 2009, Page(s):13 - 19
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (337 KB) | HTML iconHTML

    This paper presents a new six-transistor static random access memory (6 T SRAM) cell with significantly reduced power consumption that achieves high read and write performance. Unlike traditional 6 T SRAMs, this study proposes an asymmetric 6 T SRAM which uses a single line to implement read or write operations without reducing performance. This design not only reduces power consumption, but also ... View full abstract»

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  • A Wide-VDD Embedded SRAM for Dynamic Voltage Asynchronous Systems

    Publication Year: 2009, Page(s):20 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB) | HTML iconHTML

    Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous SRAM. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across ... View full abstract»

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  • Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-? Metal-Gate Devices

    Publication Year: 2009, Page(s):27 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB) | HTML iconHTML

    The contact resistance of CMOS device increases sharply withtechnology scaling, especially in SRAM cells with minimum size and/or sub-groundrule devices. Meanwhile, VT drifts caused by Negative-Bias Temperature Instability (NBTI) and Positive-Bias Temperature Instability (PBTI) degrade stability, margin, and performance of nanoscale SRAM with high-kappa metal-gate devices over the lifetime of usag... View full abstract»

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  • High-k Hf-Based Nanocrystal Memory Capacitors with IrOx Metal Gate for NAND Application

    Publication Year: 2009, Page(s):31 - 33
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    The memory characteristics of atomic layer deposited high-kappa Hf-based nanocrystals embedded in high-kappa Al2O3 films in an n-Si/SiO2/HfO2/high-k nanocrystal/Al2O3/IrOx memory structure have been investigated. The high-k nanocrystals can be formed after high temperature (> 900degC) annealing process. The high-k nano... View full abstract»

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  • A Micro-Watt Multi-port Register File with Wide Operating Voltage Range

    Publication Year: 2009, Page(s):34 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB) | HTML iconHTML

    In this paper, a micro-watt multi-port register file with wide operating voltage range for micro-power applications is presented. Multibank architecture for simultaneous access with collision detecting technique is proposed. The architecture has been analyzed under wide operating voltage range between 1 V to 0.25 V with varies process corner. Negative voltage write scheme ensures successful write ... View full abstract»

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  • Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency

    Publication Year: 2009, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (690 KB) | HTML iconHTML

    Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content ad-dressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliabi... View full abstract»

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  • Variability-Tolerant Binary Content Addressable Memory Cells

    Publication Year: 2009, Page(s):44 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (222 KB) | HTML iconHTML

    Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes four-types of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write ... View full abstract»

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  • Memory Repair by Die Stacking with through Silicon Vias

    Publication Year: 2009, Page(s):53 - 58
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (459 KB) | HTML iconHTML

    As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes more difficult. It seems inevitable that during the ramp-up period, the initial manufacturing yield will be lower, and it takes more time and effort to improve the yield to a reasonable level. Although redundancy can be used to improve the yield eventually, the reserved spares m... View full abstract»

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