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Embedded and Real-Time Computing Systems and Applications, 2009. RTCSA '09. 15th IEEE International Conference on

Date 24-26 Aug. 2009

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Displaying Results 1 - 25 of 69
  • [Front cover]

    Page(s): C1
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - ix
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  • Foreword

    Page(s): x
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  • Organization Committee

    Page(s): xi - xiii
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  • External reviewers

    Page(s): xiv
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  • Sponsors

    Page(s): xv
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  • Branch Target Buffers: WCET Analysis Framework and Timing Predictability

    Page(s): 3 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis has to consider microarchitectural features like caches, branch prediction, and branch target buffers (BTB). We propose a modular WCET analysis framework for branch target buffers (BTB), which allows for easy adaptability to different BTBs. As an example, we investigate the Motorola PowerPC 56x family MPC56x, which is used in automotive and avionic systems. On a set of avionic and compiler benchmarks, our analysis improves WCET bounds on average by 13% over no BTB analysis. Capitalizing on the modularity of our framework, we explore alternative hardware designs. We propose more predictable designs, which improve obtainable WCET bounds by up to 20%, reduce analysis time considerably, and simplify the analysis. We generalize our findings and give advice concerning hardware used in real-time systems. View full abstract»

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  • An Efficient Algorithm for Parametric WCET Calculation

    Page(s): 13 - 21
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (213 KB) |  | HTML iconHTML  

    Static WCET analysis is a process dedicated to derive a safe upper bound of the worst-case execution time of a program. In many real-time systems, however, a constant global WCET estimate is not always so useful since a program may behave very differently depending on its configuration or mode. A parametric WCET analysis derives the upper bound as formula rather than a constant. This paper presents a new efficient algorithm that can obtain a safe parametric estimate of the WCET of a program. This algorithm is evaluated on a large set of benchmarks and compared to a previous approach to parametric WCET calculation. The evaluation shows that the new algorithm, to the cost of some imprecision, scales much better and can handle more realistic programs than the previous approach. View full abstract»

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  • Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs

    Page(s): 22 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB) |  | HTML iconHTML  

    Many WCET analysis tools developed in academia integrate WCET analysis into program compilation, either to transform flow information extracted from the source code level to the object code level, or to perform flow analysis on a special intermediate representation. This integration increases analysis complexity, forces software developers to use a special compiler, and thus, strongly limits the usability of the tools in practice. Motivated by this limitation in the existing flow analysis approaches, this paper presents a more efficient approach, that performs flow analysis on the intermediate source code (ISC), transformed from the original source code. ISC retains the functional behavior and executability of the original source code but has a structure close to the object code. This low level structure facilitates the transformation of the flow facts, extracted from the ISC, down to the object code level. In the whole approach, no modification of standard tools is needed. View full abstract»

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  • Dynamic Hinting: Real-Time Resource Management in Wireless Sensor/Actor Networks

    Page(s): 31 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB) |  | HTML iconHTML  

    Increasing complexity of today's WSAN applications can rapidly result in reduced real-time capabilities of the underlying sensor nodes. Using preemptive operating systems is one way to retain acceptable reactivity within highly dynamic environments but commonly leads to severe resource management problems. We present the dynamic hinting approach for maintaining good system reactivity by efficient combination of preemptive task scheduling and cooperative resource allocation. With respect to task priorities, our technique significantly improves classical methods for handling priority inversions under both short- and long-term resource allocations. Furthermore, we facilitate compositional software design by providing independently developed tasks with runtime information for yet collaborative resource sharing. In some cases this even allows to improve blocking delays as otherwise imposed by bounded priority inversion. View full abstract»

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  • Multi-path Planning for Mobile Element to Prolong the Lifetime of Wireless Sensor Networks

    Page(s): 41 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (266 KB) |  | HTML iconHTML  

    Mobile elements, which can traverse the deployment area and convey the observed data from static sensor nodes to a base station, have been introduced for energy efficient data collection in wireless sensor networks (WSNs). However, most existing solutions only plan a single path for the mobile element, which may lead to quick energy depletion for the sensor nodes that are far away from the path. In this paper, for data collection in WSNs, we study the multi-path planning (MPP) problem for the mobile element to prolong the lifetime of WSNs. Observing the intractability of the problem, two MPP heuristic schemes, namely fixed-K and adaptive-K, are proposed. The central idea of these schemes is to plan multiple paths and have the mobile element follow them in turn to balance the energy consumption on individual sensor nodes, thus extending the lifetime of WSNs. The proposed schemes are evaluated through extensive simulations. The results show that, compared to that of the single path solution, the multi-path approaches can extend the lifetime of WSNs by up to four times. Moreover, the adaptive-K scheme treats the sensor nodes more fairly with less variation on their energy consumptions. View full abstract»

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  • PLL Based Time Synchronization in Wireless Sensor Networks

    Page(s): 51 - 56
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    Time synchronization is a key component in numerous wireless sensor network applications. Most of the current software based time synchronization approaches suffer from communication overhead and lack of scalability. In this paper, we propose a hardware based approach based on voltage controlled crystal oscillator and phase locked loop techniques to achieve and maintain sub microsecond level time synchronization. Our approach does not require any exchange of synchronization messages with neighboring nodes. Performance evaluations in Matlab demonstrate sub microsecond accuracy and robustness to infrequent loss of WWVB signal. The principle advantages of our solution is scalability, accuracy, and low communication overhead. View full abstract»

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  • Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration

    Page(s): 59 - 68
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    Resources in contemporary systems-on-chip (SoC) are shared between applications to reduce cost. Access to shared resources is provided by arbiters that require a small hardware implementation and must run at high speed. To manage heavily loaded resources, such as memory channels, it is also important that the arbiter minimizes over allocation. A Credit-Controlled Static-Priority (CCSP) arbiter comprised of a rate regulator and a static-priority scheduler has been proposed for scheduling access to SoC resources. The proposed rate regulator, however, is not straight-forward to implement in hardware, and assumes that service is allocated with infinite precision. In this paper, we introduce a fast and small hardware implementation of the CCSP rate regulator and formally prove its correctness. We also show an efficient way of representing the allocated service in hardware with finite precision. Based on this representation, we define and evaluate two allocation strategies, and derive tight bounds on their respective over allocations. We show that increasing the precision of the implementation results in an exponential reduction in maximum over allocation at the cost of a linear increase in area. We demonstrate that the allocation strategy has a large impact on the allocation success rate for use cases with high load. Finally, we compare CCSP to traditional frame-based approaches and conclude that having a fine allocation granularity that is decoupled from latency is essential to manage highly loaded resources in real-time systems. View full abstract»

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  • Zero-Buffer Inter-core Process Communication Protocol for Heterogeneous Multi-core Platforms

    Page(s): 69 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    Executing functional components in pipeline on heterogeneous multi-core platforms can greatly improve the parallelism but require great amount of data communication among processes and threads. Our studies showed that existing inter-process/thread communication protocols consist of many unnecessary memory copies and prolong the execution of the applications on heterogeneous multi-core platforms. NTU ICPC uses polling-base mail notification to unnecessary context switches, and designs a memory subsystem to manage the input and output data between the senders and receivers. The protocol was implemented and evaluated on heterogeneous multi-core platform for several use scenario including H.264 encoding process. The evaluation results show that the communication overhead on sender side is independent of the data size and that on receiver side is greatly shortened, compared to several inter-process Communication (IPC) protocols including mailbox, message queue, and shared memory. When encoding H.264 video clips, the encoding frame rates increase for more than 30%. Our experiments also showed that the communication overhead accounts 40% to 50% of total execution time in average for H.264 video decoding applications. In this paper, we present the design and implementation of zero-buffer inter-core process communication protocol, named NTU ICPC, to shorten communication overhead for pipeline executed applications on heterogeneous multi-core platforms. View full abstract»

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  • On Component-Based Development and High-Integrity Real-Time Systems

    Page(s): 79 - 84
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    Component-based development approaches are becoming commonplace in business applications: they must therefore have some merit. In striking contrast to that, their penetration in the industrial practice of high-integrity real-time systems is virtually nil. This oddity needs explaining. In this paper we reflect on the presumed reasons of this situation and elaborate on possible systematic remedies. We contend that in order to make it in the high-integrity real-time systems domain, a component-based development approach must be constructed around four fundamental ingredients: a component model, a computational model, a programming model, and a congruent execution platform. Of those four ingredients, the computational model is key to bridging the lack of architectural concerns that afflicts the real-time workload models. We relate the component model to real-time systems theories. We illustrate how those elements could be neatly encased in a development method centred on model-driven engineering. We conclude by noting that the incorporation of component-based development methods, augmented with the cited ingredients, into model-driven engineering promises important savings in the development time and cost and also facilitates the industrial adoption of state-of-the-art techniques off real-time theory. View full abstract»

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  • Towards Hardware Support for Common Sensor Processing Tasks

    Page(s): 85 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (283 KB) |  | HTML iconHTML  

    Sensor processing is a common task within many embedded system domains, such as in control systems, the sensor feedback is used for actuator control. In this paper we have surveyed several embedded system domains, and extracted kernels of computation that are common across applications within a given domain, or across domains. We have shown that adding architectural support for executing these common kernels of computation can yield an overall better system performance. We present a light weight, simplified prototype of a sensor processing unit (SPU) that offloads these computations from the main arithmetic logic unit (ALU) of an embedded processor, and that accesses sensor data in a low latency manner. Our SPU prototype shows an average speed up factor of 2.48 over executing these kernels on an embedded PowerPC processor. A large portion of this speed up is due to our low latency method for accessing sensor data. Isolating our speed up to purely computation still shows an average speed up factor of 1.38 for these kernels. View full abstract»

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  • F-Model: Model of Modular Robot Based on Functional Component

    Page(s): 91 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5197 KB) |  | HTML iconHTML  

    With the rapid development of robot technology, It is becoming increasingly difficult to design and maintain robot systems. This makes it necessary to reuse hardware and software modules to lower the difficulty and the cost for the robot system design. In this paper we present a model of modular robot-F-Model. It uses functional component modules to construct function-oriented robot applications. Firstly the background of modular robot system is analyzed, and several basic conceptions in F-Model are elaborated. Then, the main framework of the model is constructed, and the model of functional component and its property are introduced to make a more in-depth description of the framework. Finally, the feasibility of F-Model is established by a simple instance. View full abstract»

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  • Component Replication Based on Failover Units

    Page(s): 99 - 108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    Although component middleware is increasingly used to develop distributed, real-time and embedded (DRE) systems, it poses new fault tolerance challenges, such as the need for efficient synchronization of internal component state, failure correlation across groups of components, and configuration of fault-tolerance properties at the component granularity level. This paper makes two contributions to R&D on component-based fault-tolerance. First, we present the structure and functionality of our component replication based on failover units (CORFU) middleware, which provides fail-stop behavior and fault correlation across groups of components in DRE systems. Second, we empirically evaluate CORFU and compare/contrast it with existing object-oriented fault-tolerance methods. Our results show that component middleware (1) has acceptable fault-tolerance performance for DRE systems and (2) eases the burden of application development by providing middleware support for fault-tolerance at the component level. View full abstract»

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  • Optimal Assignment of Real-Time Systems into Multi-context Dynamically Reconfigurable Processors

    Page(s): 109 - 118
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    In this paper, we focus on the problem of implementing a periodic concurrent system with timing constraints into multi-context dynamically reconfigurable processors (DRP). A concurrent system has multiple tasks that can be executed in parallel. Moreover, some tasks in a specific set of processes might be required to synchronize each other. We propose a method for assigning tasks into a multi-context DRP such that timing constraints of the system are satisfied and the size of the program area required on each context for implementing the given system is minimized. We formulate the problem as an ILP problem and propose a heuristic algorithm for solving the ILP problem efficiently. Experimental results and a case study using ubiquitous sensor devices are given. View full abstract»

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  • Efficient Processing of Real-Time Multi-item Requests with Network Coding in On-demand Broadcast Environments

    Page(s): 119 - 128
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (510 KB) |  | HTML iconHTML  

    On-demand broadcast is an effective wireless data dissemination technique to enhance system scalability and capability to handle dynamic user access patterns. Traditional on-demand broadcast is under the assumption that only one data item can be retrieved by mobile clients in each time unit. However, the above constraint limits bandwidth utilization and throughput of broadcast systems. In this paper, we consider data broadcast with network coding in real-time on-demand broadcast environments. We analyze the coding problem in on-demand broadcast and transform it into the problem of finding the maximum clique in graph theory. Based on our analysis, a novel algorithm called ADC is proposed. ADC considers both request overlapping and request timing requirement in request scheduling and fully exploits information about clients' cached and requested data items to implement a flexible coding mechanism. The advantages of our proposed algorithm over other traditional and coding assisted broadcast algorithms are shown through simulation results. Our algorithm not only reduces deadline miss ratio of requests, but also utilizes broadcast channel bandwidth efficiently. View full abstract»

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  • Towards Model-Based Optimisations of Real-Time Systems, an Application with the AADL

    Page(s): 129 - 134
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    Model driven engineering provides facilities to tackle complexity in real-time systems, from early requirements capture to validation & verification down to code generation. We note that models are built from a system perspective, and resources are allocated to meet communication, energy or scheduling constraints. Yet, it is seldom optimal. In this paper, we explore transformations applied at model-level that preserve schedulability of the system, yet reduce the overall resource consumption. We use AADL as input formalism. By automating this process, we show how to transition from a system view to an implementation view, closer to actual hardware constraints. View full abstract»

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  • Periodic and Aperiodic Communication Techniques for Responsive Link

    Page(s): 135 - 142
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    Responsive Link, an ISO/IEC communication standard, provides many functional capabilities for distributed realtime systems. This paper is focused on periodic and aperiodic communication techniques for Responsive Link. In periodic communication, the priority is assigned to each packet so that the network utilization is improved. A schedulability test for connection establishments is also derived to ensure timing guarantees. In aperiodic communication, meanwhile, the bandwidth is reserved to improve response time as much as possible without periodic timing violations. The effectiveness of the presented techniques is demonstrated through a series of simulations. View full abstract»

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