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2009 17th IEEE Symposium on High Performance Interconnects

25-27 Aug. 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - vii
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  • Message from General Chair

    Publication Year: 2009, Page(s): viii
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  • Message from Program Co-chairs

    Publication Year: 2009, Page(s): ix
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  • Organizing Committee

    Publication Year: 2009, Page(s): x
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  • Program Committee

    Publication Year: 2009, Page(s): xi
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  • Keynote: The Other Face of On-Chip Interconnect

    Publication Year: 2009, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (51 KB)

    The multicore revolution has changed the way we think about computing. The same movement has also changed the way we look at on-chip interconnect because it is a key determinant of the performance and power efficiency of multicores. This talk will highlight some of the lesser known issues and opportunities of on-chip interconnect, such as protection, programming ease, and the impact on the basic s... View full abstract»

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  • Keynote: The Need for Speed in Trading Environments

    Publication Year: 2009, Page(s): xiii
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB)

    Time is of the essence in today's rapid business climate. The speed at which signals are transmitted and received at their destination is vital to optimizing the performance of real-time systems, both in hardware and in software. There is an industry shift taking place for mission critical low-latency systems with more functionality moving from software to hardware. In global financial trading env... View full abstract»

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  • Keynote: High-Speed Networking and the Race to Zero

    Publication Year: 2009, Page(s): xiv
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (61 KB)

    There may be no more critical an environment for interconnect and networking than the Electronic and trading floors of the NYSE Euronext markets. National economies can be impacted and personal fortunes created in the blink of an eye. At NYSE Euronext, we are leading the charge to ever faster and faster trading speeds through the adoption of leading edge technology and architectures. In this talk,... View full abstract»

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  • Tutorial: Infiniband and 10-Gigabit Ethernet for Dummies

    Publication Year: 2009, Page(s): xv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (58 KB)

    InfiniBand Architecture (IB) and 10-Gigabit Ethernet (10GE) technologies are generating significant excitement towards building next generation high-end computing (HEC) systems. This tutorial will provide an overview of these emerging technologies, their offered features, their current market standing, and their suitability for prime-time HEC. It will start with a brief overview of IB, 10 GE, and ... View full abstract»

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  • Tutorial: Designing High-End Computing Systems with Infiniband and 10-Gigabit Ethernet

    Publication Year: 2009, Page(s):xvi - xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB)

    As InfiniBand architecture (IB) and 10-Gigabit Ethernet (10GE) technologies mature in their support for next generation high-end computing (HEC) systems, more and more scientists, engineers and researchers are becoming interested in learning about the details of these technologies. Large-scale deployments of these technologies are also bringing new challenges in terms of performance, scalability, ... View full abstract»

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  • Panel: Remote Direct Memory Access over the Converged Enhanced Ethernet Fabric: Evaluating the Options

    Publication Year: 2009, Page(s): xviii
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  • Panel: Industrial Leaders Forum

    Publication Year: 2009, Page(s): xix
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  • Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects

    Publication Year: 2009, Page(s):3 - 12
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (267 KB) | HTML iconHTML

    In a power and area constrained multicore system, the on-chip communication network needs to be carefully designed to maximize the system performance and programmer productivity while minimizing energy and area. In this paper, we explore the design of energy-efficient low-diameter networks (flattened butterfly and Clos) using equalized on-chip interconnects. These low-diameter networks are attract... View full abstract»

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  • Winning with Pinning in NoC

    Publication Year: 2009, Page(s):13 - 21
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (787 KB) | HTML iconHTML

    In chip multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design. Previously proposed techniques for reducing router latency using expre... View full abstract»

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  • Simple Fairness Protocols for Daisy Chain Interconnects

    Publication Year: 2009, Page(s):22 - 30
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (349 KB) | HTML iconHTML

    In this paper, we focus on fair access to bandwidth in daisy-chained interconnects. We first analyze the original HyperTransport fairness protocol and show that it is not perfectly fair. We then propose a new, fair scheme whose complexity is similar to that of the HyperTransport protocol. View full abstract»

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  • Adaptive Routing in Data Center Bridges

    Publication Year: 2009, Page(s):33 - 41
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1806 KB) | HTML iconHTML

    In an effort to drive down the cost of ownership of interconnection networks for data centers and high-performance computing systems, technologies enabling consolidation of existing networking infrastructure, which often comprises multiple, incompatible networks operating in parallel, are feverishly being developed. Such consolidation carries the promises of lower complexity, less maintenance over... View full abstract»

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  • Fulcrum's FocalPoint FM4000: A Scalable, Low-Latency 10GigE Switch for High-Performance Data Centers

    Publication Year: 2009, Page(s):42 - 51
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (510 KB) | HTML iconHTML

    The convergence of different types of networks into a common data center infrastructure poses a superset challenge on the part of the underlying component technology. IP networks are feature-rich, storage networks are lossless with controlled topologies, and transaction networks are low-latency with low jitter, parallel multicast. A successful converged enhanced Ethernet (CEE) switch should pass t... View full abstract»

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  • Performance Measurement of an Integrated NIC Architecture with 10GbE

    Publication Year: 2009, Page(s):52 - 59
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (337 KB) | HTML iconHTML

    The deployment of 10 Gigabit Ethernet (10 GbE) connections to servers has been hampered by the "fast-network-slow-host" phenomenon. Recently, the integration of network interfaces (INICs) is proposed to tackle the performance mismatch. While significant advantages over PCI-based discrete NICs (DNICs) were shown in prior work using simulation methodologies, it is still unclear how INICs perform on ... View full abstract»

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  • MPI Collective Communications on The Blue Gene/P Supercomputer: Algorithms and Optimizations

    Publication Year: 2009, Page(s):63 - 72
    Cited by:  Papers (5)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    The IBM Blue Gene/P (BG/P) system is a massively parallel supercomputer succeeding BG/L, and it comes with many machine design enhancements and new architectural features at the hardware and software levels. This paper presents techniques leveraging such features to deliver high performance MPI collective communication primitives. In particular, we exploit BG/P rich set of network hardware in expl... View full abstract»

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  • MiAMI: Multi-core Aware Processor Affinity for TCP/IP over Multiple Network Interfaces

    Publication Year: 2009, Page(s):73 - 82
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB) | HTML iconHTML

    The multi-core processors are being widely exploited by many high-end systems and leveraging throughput and scalability. Due to the availability of boosting many concurrent processes, not only the parallel programs but also network server programs can benefit tremendously from multi-core processors. In spite of many researches, modern operating systems still have significant design and optimizatio... View full abstract»

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  • FPGA Accelerated Low-Latency Market Data Feed Processing

    Publication Year: 2009, Page(s):83 - 89
    Cited by:  Papers (14)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (217 KB) | HTML iconHTML

    Modern financial exchanges provide updates to their members on the changing status of the market place, by providing streams of messages about events, called a market data feed. Markets are growing busier, and the data-rates of these feeds are already in the gigabit range, from which customers must extract and process messages with sub-millisecond latency.This paper presents an FPGA accelerated ap... View full abstract»

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