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Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

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Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Date 19-23 Sept. 2004

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Title History

General Chair's welcome

[Copyright notice]

Table of contents

Electromagnetic field induced degradation of magnetic recording heads in a GTEM cell

Wire bonding tip study for extremely ESD sensitive devices

Soft ESD phenomena in GMR heads in the HDD manufacturing process

Nano-transient current and transient resistance on the conductive or dissipative materials for extremely sensitive devices

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions

InGaP/GaAs HBT DC-20 GHz distributed amplifier with compact ESD protection circuits

Low-voltage diode-configured sige:C HBT triggered ESD power clamps using a raised extrinsic base 200/285 GHz (fT/fMAX) SiGe:C HBT device

From the ESD robustness of products to the system ESD robustness

Evaluation of ESD hardness for fingerprint sensor LSIs

Induced ESD on metal object with a small air gap

Transmission line pulse test methods, test techniques and characterization of low capacitance voltage suppression device for system level electrostatic discharge compliance

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

Study of CDM specific effects for a smart power input protection structure

Implementation of 60V tolerant dual direction ESD protection in 5V BiCMOS process for automotive application

ESD protection design using a mixed-mode simulation for advanced devices

Gate oxide failures due to anomalous stress from HBM ESD testers

Formation and suppression of a newly discovered secondary EOS event in HBM test systems

The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps

Voltages before and after HBM stress and their effect on dynamically triggered power supply clamps

Latchup test-induced failure within ESD protection diodes in a high-voltage CMOS IC product

ESD design automation for a 90nm ASIC design system

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