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2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.

Date 6-10 Oct. 2002

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Displaying Results 1 - 25 of 70
  • [Cover]

    Publication Year: 2002 , Page(s): i
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  • General chair's welcome

    Publication Year: 2002 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2002 , Page(s): i
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  • Symposium Steering Committee

    Publication Year: 2002 , Page(s): i - iii
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  • History of the EOS/ESD Symposium

    Publication Year: 2002 , Page(s): iv
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  • Table of contents

    Publication Year: 2002 , Page(s): i - vi
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  • New considerations for MOSFET power clamps

    Publication Year: 2002 , Page(s): 1 - 5
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (282 KB) |  | HTML iconHTML  

    Two ESD clamp circuit design techniques have been developed to reduce cell size and to combat the effects of gate leakage that have become significant in recent generations of digital CMOS process technology. Such clamps have proven to be able to withstand HBM stresses of 6kV and CDM pulses of 1.2kV. View full abstract»

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  • New ESD protection circuits based on PNP triggering SCR for advanced CMOS device applications

    Publication Year: 2002 , Page(s): 6 - 9
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (238 KB) |  | HTML iconHTML  

    New silicon controlled rectifier (SCR) structures for ESD protection circuits, with low parasitic capacitance, are proposed. These new SCR structures are triggered by parasitic PNP (not NPN) transistor, with which the anode-cathode spacing (LSCR), the triggering voltage (VTRIG), the holding voltage (VHOLD), and the on-resistance (RON) were reduced successfully, and excellent ESD performance was achieved View full abstract»

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  • High Holding Current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation

    Publication Year: 2002 , Page(s): 10 - 17
    Cited by:  Papers (2)  |  Patents (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (320 KB) |  | HTML iconHTML  

    This paper presents a novel SCR for power line and local I/O ESD protection. The HHI-SCR exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current is controlled by device design. The HHI-SCR is demonstrated in 0.10um-CMOS and in a 0.4um-BiCMOS technology. The design is highly area efficient. View full abstract»

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  • A 6mW, 1.5dB NF CMOS LNA for GPS with 3kV HBM ESD-protection

    Publication Year: 2002 , Page(s): 18 - 25
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (9705 KB) |  | HTML iconHTML  

    This paper describes the design of a high performance 0.25µm CMOS Low Noise Amplifier (LNA) for the Global Positioning System (GPS) operating at 1.57GHz. The LNA features a 1.5dB noise figure. The input ESD-protection is in the order of 3kV HBM and the power consumption is only 6mW. View full abstract»

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  • Sources of impulsive EMI in large server farms

    Publication Year: 2002 , Page(s): 26 - 31
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (815 KB) |  | HTML iconHTML  

    Further research is reported on EMI in large server installations.[1] Data is presented from both staged events and server environments. The data confirms the presence of strong fields in the vicinity of servers. One unexpected source of EMI is reported. However, human activity is strongly correlated with the generation of EMI in most cases. View full abstract»

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  • Electromagnetic interference (EMI) inside a hard disk drive Due to external ESD

    Publication Year: 2002 , Page(s): 32 - 36
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (709 KB) |  | HTML iconHTML  

    GMR recording heads used in today's hard disk drives are very sensitive to damage from impulsive current transients caused by electrostatic discharge (ESD) and even the electromagnetic interference (EMI) due to a nearby ESD event.[1,2,3] In this work, we measure the EMI inside a hard disk drive due to a variety of ESD events outside the drive enclosure. View full abstract»

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  • Experimental investigation of the electrostatic discharge (ESD) characteristics for the charged human body handling circuit packs

    Publication Year: 2002 , Page(s): 37 - 46
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    An experimental study of the electrostatic discharge (ESD) characteristics for the charged human body in close approach to various sizes and orientations of electronic circuit packs near and away from a horizontal ground plane was conducted. Calculations based on measured capacitance coefficients provide a comparison of the relative probabilities and severities of the ESD event. View full abstract»

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  • A study of flip-flop IC upset exposed by ESD radiated fields

    Publication Year: 2002 , Page(s): 47 - 51
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    How ESD events cause upset to devices is discussed. A flip-flop IC (type “74xx74”) is used as a test device to observe how ESD fields are coupled into devices. EMI from the ESD event is measured as well as the di/dt characteristics of metal objects. It was determined that the IC upset can occur under low-voltage ESD (such as 600V) and normal digital circuit operating conditions. Contributing factors to IC upset problems will be given. View full abstract»

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  • Variable-trigger voltage ESD Power Clamps for mixed voltage applications using a 120 GHz/100 GHz (fT/fMAX) Silicon Germanium Heterojunction Bipolar Transistor with Carbon incorporation

    Publication Year: 2002 , Page(s): 52 - 61
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (387 KB) |  | HTML iconHTML  

    A novel ESD Power Clamps for 40 GHz applications, using a 120 GHz/100 GHz fT/fMAX Silicon Germanium Heterojunction Bipolar Transistor (HBT) with Carbon incorporation, is developed by modification of the circuit to avoid the Johnson Limit constraints for non-native voltage applications. The theory, operation, and ESD results of the ESD power clamp will be shown. View full abstract»

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  • Optimization of input protection diode for high speed applications

    Publication Year: 2002 , Page(s): 62 - 72
    Cited by:  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (14128 KB) |  | HTML iconHTML  

    Optimization of input protection diodes for high-speed applications including RF and Internet receivers is examined. The key parameters used to rate the diodes are the RC time constant and the failure point defined by HBM failure voltage per unit of capacitance. Minimizing the RC time constant for stripe diodes includes looking at tapered metal, wide ground stripes, slot contacts, background doping, and the length of the stripes. Maximizing the failure point includes looking at tapered metal, contacts, and proximity effects. View full abstract»

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  • Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies

    Publication Year: 2002 , Page(s): 73 - 82
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (413 KB) |  | HTML iconHTML  

    In an ESD analysis of the radio frequency (RF) npn transistor in three BiCMOS generations the basepushout effect is identified as a dominant factor, causing a characteristically high differential resistance at low and intermediate ESD currents and a second non-thermal snapback leading to the transistors usual low-ohmic breakdown mode. Concepts to exploit the base-pushout effect for improved RF ESD protection schemes are presented. View full abstract»

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  • A novel on-chip ESD protection circuit for GaAs HBT RF power amplifiers

    Publication Year: 2002 , Page(s): 83 - 91
    Cited by:  Papers (4)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (10372 KB) |  | HTML iconHTML  

    A low capacitance, on-chip Electrostatic Discharge (ESD) protection circuit for GaAs power amplifiers that does not degrade RF circuit performance is introduced. It's principle of operation, capacitance loading, leakage current, ESD clamping characteristics, and robustness over process variation and temperature will be presented. Finally, a case study of its application to wireless local area network 11.802A, 5.8GHz power amplifier will be discussed. View full abstract»

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  • Test methods, test techniques and failure criteria for evaluation of ESD degradation of analog and radio frequency (RF) technology

    Publication Year: 2002 , Page(s): 92 - 100
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (13064 KB) |  | HTML iconHTML  

    This publication explores new test methods, and techniques to evaluate the influence of ESD damage on analog and radio frequency (RF) technology. The methods evaluate the relationship between transistor dc degradation and RF performance fT and f{maxMAX}, a dc shift criteria vs pre- and post-RF functional product test degradation results, a Time Domain Reflection (TDR) reflection method, and a pre- and post- stress “eye test” evaluation method. View full abstract»

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  • Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway

    Publication Year: 2002 , Page(s): 101 - 110
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (13554 KB) |  | HTML iconHTML  

    A 2-D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, is presented. The method is used to provide physical evaluation of a safe operation regime for BiCMOS ESD protection structures and circuits. ESD stress induced hot spot formation using 3D simulation has been presented for the case of a simplified snapback n-MOS device. View full abstract»

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  • Modelling and extraction of RF performance parameters of CMOS Electrostatic Discharge protection devices

    Publication Year: 2002 , Page(s): 111 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    The HF parasitic behaviour of two terminal, CMOS Electrostatic Discharge (ESD) protection devices is studied. Basic small signal RC equivalent models and corresponding parameter extraction procedures, applicable for the most typical structures such as ggNMOS, diodes and SCR's are presented. A new de-embedding procedure, not requiring bulky ‘dummy’ (open, short) structures, is developed to allow easy S-parameter evaluation of the ESD devices from the most often used, two terminal ESD characterization test arrays. Finally, the impact of the ESD protection device failure on the overall RF circuit performance is discussed. View full abstract»

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  • Analysis of Barkhausen noise failure caused by ESD in a GMR head

    Publication Year: 2002 , Page(s): 119 - 122
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2896 KB) |  | HTML iconHTML  

    We used a spin-stand with a pre-amplifier with a built-in ESD simulator circuit to investigate a new magnetic failure mode caused by ESD current. This failure mode originates in Barkhausen noise from unexpected domain walls in the free layer of a giant magnetoresistive (GMR) head. According to a modified machine model (0 Ω, 50 pF), this failure occurs at around 0.5 V, i.e., a quarter of that at which a conventional pinned layer reversal failure occurs. View full abstract»

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  • Effects of ESD transients on the properties of GMR heads

    Publication Year: 2002 , Page(s): 123 - 129
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (6814 KB) |  | HTML iconHTML  

    Simulated ESD transients with pulsewidths from 0.1 nsec to 10 nsec were applied to GMR heads. From 1 to 10 nsec essentially no changes in failure voltages are observed, but below approximately 1 nsec, failure voltages increase. The time marking a transition between the two regimes, ∼1 nsec, and the dependence of failure voltage on either side are qualitatively consistent with the expected transition from adiabatic failure for short pulses to a more steady-state thermal failure for longer pulses, but true adiabatic behavior is not clear for short pulses. The ratio in voltages inducing resistance versus amplitude failure remains constant over all pulsewidths and for both voltage polarities, suggesting thermal degradation is dominant. Although magnetic failures occur at lower voltages than resistive, no observations here suggest that either the magnitude or direction of the pulse-induced magnetic field is a critical parameter in head failure. View full abstract»

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  • High frequency instabilities in GMR heads due to metal-to-metal contact ESD transients

    Publication Year: 2002 , Page(s): 130 - 137
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    Utilizing a D-CDM (Direct Charged Device Model) ESD tester this study evaluates the failure rates of GMR heads by measuring high frequency instability noise events as the discrimination factor vs. ESD voltage. The D-CDM tester replicates the sub-1ns ESD event produced by metal-to-metal contact discharge that occurs as a charged component, in this case the GMR head, discharges to another object at a different electrostatic potential. By generating this ESD event at increasing charge voltages in an in-situ environment with a QuasiStatic (QST) tester, head failure effects were recorded. In addition to the standard parametrics of amplitude and resistance, advanced noise instability measurements were also performed. As is commonly understood with GMR heads amplitude may begin to fail unpredictably prior to detectable resistance failures, but this study analyzes the voltage levels where GMR heads become unstable, and their instability characteristics. View full abstract»

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  • A study of electrostatic discharge on MR heads in digital tape systems

    Publication Year: 2002 , Page(s): 138 - 141
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    In helical-scan digital tape systems, the MR head is brought into contact with the tape surface without a protective coating. In this paper, we study electrostatic discharge when the MR heads make contact with the charged tapes in terms of tape surface resitance and the electrostatic charge on the tape. View full abstract»

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