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Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.

Date 11-13 Sept. 2001

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Displaying Results 1 - 25 of 65
  • [Cover]

    Publication Year: 2001 , Page(s): c1
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    Freely Available from IEEE
  • [Title page]

    Publication Year: 2001 , Page(s): i
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  • [Copyright notice]

    Publication Year: 2001 , Page(s): ii
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  • Table of contents

    Publication Year: 2001 , Page(s): iii - viii
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    Freely Available from IEEE
  • Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling

    Publication Year: 2001 , Page(s): 1 - 11
    Cited by:  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (13340 KB) |  | HTML iconHTML  

    A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs. View full abstract»

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  • 5-V tolerant fail-safe ESD solutions for 0.18µm logic CMOS process

    Publication Year: 2001 , Page(s): 12 - 21
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2062 KB) |  | HTML iconHTML  

    Failsafe, high voltage tolerant, low capacitive ESD solutions are implemented in a 0.18 mum dual- gate advanced CMOS technology. This technology features a drain-extended transistor with BVdss of 13 V. Protection of drain extended transistors that allow up to 7V drain operating voltage using 70Aringring oxide is investigated with the integration of a special ldquoself-alignedrdquo STI-blocked SCR structure. Excellent HBM and CDM performance for the I/O applications with this approach are demonstrated. View full abstract»

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  • GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes

    Publication Year: 2001 , Page(s): 22 - 31
    Cited by:  Papers (1)  |  Patents (8)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (810 KB) |  | HTML iconHTML  

    In this paper, design aspects, operation, protection capability and applications of SCRs in deep sub-micron CMOS are addressed. A novel Grounded-Gate NMOS Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR. Experimental verification, including endurance testing, demonstrates that GGSCRs can fulfill all ESD protection requirements for todays IC applications in different 0.25 um, 0.18 um and 0.13 um CMOS processes. View full abstract»

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  • ESD protection design for mixed-voltage I/O buffer by using stacked-NMOS triggered SCR device

    Publication Year: 2001 , Page(s): 32 - 43
    Cited by:  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB) |  | HTML iconHTML  

    A new ESD protection circuit, by using the stacked-NMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS IC's. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original ~2 kV to become > 8 kV by using this new proposed ESD protection circuit. View full abstract»

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  • An analysis of ESD packaging systems through thermoforming

    Publication Year: 2001 , Page(s): 44 - 49
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (233 KB) |  | HTML iconHTML  

    In the packaging industry, from folding cartons to bags and clamshells, various packaging configurations are available to the end-user. This paper explores the factors involved in producing the electrostatic dissipative (ESD) effect and its benefit in the clamshell blister segment by equating differences before and after thermoforming of the ESD article. View full abstract»

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  • Performance of fiber based ESD protective packaging

    Publication Year: 2001 , Page(s): 50 - 54
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    We have studied the performance (surface resistance, charge decay and electrostatic discharge shielding properties) of 100 % recyclable, biodegradable, fiber based ESD protective packages and packaging materials. The measurements have been done in the humidity range of 5 - 95 % RH, representing extreme environmental conditions experienced by electronic products during global transportation and storage. The tested fiber based materials seem very promising for the new generation of ESD protective packaging. They can shield ESD sensitive electronics from external ESD contact discharges of several kV magnitude and effectively dissipate or migrate electric charge. View full abstract»

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  • New ESD control material based on special carbon

    Publication Year: 2001 , Page(s): 55 - 60
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2293 KB) |  | HTML iconHTML  

    New ESD control materials, based on combining special carbon material with moderately conductive surface resistivity with polycarbonate (PC) and polyetheretherketone (PEEK), have been developed and assessed. The surface resistivity of special carbon with resistivity of 107 ohms/sq., filled with PC and PEEK, remained in the range of 109 to 108 ohms/square regardless of the carbon content beyond each critical. The surface resistivity was easily controlled at the specific levels required for ESD control materials by using the special carbon. The surface resistivity fluctuation on the injection-molded plate was very small and the surface resistivity change against applied voltage was small. View full abstract»

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  • Analysis and improved compact modeling of the breakdown behavior of sub-0.25 micron ESD protection ggNMOS devices

    Publication Year: 2001 , Page(s): 61 - 69
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (429 KB) |  | HTML iconHTML  

    The work focuses on a better understanding of the sub-quater micron ggNMOS device breakdown, compact modeling of the band-to-band tunneling enhanced substrate current and the observed gate hot hole injection current. Simple implications of the improved subbreakdown current model on the ggnNMOS model behaviour are shown. Finally, the observed TLP failure mode of the investigated devices is discussed. View full abstract»

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  • Modeling substrate diodes under ultra high ESD injection conditions

    Publication Year: 2001 , Page(s): 70 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    In this paper the behavior of P+-N--N+ substrate diodes under ultra high injection conditions will be analyzed both numerically and experimentally. The J(V) characteristic in this regime will be analytically obtained, modeled and verified both on numerical simulations and on measured devices. For modeling purposes, an analytical fitting law matching the J(V) characteristic over a broad range of injection levels will be proposed. Self-heating effects and process/layout variations will be analyzed too. View full abstract»

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  • Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies

    Publication Year: 2001 , Page(s): 81 - 94
    Cited by:  Papers (2)  |  Patents (11)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (404 KB) |  | HTML iconHTML  

    This paper introduces a new distributed active MOSFET rail clamp network that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity and ease of reuse. SPICE simulation results using an extended vertical PNP bipolar transistor compact model and a new method for optimizing distributed rail clamp networks are presented along with chip-level test results. View full abstract»

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  • Automatic layout based verification of electrostatic discharge paths

    Publication Year: 2001 , Page(s): 95 - 100
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2246 KB) |  | HTML iconHTML  

    This work describes an ESD path verification methodology based on layout parasitic extraction. This approach was implemented in Cadence DFII. It provides information about the preferred ESD path between two pads and estimates the peak pad to pad voltage. The path can also be overlaid on the layout view. The methodology was applied to a 0.5 um BiCMOS design to improve its ESD robustness. In that case, weak ESD paths overlooked during conventional design reviews were identified and corrected. The ESD robustness improved from 1.0 kV to 2.5 kV and 100 V to 250 V for HBM and MM respectively. View full abstract»

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  • Experimental analysis and electro-thermal simulation of low- and high-voltage ESD protection bipolar devices in a Silicon-On-Insulator Bipolar-CMOS-DMOS technology

    Publication Year: 2001 , Page(s): 101 - 108
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (613 KB) |  | HTML iconHTML  

    We present the results of extensive characterization of fully isolated SOI NPN bipolar protection devices by means of both 2D simulations, DC and TLP measurements, and HBM/TLP ESD stress tests. Excellent agreement between measured and simulated quasistatic and pulsed I-V characteristics of the protection structures has been obtained. We also confirm the usefulness of 2D/3D device simulations for ESD optimization. View full abstract»

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  • Human Body Model test of a Low Voltage Threshold SCR device: Simulation and comparison with the Transmission Line Pulse test

    Publication Year: 2001 , Page(s): 109 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    A methodology for the application of two-dimensional (2-D) device simulation to HBM events is presented, validated on linear components and applied on the particular case of an ESD protection structure (a 1.2 mum Low Voltage Threshold Silicon Controlled Rectifier LVTSCR). Then we compare HBM and TLP tests. For this example, no correlation between the HBM breakdown level and the second breakdown current density Jt2 has been found. Nevertheless, we demonstrate some common mechanisms between the two types of tests. View full abstract»

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  • Controlling ESD damage of ICs at various steps of back-end process

    Publication Year: 2001 , Page(s): 119 - 123
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    In this work we study the methodology of ESD Event identification and their correlation with operation of equipment at various stages of the back end IC manufacturing. Survey of ESD environment in terms of exposure of ICs to known strength of ESD Events is described. Such correlation is instrumental in identification of sources of ESD damage and in setting up and maintaining ESD-safe environment. View full abstract»

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  • An effective ESD protection system in the Back end (BE) semiconductor manufacturing facility

    Publication Year: 2001 , Page(s): 124 - 131
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    ESD protection measures in the Back-end (BE) semiconductor manufacturing environment have become more and more critical. This is due to the increased sensitivity to ESD damage of microchips from the decreasing structural geometries and increased integration density. However, the requirements for BE ESD protection have not been well understood in the semiconductor industry. Some of the commonly observed evidence of this are overkill ESD protection measures with ineffective end results. This paper provides an overview on an effective ESD protection system implementation in a BE semiconductor manufacturing facility. View full abstract»

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  • Preparing a microelectronics assembly and test area for more sensitive product

    Publication Year: 2001 , Page(s): 132 - 139
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    In anticipation of bringing a more sensitive product (< 50 V MM and HBM damage threshold) into a microelectronics area, audits were performed on the equipment, materials and processes in the area. First, the ESD sensitivity of the product was determined. Then, using an electrometer, static event detectors and test articles, tests were performed to identify high-risk materials and processes. These included ball bonding, laser welding and bench-to-oven transport. Several modifications to equipment and materials were necessary to reduce the risk for ESD damage to the product. This paper summarizes the test methods, findings, and recommendations for improvement. View full abstract»

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  • Anodized Aluminum alloys, insulator or not?

    Publication Year: 2001 , Page(s): 140 - 147
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (371 KB) |  | HTML iconHTML  

    The automated handling equipment (AHE) industry presently uses expensive, exotic and environmental unfriendly conductive or dissipative finishes such as silver impregnated anodize, black electroless nickel, black chrome, and black copper to control ESD. The purpose of this study was to determine if anodized aluminum would provide a sufficient range of dissipation. This paper describes the result of controlled experiments of several plating suppliers and types of plating. When implemented, dissipative anodized aluminum will provide a conservative annual savings of at least $1,000,000 to Universal Instruments Corporation. View full abstract»

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  • DC Transient Monitoring and analysis to prevent EOS in burn-in systems

    Publication Year: 2001 , Page(s): 148 - 151
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    This paper describes a Direct Current (DC) Transient Monitoring system integrated in burn-in test systems, to detect exceed voltages and occurrences per period limits, and record readings into a database for analysis of noise (physical and behavior). The system has features to automatically shut down a burn-in system to prevent damage to devices under test from electrical overstress (EOS) events. View full abstract»

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  • Measurement of electrostatic generation in semiconductor processing fluids as a result of pumping through insulative pumps and tubing

    Publication Year: 2001 , Page(s): 152 - 158
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    The voltage generation in six different semiconductor processing fluids; air, deionized water, methanol, isopropanol, Aleg-310reg and REZI-28reg, was evaluated as they were pumped through a PTFE pump and tubing. It was found that more voltage was generated in the ungrounded fluids during operator contact with the pump and tubing than was generated during the pumping operation. View full abstract»

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  • Field-induced charging and FIM ESD tests on GMR heads in Hard Disk Assembly

    Publication Year: 2001 , Page(s): 159 - 165
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    Both field-induced charging and ESD tests on non-input/output locations on uncovered HDA were studied. The lowest failure thresholds for GMR sensors due to fast charging transients and hard discharge were about 1000 V and 150 V respectively. Such threshold for a slow field-induced charging within a fraction of second was about 1500 V. A direct HBM ESD in the absence of field induction on the HDA would have 1300 V threshold. All these results show that protection focused at input/output and at HDA baseplate ground may not be sufficient. This study confirms that for HDA, FIM events are by far the most severe form of ESD. View full abstract»

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  • A study of shunt ESD protection for GMR recording heads

    Publication Year: 2001 , Page(s): 166 - 170
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    The electrostatic discharge (ESD) behavior of shunted GMR heads on a head gimbal assembly (HGA) design is reported. It was found that the shunt offers ESD protection only when the charge from the ESD event is applied very close to the shunt. An explanation is given in terms of the impedance of the wires between the GMR head and shunt at the high frequencies associated with metal contact ESD. View full abstract»

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