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Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Date 2-5 Aug. 2009

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Displaying Results 1 - 25 of 290
  • A pseudo rail-to-rail chopper-stabilized instrumentation amplifier in 0.13 µm CMOS

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB) |  | HTML iconHTML  

    This paper presents a CMOS chopper-stabilized instrumentation amplifier based on a compact differential difference amplifier (DDA). The DDA itself is based on a high gain and robust two-stage class-AB amplifier. Simulation results show that with chopping frequency at 250 KHz, both the noise density and offset can be reduced by a factor of 10. Detailed practical application considerations of the proposed In-Amp as a current-sensing amplifier in a power management chip are presented. View full abstract»

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  • Design of high-side current sense amplifier with ultra-wide ICMR

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (733 KB) |  | HTML iconHTML  

    A high-side current sense amplifier with wide input common mode range (ICMR) is proposed. To improve the accuracy of signal transfer, a common base structure is introduced to realize the control to bias currents. And a high accurate current mirror is used to enhance the gain precision. In addition, a common emitter and common source class AB amplifier topology is proposed to provide a rail-to-rail output and high driven capability. As results, the amplifier keeps the constant closed-loop voltage gain of 50 V/V, and an ICMR of 0 V-28 V is achieved, which is independent of the supply voltage. It can work at low supply voltage down to 1.5 V. And the minimum supply current is 38 muA. The chip was designed and fabricated in 1.5 mum BCD technology. The experimental results showed that the chip works normally and all expected specifications are achieved. View full abstract»

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  • Indirect compensation techniques for three-stage CMOS op-amps

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (742 KB) |  | HTML iconHTML  

    As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the transistor threshold voltages are remaining relatively constant. Making matters worse, the inherent gain available from the nano-CMOS transistors is dropping. Traditional techniques for achieving high-gain by vertically stacking (i.e. cascoding) transistors becomes less useful in nano-scale CMOS processes. Horizontal cascading (multi-stage) must be used in order to realize high-gain op-amps in low supply voltage processes. This paper discusses new design techniques for the realization of three-stage op-amps. The proposed and experimentally verified op-amps, fabricated in 500 nm CMOS, typically exhibit 30 MHz unity-gain frequency, near 100 ns transient settling and 72deg phase-margin for 500 pF load. This results in significantly higher op-amp performance metrics over the traditional op-amp designs while at the same time having smaller layout area. View full abstract»

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  • Design procedure and performance potential for operational amplifier using indirect compensation

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB) |  | HTML iconHTML  

    A design procedure for an operational amplifier using indirect compensation is presented in this paper. Indirect compensation has inherent benefits in regards with power to speed trade-off. The technique has been seldom used in the past because a clear methodology for designing such an amplifier has not been provided. This paper develops the mathematical and analytical insight for designing an operational amplifier with this technique. The paper also provides a design strategy and an example to illustrate the use of the proposed design procedure. View full abstract»

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  • Low-voltage CMOS cross-quad implementation based on dynamic positive feedback

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (574 KB) |  | HTML iconHTML  

    This paper presents the implementation of a cross-quad circuit suitable for low-voltage operation. The proposed cell exploits a dynamic positive feedback gm boosting technique to achieve linear voltage-to-current conversion, while it manages to work with low-voltage with no extra bias current and minimal additional hardware. Results for a 0.5 mum CMOS implementation supplied at 3 V show a 0.972% voltage-to-current accuracy, improving the 0.867% accuracy of a previously reported cross-quad topology also suitable for low-voltage operation which is based on folded transistors. View full abstract»

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  • A precision architecture for high-speed amplifier applications

    Page(s): 21 - 23
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    A circuit configuration is suggested for the design of fixed-gain amplifiers that are intended for integrated circuit fabrication and that require both accuracy and high-speed. The approach, which does not employ negative feedback, is demonstrated in both BJT and HBT processes. Fixed-gain amplifiers are designed and tested to a specification of 0.1% gain accuracy and bandwidths in excess of 2 GHz. View full abstract»

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  • Oscillation controlled electronic systems design using Posicast-based pulse pre-shaping

    Page(s): 24 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (641 KB) |  | HTML iconHTML  

    In this paper, a novel method is proposed to make electronic systems instability safe using pulse pre-shaping techniques. The under test target systems in this work are the electronic systems that experience pulse like inputs. This method reduces the overshoot of the system's response and improves the settling time significantly using Posicast-based input command shaping. The method is applied on three types of systems which have oscillation and overshoot in their step response. Simulation results are shown to verify the effectiveness of the proposed method on oscillation and overshoot canceling. Experimental results of HSPICE simulations show that the overshoot of discussed systems is decreased more than 95% and in some cases is canceled completely that leads to increase of phase margin and complete stability of system. Also, the settling time is improved more than 78% for each three systems. Besides, the effects of pre-shaped Posicast pulse non-idealities like variations and jitters on systems response are completely simulated. The effective non-ideal factors on Posicast response are: variation in time of applying Posicast command (jitter noise) and voltage level of Posicast command. View full abstract»

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  • A CMOS voltage reference using compensation of mobility and threshold voltage temperature effects

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    A CMOS voltage reference using compensation of mobility and threshold voltage temperature effects is proposed. In this reference, the nested connection of two NMOS transistors supplies a voltage with positive temperature coefficient, and the diode-connected NMOS transistor supplies a voltage with negative temperature coefficient. These two circuits are connected in series via an operational amplifier, and the resulting voltage that appears in the output stage of this amplifier has low temperature coefficient. The calculations are verified by simulations of the reference designed in 0.13 mum CMOS technology. The simulated reference provides a voltage of about 490 mV with the variation of 1 mV in the temperature range 20 to 120degC. The reference is able to operate with sub-1V power supplies. View full abstract»

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  • A 12nV/√Hz noise-shaped channel select filter for DVB-H mobile-TV tuners

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (606 KB) |  | HTML iconHTML  

    In this paper, a new technique for realizing area efficient, low noise filters is introduced. The proposed filter topologies utilize noise shaping techniques to shift the noise of the passive and active filter components out of the pass band of the filter. This is illustrated by implementing a 5th-order noise-shaped post mixer gain-filtering circuit in a 65-nm CMOS process. The proposed circuits consume 4.8 mA from a 1.2-V supply with an in-band noise density of 12 nV/sqrt(Hz) and an IIP3 of 25.5 dBm. The design provides 50 dB filtering for the adjacent blockers of the target digital video broadcast-handheld (DVB-H) receiver. The gain of the stage is programmable in 6-dB steps without altering the filter response. View full abstract»

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  • Modeling of CFOA based non-inverting amplifier using standard hardware description language

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1141 KB) |  | HTML iconHTML  

    This paper presents a model of current feedback operational amplifier (CFOA) based non-inverting amplifier using standard hardware description language (VHDL). Research work explains how to model analog building blocks based on a language used for describing digital hardware. The advantage of modeling using VHDL is investigated. Simulation results using VHDL is given. PSPICE simulation results confirm the VHDL simulation results are also given. View full abstract»

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  • Balanced transconductor-C ladder filters with improved linearity

    Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (474 KB) |  | HTML iconHTML  

    Balanced transconductor-C filters simulating passive LC ladder structures can be built with different arrangements of the balanced transconductors, what reduces the input voltages over the transconductor inputs, reducing the nonlinearity of the filter. The need of common-mode feedback circuits can also be eliminated by structural changes in the transconductors. The paper investigates the synthesis procedure and the stability properties of these modified filters. View full abstract»

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  • Fully Balanced Voltage Differencing Buffered Amplifier and its applications

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    An active circuit element, namely fully balanced voltage differencing buffered amplifier (FB-VDBA), is introduced. Its input stage is composed of a fully-differential operational transconductance amplifier (OTA). Voltage buffer is connected to each OTA output. Several applications are proposed which demonstrate the element's versatility. The results of SPICE simulation and measurements on experimental specimen are included. View full abstract»

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  • Comparative study on the effects of PVT variations between a novel all-MOS current reference and alternative CMOS solutions

    Page(s): 49 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (587 KB) |  | HTML iconHTML  

    Sensitivity to supply voltage, temperature and process variations of a number of current reference topologies and a novel circuit is compared in ON Semi I3T80 technology. The novel current reference shows the lowest process dependency, while supply and temperature dependency remain acceptably low. View full abstract»

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  • A flexible hardware encoder for systematic low-density parity-check codes

    Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    This paper proposes a flexible low density parity check encoder. This encoder simplifies the calculations found in other flexible encoders by increasing memory usage, allowing for parallelization and faster encoding. The flexibility of this encoder allows it to be used in emerging multi code applications and standards. To evaluate the encoder, a Verilog description was developed and synthesized on an Altera Stratix platform for the IEEE 802.16e WiMAX standard. The implementation used 11,430 logic elements and operated at a maximum clock frequency of 60 MHz. The throughput ranged from 119 Mbps for rate-1/2 codes to 357 Mbps for rate -5/6 codes. A speedup of 2.5-6 times is demonstrated compared to the prior art. View full abstract»

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  • A type III fast locking time PLL with transconductor-C structure

    Page(s): 58 - 61
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (546 KB) |  | HTML iconHTML  

    This paper is presented a type III third-order charge pump PLL with transconductor-C (Gm-C) structure to achieve a PLL with fast locking time. To reach this goal, we have used Gm-C structure in the PLL loop. The advantage of this architecture is great loop gain while increases with the ratio Gm/C. As a result, the small signal settling time decreases and then, the locking time is reduced, significantly while the loop stability increases, as well. The performance of this architecture has been verified in an example. The simulation results show that there is almost 70% reduction in the settling time in comparison with the conventional second-order PLLs. View full abstract»

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  • A nanowatt cascadable delay element for compact power-on-reset (POR) circuits

    Page(s): 62 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1184 KB) |  | HTML iconHTML  

    A cascadable power-on-reset (POR) delay element consuming nanowatt of peak power was developed to be used in very compact power-on-reset pulse generator (POR-PG) circuits. Operation principles and features of the POR delay element were presented in this paper. The delay element was designed, and fabricated in a 0.5 mum 2P3M CMOS process. It was determined from simulation as well as measurement results that the delay element works wide supply voltage ranges between 1.8 volt and 5 volt and supply voltage rise times between 100 nsec and 1 msec allowing wide dynamic range POR-PG circuits. It also has very small silicon footprint. Layout size of a single POR delay element was 35 mum x 55 mum in 0.5 mum CMOS process. View full abstract»

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  • A Spice model for magneto-impedance sensors

    Page(s): 66 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB) |  | HTML iconHTML  

    In this paper a Spice model of magneto-impedance sensors is proposed. The model is based on the equivalent circuits of a Padeacute's approximation derived from the impedance relied on Bessel functions. The resulting model is fast and acceptably accurate since only lumped electrical passive elements are required. Besides, it can predict the nonlinear frequency response from DC to several megahertz taking into account the transverse permeability changes due to an external magnetic field. The model is verified using Spice simulations together with measurements results from a discrete prototype for generating the pulse voltage source and a simple modulation type configuration. View full abstract»

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  • A CMOS low complexity Gaussian pulse generator for ultra wideband communications

    Page(s): 70 - 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (581 KB) |  | HTML iconHTML  

    A Gaussian pulse generator is proposed for UWB impulse radio systems. The generator is probed in two modulation schemes (PP and BPSK) transmitting at 400 Mbps. The proposed modulators are coupled to a 50 ohms load. The Gaussian pulse generator has been designed and simulated in Mentor Graphics for a TSMC 0.18 um MMRF CMOS process with a power supply of +/-0.9 v. View full abstract»

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  • High-speed transmitter for fully differential current-mode polyquaternary signaling scheme

    Page(s): 74 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB) |  | HTML iconHTML  

    In this work we propose fully differential current-mode polyquaternary signaling transmitter for high-speed data transmission over chip-to-chip interconnect. Polyquaternary signaling is a bandwidth efficient signaling scheme suitable for bandwidth constrained and crosstalk prone chip-to-chip interconnect. Basic polyquaternary precoding scheme is adopted for symbol-by-symbol transmission which requires simple detection logic without increasing the precoding complexity. To achieve high-speed operation pipelining and parallel processing are incorporated in to the system building blocks without much increase of power. Polyquaternary filter is integrated within the current-mode driver to reduce power and area. All building blocks are realized in current-mode logic(CML). The circuits are implemented in 1.8-V, 0.18-mum digital CMOS process technology. The power consumed in the transmitter is 53.32-mW at the data transmission rate of 10-Gb/s over 20-cm FR4 PCB trace for the targeted bit error rate(BER) of 10-12. View full abstract»

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  • The design of sub-threshold reference circuit using resistor temperature compensation

    Page(s): 78 - 81
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    A reference circuit employing sub-threshold current is presented, which uses two CTAT currents and resistor temperature compensation to generate a reference voltage of 150 mV. Since most of MOSFETs are working at sub-threshold region, the circuit only consumes 976 nW at supply voltage of 1 V with PSRR of -51.68 dB at room temperature using TSMC 0.18 mum technology. The reference voltage's average temperature coefficient is 26.67ppm/degC in the range [-25, +125]degC and its variation is 3.6 mV/V for supply voltage from 0.8 to 2.5 V. View full abstract»

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  • Design tradeoffs in a triode transconductor for low voltage zero-IF channel select filters

    Page(s): 82 - 85
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (828 KB) |  | HTML iconHTML  

    In this paper, we study the tradeoffs in operating the low voltage triode gm cell proposed by Enz at higher operating frequencies as a candidate for use in a zero-IF channel select filter. The tradeoffs in transconductor parameters are presented by introducing a current split factor design approach. It is determined that increasing the bias current in the feedback path increases the bandwidth of the gm cell at the expense of decreased tuning range and linear range. Results presented are simulated using a 0.35 mum digital CMOS process for a VDD of 1.8 V. These are useful in the preliminary design of reconfigurable filters for multi-standard receivers. View full abstract»

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  • A modified charging algorithm for comparator-based switched-capacitor circuits

    Page(s): 86 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (721 KB) |  | HTML iconHTML  

    This paper presents a modified charging algorithm for fully-differential comparator-based switched-capacitor (CBSC) circuits by utilizing an additional comparator to compare a variable differential threshold rather than detecting the zero crossing during coarse (E1) transfer phase. The large overshoot in the coarse phase can be eliminated such that it relaxes the stringent trade-off between speed and accuracy, which exists in the conventional CBSC circuits. A 1.2-V Sample-and-Hold circuit implemented in 90 nm CMOS process is used to demonstrate the effectiveness of this concept. View full abstract»

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  • A 3 mW/GHz near 1-V VCO with low supply sensitivity in 0.18-µm CMOS for SoC applications

    Page(s): 90 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    A novel pseudo-differential ring Voltage Controlled Oscillator (VCO) with near 1-V supply is realized in standard 0.18-mum CMOS with no low Vt options. The VCO core structure improves the supply noise rejection by 20 dB. The pseudo-differential structure provides rail-to-rail swing, which improves phase noise and eliminates the level shifter needed in fully differential designs. Several new topologies, suitable for near 1-V supply, are proposed for the V-to-I converter and the additional shunt supply regulator that provides additional supply noise isolation. With a 1 V supply, the whole VCO consumes less than 3 mW for 1 GHz operation and provides eight clock phases. The compatibility with digital supply and low supply sensitivity enables it to be an ideal candidate for large System-on-Chip (SoC) integrations. View full abstract»

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  • Application of active current mirrors to improve the speed of analog decoder circuits

    Page(s): 94 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (581 KB) |  | HTML iconHTML  

    Current-mirrors are widely used in the blocks of analog decoder circuits based on the sum-product algorithm. The simple current mirrors, using diode-connected input devices that traditionally have been used are limited in speed when their inputs are loaded with long wires. We present a block diagram for a large (6, 3) LDPC code and an estimation for the largest possible wiring capacitance in this decoder. We show that when active current mirrors are used on the inputs of the equality nodes, their speed is enhanced. The power and speed for a seven-input equality node are simulated with the basic mirrors and with the modified current-mirror circuits. We show through simulations in STMicroelectronics CMOS 90 nm technology and with a supply voltage of 0.4 V that the power/speed ratio for a 7-input equality node can be improved by approximately 50% with the enhanced topology. View full abstract»

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  • Limitations of the Phase-to-Frequency-Detector in Fractional Frequency Synthesizers

    Page(s): 98 - 101
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB) |  | HTML iconHTML  

    In this paper a closed form expression for the phase-to-frequency-detector (PFD) output error, in Fractional Frequency Synthesizers, is obtained. It is demonstrated that the limit frequency of operation for the PFD not only depends on the reset delay signal but also in the setup time of the PFD. With this equations a suitable delay in the reset signal can be selected. View full abstract»

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