2009 19th IEEE Symposium on Computer Arithmetic

8-10 June 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - vii
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  • Foreword

    Publication Year: 2009, Page(s): viii
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  • Program Committee

    Publication Year: 2009, Page(s): ix
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  • Steering and Symposium Committees

    Publication Year: 2009, Page(s): x
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  • Additional reviewers

    Publication Year: 2009, Page(s): xi
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  • Anton: A Specialized Machine for Millisecond-Scale Molecular Dynamics Simulations of Proteins

    Publication Year: 2009, Page(s): 3
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (143 KB) | HTML iconHTML

    The ability to perform long, accurate molecular dynamics (MD) simulations involving proteins and other biological macromolecules could in principle lead to important scientific advances and provide a powerful new tool for drug discovery. A wide range of biologically important processes, however, occur over time scales on the order of a millisecond ~ several orders of magnitude beyond the duration ... View full abstract»

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  • Efficient Data Structure and Algorithms for Sparse Integers, Sets and Predicates

    Publication Year: 2009, Page(s):7 - 14
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (314 KB) | HTML iconHTML

    We construct a natural number n > 1 by trichotomy n = g + xpd; xp = 22p, 0 les g < xp, 0 < d < xp, applied recursively, and by systematically sharing nodes with equal integer value. The resulting integer decision diagram IDD is a directed acyclic graph DAG which represents n by s(n) nodes in computer memory. IDDs compete with bit a... View full abstract»

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  • A Dual-Purpose Real/Complex Logarithmic Number System ALU

    Publication Year: 2009, Page(s):15 - 24
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (486 KB) | HTML iconHTML

    The real Logarithmic Number System (LNS) allows fast and inexpensive multiplication and division but more expensive addition and subtraction as precision increases. Recent advances in higher-order and multipartite table methods, together with cotransformation, allow real LNS ALUs to be implemented effectively on FPGAs for a wide variety of medium-precision special-purpose applications. The Complex... View full abstract»

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  • Selected RNS Bases for Modular Multiplication

    Publication Year: 2009, Page(s):25 - 32
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (453 KB) | HTML iconHTML

    The selection of the elements of the bases in an RNS modular multiplication method is crucial and has a great impact in the overall performance.This work proposes specific sets of optimal RNS moduli with elements of Hamming weight three whose inverses used in the MRS reconstruction have very small Hamming weight. This property is exploited in RNS bases conversions, to completely remove and replace... View full abstract»

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  • A Historical Perspective on Computer Arithmetic

    Publication Year: 2009, Page(s): 35
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (128 KB)

    My first experiences with decimal computer arithmetic in college (1963) influenced my subsequent career decisions and projects as described herein. Many popular early computers focused on commercial applications for which decimal arithmetic was appropriate. These digit-serial implementations did not minimize hardware cost, but provided the precision needed by the application. Decimal arithmetic as... View full abstract»

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  • Higher Radix Squaring Operations Employing Left-to-Right Dual Recoding

    Publication Year: 2009, Page(s):39 - 47
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (523 KB) | HTML iconHTML

    We introduce a novel left-to-right leading digit first dual recoding of an operand for the purpose of designing the squaring operation on that operand. Our dual recoding yields an array of non-negative partial squares of size essentially one half that of a comparable multiplier partial product array for both radix-4 and radix-8 designs. For radix-8 design the 128-bit square of a 64-bit operand can... View full abstract»

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  • Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

    Publication Year: 2009, Page(s):48 - 56
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (200 KB) | HTML iconHTML

    The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power consumption. Depending on the instruc... View full abstract»

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  • Unified Approach to the Design of Modulo-(2^n +/- 1) Adders Based on Signed-LSB Representation of Residues

    Publication Year: 2009, Page(s):57 - 64
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (494 KB) | HTML iconHTML

    Moduli of the form 2n plusmn 1, which greatly simplify certain arithmetic operations in residue number systems (RNS), have been of longstanding interest. A steady stream of designs for modulo (2n plusmn 1) adders has rendered the latency of such adders quite competitive with ordinary adders. The next logical step is to approach the problem in a unified and systematic manner t... View full abstract»

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  • Subquadratic Space Complexity Multiplier for a Class of Binary Fields Using Toeplitz Matrix Approach

    Publication Year: 2009, Page(s):67 - 75
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (337 KB) | HTML iconHTML

    In the recent past, subquadratic space complexity multipliers have been proposed for binary fields defined by irreducible trinomials and some specific pentanomials. For such multipliers, alternative irreducible polynomials can also be used, in particular, nearly all one polynomials (NAOPs) seem to be better than pentanomials (see [7]). For improved efficiency, multiplication modulo an NAOP is perf... View full abstract»

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  • Hybrid Binary-Ternary Joint Form and Its Application in Elliptic Curve Cryptography

    Publication Year: 2009, Page(s):76 - 83
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (263 KB) | HTML iconHTML

    Multi-exponentiation is a common and time consuming operation in public-key cryptography. Its elliptic curve counterpart, called multi-scalar multiplication is extensively used for digital signature verification. Several algorithms have been proposed to speed-up those critical computations. They are based on simultaneously recoding a set of integers in order to minimize the number of general multi... View full abstract»

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  • Polynomial Multiplication over Finite Fields Using Field Extensions and Interpolation

    Publication Year: 2009, Page(s):84 - 91
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (433 KB) | HTML iconHTML

    A method for polynomial multiplication over finite fields using field extensions and polynomial interpolation is introduced. The proposed method uses polynomial interpolation as Toom-Cook method together with field extensions. Furthermore, the proposed method can be used when Toom-Cook method cannot be applied directly. Explicit formulae improving the previous results in many cases are obtained. View full abstract»

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  • A New Binary Floating-Point Division Algorithm and Its Software Implementation on the ST231 Processor

    Publication Year: 2009, Page(s):95 - 103
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (345 KB) | HTML iconHTML

    This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targets a VLIW integer processor of the ST200 family, and is based on fast and accurate programs for evaluating some particular bivariate polynomials. We start by giving approximation and evaluation error conditions that are s... View full abstract»

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  • Fast and Accurate Bessel Function Computation

    Publication Year: 2009, Page(s):104 - 113
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (295 KB) | HTML iconHTML

    The Bessel functions are considered relatively difficult to compute. Although they have a simple power series expansion that is everywhere convergent, they exhibit approximately periodic behavior which makes the direct use of the power series impractically slow and numerically unstable. We describe an alternative method based on systematic expansion around the zeros, refining existing techniques b... View full abstract»

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  • Implementation Specific Verification of Divide and Square Root Instructions

    Publication Year: 2009, Page(s):114 - 121
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB) | HTML iconHTML

    Floating point operations such as divide and square root are typically implemented in microcode rather than dedicated logic. Bugs in these operations missed by generic black-box verification tools, were analyzed. This led to the conclusion that the corner cases, in addition to being implementation dependent, could not be characterized in terms of special input or output values in a straightforward... View full abstract»

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  • A Decimal Floating-Point Adder with Decoded Operands and a Decimal Leading-Zero Anticipator

    Publication Year: 2009, Page(s):125 - 134
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (892 KB) | HTML iconHTML

    The IEEE 754-2008 Standard for Floating-Point Arithmetic was officially approved this year. One of the most important revisions to IEEE 754-1985 is the introduction of decimal floating-point (DFP) formats and operations. Since IEEE 754-1985 was revised, major microprocessor vendors have been working on hardware designs and software libraries for decimal arithmetic. Because the new standard has bee... View full abstract»

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  • A High-Performance Significand BCD Adder with IEEE 754-2008 Decimal Rounding

    Publication Year: 2009, Page(s):135 - 144
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (283 KB) | HTML iconHTML

    We present a new method and architecture to merge efficiently IEEE 754-2008 decimal rounding with significand BCD addition and subtraction. This is a key component to improve several decimal floating-point operations such as addition, multiplication and fused multiply-add. The decimal rounding unit is based on a direct implementation of the IEEE 754-2008 rounding modes. We show that the resultant ... View full abstract»

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