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Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Date 6-10 July 2009

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Displaying Results 1 - 25 of 194
  • [Front matter]

    Publication Year: 2009 , Page(s): i - iv
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  • Committee

    Publication Year: 2009 , Page(s): v - viii
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  • Content

    Publication Year: 2009 , Page(s): ix - xxiv
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  • Development of microelectronics reliability technology in China

    Publication Year: 2009 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1567 KB) |  | HTML iconHTML  

    Great advances in microelectronics failure physics, process reliability, reliability test and evaluation and failure analysis technologies have been achieved in China recently. Some of the significant achievements include the hot-carrier injection (HCI) degradation model, gate oxide TDDB, negative bias temperature instability (NBTI) of very deep sub-micro(VDSM) devices, process quality parameter monitoring (PM), statistical process control(SPC) technique, wafer-level-reliability engineering of CMOS process, the equivalent thickness method for evaluating quality and reliability of dielectrics in GaAs monolithic microwave circuits (MMICs), reliability evaluation of metallization interconnect, accurate measurement of anti-latch-up characteristics, total dose X-ray radiation evaluation, accelerated lifetime assessment of GaN/GeSi devices, reliability assurance of Known-Good-Dies (KGDs), failure location and micro-defect analysis of ICs, failure diagnosis and design verification, and the failure analysis expert systems. View full abstract»

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  • Logic LSI technology roadmap for 22 nm and beyond

    Publication Year: 2009 , Page(s): 7 - 10
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    Logic CMOS technology roadmap for dasia22 nm and beyondpsila is described with ITRS (International Technology Roadmap for Semiconductor) as a reference. In the ITRS 2008 Update published just recently, there has been some significant change in the trend of the gate length. The predicted trend has been amended to be less aggressive from the ITRS 2008-Update, resulting in the delay in the gate-length shrinkage for 3 years in the short term and 5 years in the long term from those predicted in ITRS 2007. Regarding the downsize limit, it would take probably 20 to 30 years until we reach the final limit, because the duration between the generations will become longer when approaching the limit. In order to suppress the off-leakage current, double gate (DG) or fin-FET type MOSFETs are the most promising. Then, it is a natural extension for DG FETs to evolve to Si-nanowire MOSFETs as the ultimate structure of transistors for CMOS circuit applications. Si-nanowire FETs are more attractive than the conventional DG FETs because of higher on-current conduction due to their quantum nature and also because of their adoptability for high-density integration including that of 3D. Then, what will come next after reaching the final limit of the downsizing? The answer is new algorithm. In the latter half of this century, the application of algorithm used for the natural bio system will make the integrated circuits operation tremendously high efficiency. Much higher performance with ultimately low power consumption will be realized. View full abstract»

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  • Resolution and sensitivity enhancements of scanning optical microscopy techniques for integrated circuit failure analysis

    Publication Year: 2009 , Page(s): 11 - 18
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11806 KB) |  | HTML iconHTML  

    Scanning optical microscopy techniques are effective for optical fault localization of failures that are sensitive to thermal stimulation. In this paper, the recent developments in resolution and sensitivity enhancements that allow these techniques to be used with advanced technology nodes are described. The enhancement methods include refractive solid immersion lens technology, dc-coupling of the laser induced detection system and laser pulsing with signal integration algorithm. The combination of these enhanced scanning optical microscopy techniques and refractive solid immersion lens technology has brought about significantly better localization precision and sensitivity. View full abstract»

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  • Improving failure analysis navigation Using optical super resolved imaging

    Publication Year: 2009 , Page(s): 19 - 23
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    The authors present a new numerical approach for improving the resolving power of low resolution images which is applied for failure analysis of microelectronic chips. The resolution improvement is based upon a numerical iterative comparison between a high resolution layout image and a low resolution experimentally captured image of the same region of interest. View full abstract»

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  • Using nanoprobing and SEM doping contrast techniques for failure analysis of current leakage in CMOS HV technology

    Publication Year: 2009 , Page(s): 24 - 27
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12451 KB) |  | HTML iconHTML  

    The method of substrate isolation in a typical CMOS HV technology with the addition of a deep nwell (DNW) is commonly applied in order to minimize the effect of disturbance in the substrate potential. The difficulties in identifying the true leakage path are, however, increasing as the noise current flows from this complex well structure with DNW employed in CMOS HV technology. This paper describes the use of nanoprobing and scanning electron microscope (SEM) doping contrast techniques to quickly and precisely pinpoint the leakage path. View full abstract»

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  • An advanced reliability improvement and failure analysis approach to thermal stress issues in IC packages

    Publication Year: 2009 , Page(s): 28 - 32
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12829 KB) |  | HTML iconHTML  

    A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles. View full abstract»

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  • RF performance increase allowing IC timing adjustments by use of backside FIB processing

    Publication Year: 2009 , Page(s): 33 - 36
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8834 KB) |  | HTML iconHTML  

    Dealing with timing related soft fails has become predominant with recent technologies and is expected more so future. A backside FIB edit procedure allowed trimming of internal timing conditions, with demonstrated FIB-induced speed enhancement > 20%. This proposed technique seems applicable to any on chip circuitry, expanding rapid prototyping options. View full abstract»

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  • Using a combination of C-AFM and SCM for failure analysis of SRAM leakage in CMOS process with the addition of a DNW module

    Publication Year: 2009 , Page(s): 37 - 40
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8356 KB) |  | HTML iconHTML  

    The use of scanning probe microscopes (SPM), such as conductive atomic force microscope (C-AFM) and scanning capacitance microscope (SCM) have been widely reported as a method of failure analysis in nanometer scale science and technology. This paper will demonstrate the use of the C-AFM to identify the true SRAM leakage path in CMOS process with the addition of a deep n-well (DNW) module. After taking electrical measurements, the SCM technique is utilized to identify and understand the physical root cause of the electrical failure. View full abstract»

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  • Source-side engineering to increase holding voltage of LDMOS in a 0.5-m 16-V BCD technology to avoid latch-up failure

    Publication Year: 2009 , Page(s): 41 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8357 KB) |  | HTML iconHTML  

    To avoid latch-up failure in high voltage integrated circuits, a source-side engineering technique for on-chip ESD protection nLDMOS is proposed in this work. Experimental results have been verified in a 0.5-mum 16-V bipolar CMOS DMOS technology. Measurement results from transmission-line-pulsing system show that the proposed source-side engineering method can effectively increase the holding voltage of the nLDMOS from 10.5 V to 16.2 V. Transient-induced latch-up tests show that the proposed source-side engineering technique significantly improves the latch-up immunity of nLDMOS in on-chip ESD protection circuit. View full abstract»

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  • Chip-level and board-level CDM ESD tests on IC products

    Publication Year: 2009 , Page(s): 45 - 49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5759 KB) |  | HTML iconHTML  

    The electrostatic discharge (ESD) transient currents and failure analysis (FA) between chip-level and board-level charged-device-model (CDM) ESD tests are investigated in this work. The discharging current waveforms of three different printed circuit boards (PCBs) are characterized first. Then, the chip-level and board-level CDM ESD tests are performed to an ESD-protected dummy NMOS and a high-speed receiver front-end circuit, respectively. Scanning electron microscope (SEM) failure pictures show that the board-level CDM ESD test causes much severer failure than that caused by the chip-level CDM ESD test. View full abstract»

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  • Logic failure analysis 65/45nm device using RCI & nano scale probe

    Publication Year: 2009 , Page(s): 50 - 53
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4605 KB) |  | HTML iconHTML  

    Scan chain failure analysis is more difficult and complicated compared to memory analysis and analysis of defect monitoring test element group (DTEG) which has a large area is also difficult. This paper has verified that various defects of logic process sub 65nm device are easily analyzed through Resistive Contrast Imaging (RCI) and nanoprobe. In addition, Metal5 (M5) bridge defect (Short case) was detected in failure of scan ATPG (Automatic Test Pattern Generation) which has long failing nets and by discovering Via4 (V4) open defect (Open case) by Unetch, it was confirmed that it is possible to analyze high resistance Via failure. And it was verified that position of Cu line void of metal7 (M7) can be localized at high level metal layer. It is judged that it will be used usefully in failure analysis sub 65nm in the future as a technique utilizing principle of RCI and nanoprobe and also it will make lots of contributions to improvement of yield. View full abstract»

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  • Investigation of thermal budget impact on core CMOS SRAM device in an embedded FLASH technology

    Publication Year: 2009 , Page(s): 54 - 58
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6221 KB) |  | HTML iconHTML  

    This paper presents insights into the mechanisms of counter doping and gate depletion due to the lateral diffusion of dopants in embedded flash technology. Core SRAM device behavior is modified by the thermal budget needed to process the specific flash dielectrics. Using a nanoprobe technique, the MOS characteristics of failed and good bits used as a reference in actual SRAM cells were measured directly. In the worst cases, it was confirmed that the on-state current of a PMOS was about three orders of magnitude smaller than that of normal bits, and the threshold voltage was of about 0.9 V higher. A selective etching technique using a KOH solution showed these degradations were caused by local gate depletion. The fabrication process flow shows that the thermal treatment used to form the rapid thermal oxidation layer, causing additional thermal budget, can lead to lateral As-dopant diffusion into a B-doped gate. This diffusion can cause work-function shift, as well as the formation of a depletion capacitor at the polysilicon gate oxide interface, while the MOS is biased. Adjusting the N+ implant boundary for the second poly layer to increase the margin has been found to be quite effective in improving the on-state current degradation and increasing yield. View full abstract»

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  • Failure analysis of process-induced particle contamination acting as masks that block implantation using C-AFM and chemical etching

    Publication Year: 2009 , Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10668 KB) |  | HTML iconHTML  

    Ion implantation is one of the most common steps in the manufacture of integrated circuits. The characterization and visualization of process-induced particle contamination acting as masks that block implantation especially when the defects are not in a specific area of a chip takes a lot of effort. This paper describes the use of a Conductive Atomic Force Microscope (C-AFM) technique coupled with wet chemical etching analysis to quickly make different implants visible at low cost. View full abstract»

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  • Towards a viable TDDB reliability assessment methodology: From breakdown physics to circuit failure

    Publication Year: 2009 , Page(s): 63 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4950 KB) |  | HTML iconHTML  

    In this paper, the advances in the understanding of breakdown statistics and physics of the so-called first breakdown (BD) phenomena are presented. Then the recent findings on post-breakdown effects and the impact of oxide BD on device failure and circuit functionality are reviewed. With this state-of-the-art understanding of the first BD methodology and post-BD methodologies, a robust reliability projection methodology can be developed for SiO2-based dielectrics which covers a wide range of oxide thicknesses and applied voltages. Furthermore, these advances will allow the development of a viable circuit-level reliability assessment methodology from basic breakdown physics. View full abstract»

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  • Post-breakdown conduction in metal gate/MgO/InP structures

    Publication Year: 2009 , Page(s): 71 - 74
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    The electrical behavior of broken down thin films of magnesium oxide (MgO) grown on indium phosphide (InP) substrates was investigated. To our knowledge, this is the first report that identifies the Soft Break Down (SBD) conduction mode in a metal gate/high-kappa/III-V semiconductor structure. It is shown that the leakage current associated with this failure mode follows the power-law model I=aVb for both injection polarities in a voltage range that largely exceeds the one reported for SiO2. We also show that the Hard Break Down (HBD) current is remarkably high, involving significant thermal effects that are believed to be at the origin of the switching behavior exhibited by the I-V characteristics. View full abstract»

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  • Improving reliability and diminishing parasitic capacitance effects in a vertical transistor with embedded gate

    Publication Year: 2009 , Page(s): 75 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (13013 KB) |  | HTML iconHTML  

    We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional VMOS. View full abstract»

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  • Comparison of charge trapping in silicon dioxide and hafnium dioxide at nanoscale

    Publication Year: 2009 , Page(s): 79 - 82
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    In this paper, we report a new measurement technique that can be used to determine the nanoscale charge trapping properties of gate oxide. Forward and backward sweep ramped voltage were applied to the samples in order to measure the nanoscale I-V characteristics using conductive atomic force microscopy (CAFM) in conjunction with a semiconductor parameter analyzer, Agilent 4156C. From the voltage hysteresis between the forward and backward sweeps I-V characteristics at a fixed current level, we successfully compared the differences between the nanoscale charge trapping in thermal SiO2 and ALD HfO2 gate dielectrics. View full abstract»

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  • Study and optimization of hot-carrier degradation in high voltage pledmos transistor with thick gate oxide

    Publication Year: 2009 , Page(s): 83 - 86
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    The degradations of p-type lateral extended drain MOS transistors with thick gate oxide are experimentally investigated. A novel structure is proposed with a low doped boundary of the drift region without additional process, which will be helpful in reducing the electric field, reducing the degradations of electrical parameters correspondingly. The effects have been detailed analyzed by the CP measurements and MEDICI simulations. Our of the simulations results, the length of the low doped boundary of the drift region is discussed and their effect on the degradation induced by hot carriers has been investigated. An optimization structure is proposed. View full abstract»

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  • The effect of polyimide surface treatment on flip-chip assembly

    Publication Year: 2009 , Page(s): 87 - 90
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9960 KB) |  | HTML iconHTML  

    This paper studied the effects of polyimide surface morphology and RIE treatment for lead-free C4 bumping of SOI device on assembly process by flip-chip technique. The characterizations were experimentally carried out with FTIR, AFM and CSAM. The process sequences have been optimized based on the DOE results. View full abstract»

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  • Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor

    Publication Year: 2009 , Page(s): 91 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8947 KB) |  | HTML iconHTML  

    This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that this study can help us understand the influence of body-tied scheme on the properties of poly-Si TFT. View full abstract»

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  • Failure analysis of Through-Silicon-Vias Aided by high-speed FIB silicon removal

    Publication Year: 2009 , Page(s): 94 - 99
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9290 KB) |  | HTML iconHTML  

    High-speed FIB silicon trenching is used to remove substrate materials around large structures on semiconductor devices. After removing the surrounding substrate material, it is possible to perform FIB cross-sectional analyses on structures that would normally be too large for such an approach. Through-silicon-vias (TSVs) are examined in detail, but other applications are also briefly described. View full abstract»

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  • Failure analysis overview and its new challenges

    Publication Year: 2009 , Page(s): 100 - 107
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (16424 KB) |  | HTML iconHTML  

    Failure analysis is a critical step for solving design, process, product and customer application issues. Failure analysts need to have strong and broad technical background as well as unique personality to be successful in this field. Failure analysis flow contains 8 basic steps, and should be followed to ensure the quality of the daily analysis work. Three case studies were demonstrated on how to use the 8-step FA flow to solve real life problems. With new technology, device materials and architecture in advanced products, new challenges need to be met in order to successfully support the failure analysis needs in the coming years. View full abstract»

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