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Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.

Date 12-17 July 2009

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Displaying Results 1 - 25 of 90
  • On-chip charge-pump with continuous frequency regulation for precision high-voltage generation

    Publication Year: 2009 , Page(s): 68 - 71
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (982 KB) |  | HTML iconHTML  

    Closed-loop operation of charge-pumps is often taken advantage of in order to improve efficiency and to reduce the charge-pump output impedance and heavy sensitivity to supply and process variations. A fully integrated charge-pump, which utilizes continuous frequency control for the closed-loop operation, is presented in this paper. This means of control allows the charge-pump clock to settle to correct frequency according to current load while maintaining 50% duty ratio of the clock. The final high-voltage signal is generated by using a closed-loop amplifier, for which the pump creates the supply, and which then amplifies the desired low-voltage signal to correct level. The implemented pump with the regulator has an active chip area of 0.14 mm2 and creates a nominal output of 10 V with 29 muA load current and 2.5 V minimum supply. View full abstract»

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  • Fully integrated 5.6–6.4 GHz power amplifier using transformer combining

    Publication Year: 2009 , Page(s): 160 - 163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (562 KB) |  | HTML iconHTML  

    A fully integrated 5.6-6.4 GHz power amplifier is implemented in a 0.25 mum SiGe-HBT technology using an on-chip transformer combining structure. The novel combiner topology combines the output power of two push pull pairs and leads to a reduced transistor size compared to a conventional combiner while enhancing the efficiency and maintaining the maximum output power. Electromagnetic modeling of the whole chip layout has been carried out to optimize the performance of the presented circuit. At 6 GHz and a supply voltage of 1.2/1.8 V the single-stage power amplifier achieves a measured output power of 18/21 dBm at 1 dB power compression and 21/24 dBm in saturation region. The maximum power added efficiency is 24.7%. A small signal gain of 12 dB was observed at the center frequency of 6 GHz. View full abstract»

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  • CMOS phase-interpolation DDS for an UWB MB-OFDM Alliance application

    Publication Year: 2009 , Page(s): 200 - 203
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB) |  | HTML iconHTML  

    This paper presents a novel concept of using a phase-interpolation direct digital synthesizer for an Ultra Wideband MB-OFDM Alliance application as a low silicon area alternative to state of the art solutions. In particular, an investigation of the spurious tones in such direct digital synthesizer is presented and ways how to reduce their presence are discussed. The design and simulation of the critical blocks made using a 65-nm CMOS process are also presented. View full abstract»

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  • A 10bit 1.1V 130MS/s 0.125mm2 pipeline ADC for flat-panel display applications in 65nm CMOS

    Publication Year: 2009 , Page(s): 4 - 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (583 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of a low-voltage low-power high speed pipeline analog-to-digital converter (ADC) for flat-panel display application fabricated in a standard digital 65 nm CMOS technology. The ADC does not use a dedicated sample-and-hold (S&H) stage and is built by means of the cascade of 8 pipeline stages and a 2-bit flash ADC. Operational amplifier sharing technique is applied in order to reduce power consumption. Nested cascoded miller compensation technique is used to optimize speed and power of the first and second stage. Performance of 56.5 dB SNDR at 5 MHz and 50 dB at 85 MHz input frequency is obtained at 130MS/s for full-scale. The occupied silicon area is 0.125 mm2, and the power consumption of 33 mW from a 1.1 V supply. View full abstract»

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  • Large-signal settling optimization of SC circuits using two-stage amplifiers with current-buffer miller compensation

    Publication Year: 2009 , Page(s): 328 - 331
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (465 KB) |  | HTML iconHTML  

    The large-signal performances of switched-capacitor (SC) circuits employing two-stage operational amplifiers (opamps) with current-buffer Miller compensation are analyzed. Well-defined rules to fix carefully the bias currents of the two op-amp stages are proposed in order to optimize the amplifier settling behavior. Simulation results related to op-amps designed in a commercial 0.35 ¿m CMOS technology show the usefulness of the proposed design guidelines. View full abstract»

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  • Comparative study of the MASH digital delta-sigma modulators

    Publication Year: 2009 , Page(s): 196 - 199
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (718 KB) |  | HTML iconHTML  

    The paper focuses on the Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) that employs multi-moduli (MM-MASH). Different architectures of the MASH DDSM are compared. In particular, it is proven that a higherorder error feedback modulator (EFM) has the same sequence length as a first-order EFM (EFM1) in an MM-MASH. In addition, the method that is required to setup the quantisation moduli of the MM-MASH is introduced. The theory is validated by simulation. View full abstract»

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  • A FM-radio transmitter concept based on an all-digital PLL

    Publication Year: 2009 , Page(s): 192 - 195
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    A stereo FM-radio transmitter with Radio Data System (RDS) support based on an all-digital PLL is presented. It has been designed as a fully integrated single-chip transmitter in a 90-nm CMOS technology to be compatible with digital deep-submicrometer processes. Target application of the proposed system is the cointegration with baseband processors and transmitters for mobile communication systems. Nowadays mobile phones have a lot of multimedia capabilities e. g. an integrated MP3 player. The proposed transmitter enables a mobile device to stream audio data to a FM receiver which is popular and existing in most households world wide. RDS support allows to send additional information e. g. title and artist of a song. As mobile applications are the main target for the transmitter great attention has been attached to saving power and area. Therefore, the presented transmitter works on a 1 V supply voltage and is aimed for using a 32.768 kHz reference crystal oscillator instead of the commonly used 26 MHz reference oscillator while still providing wideband frequency modulation capability. View full abstract»

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  • Hierarchical modeling of a 2.4-GHz power amplifier for energy consumption analysis at system level

    Publication Year: 2009 , Page(s): 164 - 167
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1080 KB) |  | HTML iconHTML  

    In this paper the hierarchical modeling of a 2.4-GHz RF power amplifier with its energy consumption considerations is presented. The models foresee the component's total power consumption as one of its high-level parameters, in addition to gain, input and output impedances and third order nonlinearities. Hence an estimation of the energy consumed by the transmitter can be achieved at the system level of design, due to the inclusion of amplifier's efficiency (¿), first within an intermediate model (VHDL-AMS) and later at highest level, using Matlab and Simulink. View full abstract»

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  • Yield analysis of active mixers with N-bit IIP2-tuning

    Publication Year: 2009 , Page(s): 84 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB) |  | HTML iconHTML  

    In this paper, we study the effect of a simple load resistor tuning on the IIP2 yield of active down-conversion mixers. Without IIP2 tuning, only 46% of the mixers designed in a 65-nm standard digital CMOS technology meet the IIP2 requirement of the WCDMA standard. We investigate how much the yield can be increased with a digitally controlled load resistance tuning as a function of the number of control bits. We show that the the IIP2 yield can be increased from 46% to 97% with a 5-bit tuning. The tuning is efficient even with considerable phase and amplitude errors in the LO and RF signals. View full abstract»

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  • Read range limitation in IF-based far-field RFID using ASK backscatter modulation

    Publication Year: 2009 , Page(s): 348 - 351
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (465 KB) |  | HTML iconHTML  

    A model is proposed to describe the fundamental read range limitation due to the local oscillator phase noise in the reader, in IF-based, far-field RFID systems using amplitude-shift keying backscatter modulation. The relation between the system parameters (such as the data transfer rate) and the read range is discussed. The model is validated by measurements done on two different laboratory tag-reader systems. View full abstract»

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  • An EPC Class-1 Generation-2 baseband processor for passive UHF RFID tag

    Publication Year: 2009 , Page(s): 52 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (581 KB) |  | HTML iconHTML  

    Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation- 2 EPC Protocol, and proposes different techniques for reducing its power consumption. After code validation with an FPGA, the processor has been synthetised in a 0.35 mum CMOS technology process and occupies 7 mm2 including pads. The design also incorporates a 10-b rail-to-rail SAR ADC for sensory applications. Under maximum digital activity conditions, post-layout simulations show that the power consumption of the processor below 2.8 muW. View full abstract»

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  • A variable gain 2.4-GHz CMOS low noise amplifier employing body biasing

    Publication Year: 2009 , Page(s): 168 - 171
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1499 KB) |  | HTML iconHTML  

    In this paper, a variable gain CMOS low noise amplifier (LNA) suitable for WiMAX (Worldwide Interoperability for Microwave Access) applications, 2.4 GHz, is reported. The design concept is based on the novel idea of body biasing. In high mode gain the cascode LNA, implemented in a 0.13 ¿m CMOS standard process and supplied under 1.1 V, exhibits a power gain of 15.44 dB, a 2.87 dB noise figure (NF), and -4.62 dBm of third order intercept point (IIP3) for a 4.64 mA current consumption and a bulk to source Voltage, VBS, of 0.3 V. Tuning VBS to -0.55 V, the LNA operates in the low gain mode, achieving 8.23 dB of power gain, 5 dB NF and 6.63 dBm IIP3 under a constrained power consumption of 1.1 mW. View full abstract»

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  • On-chip sine wave frequency multiplier for 40-GHz signal generator

    Publication Year: 2009 , Page(s): 284 - 287
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB) |  | HTML iconHTML  

    This paper presents a novel signal frequency multiplier for very high speed applications. The proposed circuit is based on a simple but effective folding cell and it is able to generate an output at four times the frequency of the differential sine wave input. The circuit has been designed and optimized for a 40-nm CMOS technology and it has been fully simulated at the transistor level. Possible fabrication and timing mismatches are corrected with foreground calibration. Simulation results shows that the multiplier can provide an output signal at 40 GHz starting from a 10-GHz input signal consuming about 5 mW. View full abstract»

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  • Heterogeneously encoded dual-bit self-timed adder

    Publication Year: 2009 , Page(s): 120 - 123
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (453 KB) |  | HTML iconHTML  

    A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit switching power dissipation compared to the basic dual-rail (1-of-2, which is the simplest 1-of-n code) encoding scheme. Here, n specifies the number of physical lines. The number of transitions gets reduced by O(k) over a dual-rail code, with k being the number of primary inputs and equals log2n. The design of a dual-bit adder is considered to illustrate the advantage of the heterogeneous encoding scheme. The proposed adder design satisfies Seitz's weak-indication timing constraints. In comparison with dual-bit adders realized using other approaches, employing dual-rail encoding or heterogeneous encoding, the proposed design is found to be efficient in terms of delay, power consumption and area parameters. View full abstract»

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  • CMOS correlation receiver for UWB pulse radar

    Publication Year: 2009 , Page(s): 356 - 359
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (999 KB) |  | HTML iconHTML  

    A correlator-based receiver of an UWB radar for cardio-pulmonary monitoring is presented. It consists of low noise amplifier, analog multiplier and integrator. The UWB LNA shows a measured -3 dB band close to 5 GHz, from 3.56 and 8.46 GHz, a transducer gain of 22.7 dB at 5.2 GHz, an input reflection coefficient lower than -10.5 dB in -3 dB band, and a input-referred 1-dB compression point of -19.7 dBm, in excellent agreement with the post-layout simulation results. The multiplier shows a direct conversion gain (GC) equal to 4.3 at 5 GHz, and implements the analog multiplication with a good linearity. The integrator (i.e. OTA) shows a -3 dB band of 40 Hz, a voltage gain of 32 dB and a phase margin of 90 degree with an input linear range of 100 mV. In the linear range the OTA is characterized by a THD of about -38 dB. View full abstract»

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  • A UHF voltage multiplier circuit using a threshold-voltage cancellation technique

    Publication Year: 2009 , Page(s): 288 - 291
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    The operating range of passive UHF transponder systems is largely determined by the tag current consumption and the rectifier efficiency. Reading ranges of several meters have recently been reported for many state of the art RFID (Radio frequency IDentification) tags [1]. At this distance, the main issue for the rectifier design is the low amplitude of the high frequency antenna signal. Schottky diodes are often used for their low forward voltage drop and high switching speed. As an alternative to Schottky diodes, different circuit techniques for compensating the threshold voltage of standard transistor diodes have been utilized [4]. The transistor gates are biased near the threshold voltage, so that the devices effectively act as diodes with very low forward voltage drop. In the presented rectifier, a secondary diode charge pump is used to generate the DC bias for the threshold voltage compensation. The circuit is implemented in a standard CMOS technology and operates at a minimum available power of -11.3 dBm for an output DC power of 7.5 ¿W. View full abstract»

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  • Sub-threshold operation of a timing error detection latch

    Publication Year: 2009 , Page(s): 124 - 127
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (621 KB) |  | HTML iconHTML  

    Significant demand for utlra-low power applications has provided an advantage for circuits capable of sub-threshold operation. The reduction of the supply voltage (Vdd) below the threshold voltage (VT ) of transistors, or sub-threshold, provides minimum energy consumption in digital CMOS logic. The exponential dependence of the drain current on VT variations leads to increased overdesign if sub-threshold circuits are to be robust. One solution to variability robustness is timing error detection (TED). Presented here is a TED latch capable of subthreshold operation. It was designed in 65 nm CMOS, has an operating voltage range of 0.2 V through 1.2 V, and a minimum energy point (MEP) of 0.4 V. At the MEP, the average power consumption for one clock period and an activity factor of alpha=0.5 is 0.37 nW. The area of the TED latch is 93 mum2. View full abstract»

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  • Design of a 3 Bit 20 GS/s ADC in 65 nm CMOS

    Publication Year: 2009 , Page(s): 1 - 3
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (506 KB) |  | HTML iconHTML  

    A 20 GS/s 3 bit flash ADC with an analog input bandwidth of 10 GHz is realized in a 65 nm LP CMOS technology. By employing a fourfold parallelization a high sample rate is achieved, while a large input bandwidth is maintained. Simulations at 20 GS/s exhibit an effective resolution of 2.5 Bits at the Nyquist frequency. The chip area is 5.2 mm2 while the ADC core area is 0.16 mm2. View full abstract»

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  • Design of 1Gs/s open-loop Track-and-Hold for 10GBASE-T Ethernet receivers

    Publication Year: 2009 , Page(s): 344 - 347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    A 1Gs/s CMOS track-and-hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65 nm low-power CMOS process, exhibits a total harmonic distortion lower than -80 dB and a spurious free dynamic range better than 79 dB, with a power consumption lower than 11 mW (dual supply voltages 1.2 V/2.5 V, 1.85 mA/4.22 mA). View full abstract»

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  • Design of floating point units for interval arithmetic

    Publication Year: 2009 , Page(s): 12 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (758 KB) |  | HTML iconHTML  

    In this paper, hardware units for interval addition, multiplication and divide-add fused are presented. Regarding interval addition, a new architecture of double path adder, is presented. This architecture exploits the parallel structure of double path adder. Regarding multiplication, the proposed architecture is based on a dual result multiplier (floating point multiplication unit with two differently rounded results for the same pair of operands) and two floating point comparators. The goal of the divide-add fused unit is to increase the performance of the interval Newton's method. Algorithm and architecture for this operation, inspired by the ones used for multiply-add fused, are proposed. View full abstract»

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  • Lumped element band pass filter design on 130nm CMOS using delta-star transformation

    Publication Year: 2009 , Page(s): 32 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    This paper presents the design of a 10 GHz lumped element band pass filter on standard 130 nm CMOS technology. A series coupled resonator topology is selected due to its advantages over classical low-pass to band-pass filter mapping. A delta-star transformation technique is used in the network synthesis to minimise the impact of stray capacitances, and to avoid the problem of fabricating excessively small coupling capacitors. View full abstract»

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  • Reduction of up-converted flicker noise in differential LC-VCO designed in 32nm CMOS technology

    Publication Year: 2009 , Page(s): 232 - 235
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    This paper deals with the design of LC Voltage Controlled Oscillator (LC-VCO) for GSM applications, implemented in a state-of-the-art 32 nm Planar CMOS technology. A standard VCO is compared with a topology featuring tail decoupling, which, to best of our knowledge, is used for the first time for a wide tuning-range application (i.e. 700 MHz centered at 3.65 GHz). The Decoupled VCO significantly reduces the Phase-Noise, up to 9 dB, by lowering the impact of the flicker noise introduced by the switching-pair on the 1/f3 region, with comparable current consumption and tuning-range with respect to the standard VCO. View full abstract»

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  • A novel LV LP CMOS internal topology of CCII+ and its application in current-mode integrated circuits

    Publication Year: 2009 , Page(s): 132 - 135
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (569 KB) |  | HTML iconHTML  

    In this paper we present a novel internal architecture of low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed internal circuit topology, designed in standard CMOS technology (AMS 0.35 ¿m), employs an n-type differential pair as input stage, while a cascoded push-pull configuration implements a very high impedance output stage. A degenerated nMOS common drain topology reduces X node impedance. The choice of internal CCII+ architecture, concerning both its stage architecture and transistor sizes, has been made in the direction of designing a quasi-ideal CCII+ in terms of parasitic components at its terminals. The developed CCII+ operates at low supply voltages of ±1 V with a total power consumption of about 300 ¿W, so it is suitable for general purpose portable applications. It has been also characterized implementing well-known applications, both in time and frequency domains, such as signal processing circuits and impedance simulators. View full abstract»

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  • Design of a low noise, low power 3.05–3.45 GHz digitally controlled oscillator in 90 nm CMOS

    Publication Year: 2009 , Page(s): 228 - 231
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2083 KB) |  | HTML iconHTML  

    The design of a multi-GHz digitally controlled oscillator (DCO) achieving low noise and power consumption is presented. The DCO is part of an all-digital phase lock loop (ADPLL) for an FM-radio transmitter prototype chip designed in a 90 nm CMOS process. For this application the oscillator frequency of 3.05-3.45 GHz is divided by 32 or 36 to cover the frequency span of 87.5-108.0 MHz. A wide tuning range combined with a precise frequency tuning is achieved by different digitally controlled variable capacitors grouped as banks. Different approaches of these variable capacitors and oscillator topologies are simulated and compared. The design is chosen considering low phase noise combined with low power consumption. The power consumption of the designed DCO core is below 1.7 mW at 1 V supply voltage. This setup shows a phase noise below -154 dBc/Hz at 20 MHz offset. The chip area utilised by one DCO is 260 times 500 mum. Simulations show the performance of this DCO is state-of-the-art. View full abstract»

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  • Analysis on power harvesting circuits with tunable matching network for improved efficiency

    Publication Year: 2009 , Page(s): 96 - 99
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (456 KB) |  | HTML iconHTML  

    This paper presents the necessity and potential of using tunable matching network in UHF RFID transponders. A compact I/V model for diode-connected MOSFET in strong inversion and sub-threshold regions, which is based on the UMC 0.13-¿m technology, is utilized to analyze the influence of the dynamic load to the performance of the power harvesting circuit. A direct dependence of the voltage sensitivity on the varying load current has been found and formulated. The dependence suggests the necessity of optimizing dynamically the impedance matching network between the antenna and the rectifier according to the transponder operation status. A concept of the operation-controlled tunable matching network is finally proposed. View full abstract»

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