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Test Symposium, 2009 14th IEEE European

Date 25-29 May 2009

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  • [Cover art]

    Publication Year: 2009 , Page(s): C1
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  • [Title page i]

    Publication Year: 2009 , Page(s): i
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  • [Title page iii]

    Publication Year: 2009 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009
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  • Table of contents

    Publication Year: 2009 , Page(s): v - vii
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  • Foreword

    Publication Year: 2009 , Page(s): viii
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  • Organizing Committee

    Publication Year: 2009 , Page(s): ix - x
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  • Steering and Program Committee

    Publication Year: 2009 , Page(s): xi
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  • Best Paper Award

    Publication Year: 2009 , Page(s): xii
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  • TTTC: Test Technology Technical Council

    Publication Year: 2009 , Page(s): xiii - xv
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  • Plenary Presentations ETS 2009 [breaker page]

    Publication Year: 2009 , Page(s): xvi
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  • We have got compression, what next?

    Publication Year: 2009 , Page(s): xvii
    Cited by:  Papers (1)
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  • Something I Always Wanted to Know About Test, But Was Afraid to Ask

    Publication Year: 2009 , Page(s): xviii
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  • Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation

    Publication Year: 2009 , Page(s): 3 - 8
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (493 KB) |  | HTML iconHTML  

    Linearity testing of high resolution analog-to-digital Converters (ADCs) requires test instrumentation that has high precision digital-to-analog conversion (DAC) capability. Further, a large number of samples need to be collected for linearity testing of high resolution ADCs (18-24 bit) to guarantee test quality. In this paper a novel fast linearity testing approach is proposed for testing high resolution ADCs using a low precision DAC and a potentiometer. A polynomial fit of the transfer function of the ADC is generated using measurements made at intermediate code points. The test setup and analysis procedure makes no assumption about the linearity of the lower precision DAC or the potentiometer used to generate the ADC test stimulus. A least squares based polynomial fitting approach is used to characterize the transfer function of the ADC. The computed transfer function is then used to estimate the Integral Non-Linearity (INL) and the Differential Non-Linearity(DNL) of the system accurately. Software simulations and hardware experiments are performed to validate the proposed methodology. View full abstract»

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  • Speed-Path Debug Using At-Speed Scan Test Patterns

    Publication Year: 2009 , Page(s): 11 - 16
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    Speed path debug is a critical step to improve the performance of high performance VLSI designs. The purpose of speed path debug is to identify the performance limiting paths and fix them in the next product stepping so that the chip can run at a higher clock frequency. This paper investigates speed path debug techniques using at-speed scan test patterns. For each failing scan cell, the failing paths are identified based on structural analysis of logic simulation values. We further propose two metrics to rank the identified speed paths based on logic value analysis and based on timing information calculated for the failing pattern. Experimental results show the effectiveness of the proposed speed path debug technique. View full abstract»

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  • Resource-Efficient Programmable Trigger Units for Post-Silicon Validation

    Publication Year: 2009 , Page(s): 17 - 22
    Cited by:  Papers (8)  |  Patents (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (862 KB) |  | HTML iconHTML  

    The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. In this paper, we investigate how to design trigger units that are both resource-efficient and runtime programmable. To achieve these two goals, we introduce new architectural features, as well as an algorithm for automatically mapping trigger events onto trigger units. View full abstract»

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  • On Minimization of Peak Power for Scan Circuit during Test

    Publication Year: 2009 , Page(s): 25 - 30
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (183 KB) |  | HTML iconHTML  

    Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power, below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%. View full abstract»

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  • Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors

    Publication Year: 2009 , Page(s): 33 - 38
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Multiprocessors and multithreaded architectures are constantly becoming the typical general-purpose computing paradigm, and thus the various existing uniprocessor functional self-testing schemes must be adopted and adjusted to meet the testing requirements of complex multiprocessors. A major challenge in porting a functional self-testing approach from the uniprocessor to the multiprocessor case is to take advantage of the inherent execution parallelism offered by the multiple cores and the multiple threads in order to reduce test execution time. In this paper, we study the application of functional self-testing to chip multithreaded (CMT) processors. We propose a method that exploits thread-level parallelism (TLP) to speed up the execution of self-test routines in every physical core of a multiprocessor chip. The proposed method effectively splits the self-test routines into shorter ones, assigns the new routines to the hardware threads of the core and schedules their execution in order to minimize the core idle intervals due to cache misses or long latency operations and maximize the utilization of core computing resources. We demonstrate our method in the open-source CMT multiprocessor model, Sunpsilas OpenSPARC T1, which contains eight CPU cores, each one supporting four hardware threads. Our experimental results show a self-test execution speedup of more than three times compared to the single thread execution. View full abstract»

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  • Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment

    Publication Year: 2009 , Page(s): 39 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (215 KB) |  | HTML iconHTML  

    This paper reports the experience being made during the implementation of low pin count techniques and their insertion into a production environment. The techniques applied are "on-loadboard compare" and "shared driver". Already known on a concept level for an on-chip approach, in this paper the transfer to an on-loadboard solution is presented. Emphasis is put on production related aspects. Practical experience, challenges, and pitfalls are described to allow a better assessment of risks and benefits of the investigated methods. View full abstract»

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  • Algorithms for ADC Multi-site Test with Digital Input Stimulus

    Publication Year: 2009 , Page(s): 45 - 50
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as the test stimulus reliving the burden placed on accuracy requirement of excitation source. The objective of the test scheme is not to completely replace traditional specification-based tests, but to provide a reliable method for early identification of excessive parameter variations in production test that allows quickly discarding of most of the faulty circuits before going through the conventional test. The efficiency of the methods is validated on a 6-bit flash ADC. View full abstract»

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  • Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead

    Publication Year: 2009 , Page(s): 53 - 58
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (239 KB) |  | HTML iconHTML  

    Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test latency, which reduces the likelihood of fault accumulation. Experiments with a large number of circuits show that the hardware overhead is significantly lower than the overhead for previously published methods. Furthermore, the method allows to tradeoff fault coverage, test latency and hardware overhead. View full abstract»

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  • Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections

    Publication Year: 2009 , Page(s): 61 - 66
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (537 KB) |  | HTML iconHTML  

    Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive states depending upon the material nature integrated in memory element. To lead such memory concept to a memory circuit or even, to a product, a big effort has to be done to forecast tools necessary to design and test this emerging memory. In this paper, a particular technology of ReRAM memories is introduced. First, an electrical model (ELDO-like) of a MIM-based (Metal/Insulator/Metal) ReRAM memory element is presented. Then, this model is used for the robustness assessment of ReRAM memory element in presence of actual defects inherent to CMOS process steps. Based on this electrical model, a big hurdle has been broken between material physics, design and test. Thus, new methods and solutions could be developed in the field of design and test for ReRAM memories. View full abstract»

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  • Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications

    Publication Year: 2009 , Page(s): 67 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (301 KB) |  | HTML iconHTML  

    Efficient screening procedures for the control of the gate oxide defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel approach to the gate stress test of Lateral Diffused MOS transistors based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed built-in gate stress test procedure are described in very detail and illustrated by circuit simulation. View full abstract»

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  • Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems

    Publication Year: 2009 , Page(s): 73 - 78
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    Electrodes are fundamental to the reliable operation of a new generation of portable bio-analytical instruments based around microsystems technology. The importance of eliminating false positives and false negatives for these instruments is driving work around embedded test, condition monitoring and both diagnostics and prognostics. This paper proposes two solutions for detecting degradation in electrodes that interface to fluidic or biological systems and form the basis of numerous actuation and sensing mechanisms in the bio-fluidics area. A low frequency, impedance based method for identifying degraded structures within an array is proposed that is backed up by physical measurements from an electrode array for drug testing on cardiac and neuron tissue. In addition, a mid-frequency oscillation test is proposed which is based on the sensitivity of the bio-fluidic interface capacitance to degradation, contamination and fouling. View full abstract»

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  • Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques

    Publication Year: 2009 , Page(s): 81 - 86
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    Due to the increased speed in modern designs, testing for delay faults has become an important issue in the post-production test of manufactured chips. A high fault coverage is needed to guarantee the correct temporal behavior. Today's ATPG algorithms have difficulties to reach the desired fault coverage due to the high complexity of modern designs. In this paper, we describe how to efficiently integrate the reuse of learned information into state-of-the-art SAT-based ATPG algorithms and, by this, reduce the number of unclassified faults significantly. For further reduction, a post-classification phase is presented. Experimental results for ATPG for delay faults on large industrial circuits show the robustness and feasibility of the approach. View full abstract»

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