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2009 IEEE International Conference on IC Design and Technology

Date 18-20 May 2009

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Displaying Results 1 - 25 of 65
  • [Front cover]

    Publication Year: 2009, Page(s): c1
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  • [Title page and copyright notice]

    Publication Year: 2009, Page(s):i - ii
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  • Committee members

    Publication Year: 2009, Page(s): iii
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  • ICICDT tutorials

    Publication Year: 2009, Page(s):iv - vii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (178 KB)

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • A sub 2W low power IA processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

    Publication Year: 2009, Page(s): viii
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  • QorIQ P4080 Communications Processor design in 45nm SOI

    Publication Year: 2009, Page(s): viii
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  • Plenary & workshop sessions

    Publication Year: 2009, Page(s):ix - xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (265 KB)

    Provides an abstract for each of the plenary presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Table of contents

    Publication Year: 2009, Page(s):xiii - xix
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  • Author index

    Publication Year: 2009, Page(s):253 - 254
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  • [Back cover]

    Publication Year: 2009, Page(s): c4
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  • Custom design in a low-power/high-performance ASIC world

    Publication Year: 2009, Page(s):1 - 2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB) | HTML iconHTML

    Aggressive design cycle requirements are making it increasingly difficult to deploy custom and even semi-custom design techniques in consumer ASIC's. However, market requirements continue to push IP implementation teams harder and harder for increased performance and reduced power consumption. Given these two conflicting trends, new design methodologies are required, such that IP design teams can ... View full abstract»

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  • A low-power and multi-mode design approach for reconfigurable MASH SDM

    Publication Year: 2009, Page(s):3 - 6
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB) | HTML iconHTML

    In this paper, a sixth order multi-stage sigma-delta modulator is designed for GSM/WCDMA/WiMAX communication systems. With the multi-stage noise shaped architecture, the proposed modulator can reconfigure to adapt different system specifications. Meanwhile, the power dissipation is also flexible for power optimization. A prototype is designed with the 0.13-mum 1P8M CMOS technology. The simulation ... View full abstract»

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  • Implementation and evaluation of fine-grain run-time power gating for a multiplier

    Publication Year: 2009, Page(s):7 - 10
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (551 KB) | HTML iconHTML

    In a 32btimes32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due ... View full abstract»

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  • Improvement of LDO's PSRR deteriorated by reducing power consumption : Implementation and experimental results

    Publication Year: 2009, Page(s):11 - 15
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    In this work, a Bulk-Gate Controlled Circuit, for improving power supply rejection ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) which deteriorates due to lowering of power consumption is proposed. A test chip was fabricated using 0.18-mum CMOS process. Experimental results of the test chip demonstrate that the proposed circuit provides a high performance of PSRR which is up to 77 dB at 10... View full abstract»

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  • Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs

    Publication Year: 2009, Page(s):17 - 20
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1036 KB) | HTML iconHTML

    We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-VTH) operation of highly scaled devices. We find that the sub-VTH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by channel dimension scaling and reducing the gate overdrive into the sub-VTH regime. These large RTN fluctuations greatl... View full abstract»

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  • Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

    Publication Year: 2009, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (949 KB) | HTML iconHTML

    A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7 kV human-... View full abstract»

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  • ESD protection for RF/AMS ICs: Design and optimization

    Publication Year: 2009, Page(s):25 - 28
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (413 KB) | HTML iconHTML

    This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD p... View full abstract»

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  • A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique

    Publication Year: 2009, Page(s):29 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1409 KB) | HTML iconHTML

    A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3 times VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. ... View full abstract»

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  • Recent advances in RF-LDMOS high-power IC development

    Publication Year: 2009, Page(s):35 - 38
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1994 KB) | HTML iconHTML

    RF-LDMOS is the dominant RF power device technology in the infrastructure market from cellular through WiMAX frequencies. High performance, low cost, and excellent reliability are just a few of the factors responsible for this dominant position. Base station suppliers and their customers continue to demand improvements in system efficiency while simultaneously providing lower cost solutions. RF-LD... View full abstract»

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  • Through Silicon Via stress characterization

    Publication Year: 2009, Page(s):39 - 41
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1792 KB) | HTML iconHTML

    In this paper, we will present Micro Raman stress data of Through Silicon Vias (TSV) with different shapes and sizes & spacing, and discuss design considerations. View full abstract»

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  • A 30V complementary bipolar technology for xDSL line drivers

    Publication Year: 2009, Page(s):43 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1891 KB) | HTML iconHTML

    A 30 volt, fully oxide isolated, complementary silicon bipolar technology with pnp cutoff frequencies greater than 3.5 GHz is presented in this paper. The process, developed within a fabless semiconductor company, provides high voltage, high speed analog components suitable for the xDSL line driver market. View full abstract»

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  • Cell Merge: A basic-pre-clustering clustering algorithm for placement

    Publication Year: 2009, Page(s):47 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    In DSM era, digital circuits can contain millions placeable elements, and the complexity and the size of circuits have grown exponentially. For reducing the circuit sizes, clustering algorithm have become popular, so that the placement process can be performed faster and with higher quality. In this paper, we proposed a novel basic-pre-clustering clustering algorithm called Cell Merge which can re... View full abstract»

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  • AKEBONO: A novel quick incremental placer

    Publication Year: 2009, Page(s):51 - 53
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (318 KB) | HTML iconHTML

    In DSM era, the every stages of realistic design flow must interact with physical aspects of the design. For example, improvements in power timing may require replacing many modules with variants that have different shape and connectivity. In this paper, we present AKEBONO - a very quick incremental placement algorithm for performing Engineering Change Order (ECO). AKEBONO consists of two stages: ... View full abstract»

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  • Applications of network coding in global routing

    Publication Year: 2009, Page(s):55 - 58
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (895 KB) | HTML iconHTML

    We study the applications of the network coding technique for interconnect optimization and improving the routability of VLSI designs. Network coding technique generalizes the traditional routing approach by enabling the intermediate nodes to generate new signals by combining the signals received over their incoming wires. This is in contrast to the traditional (routing) approach, in which each in... View full abstract»

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  • Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating

    Publication Year: 2009, Page(s):59 - 62
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    Dual-edge-triggered flip-flop (DETFF) allows us to use half the clock frequency while maintaining the same throughput, thereby cutting the clock power in half. DETFF-based design, however, requires multiple runs of timing analysis, which is critical for short turn-around time; to make it worse, the number of analysis increases if we use clock gating and multiple clock gating logic, both of which a... View full abstract»

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