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IC Design and Technology, 2009. ICICDT '09. IEEE International Conference on

Date 18-20 May 2009

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Displaying Results 1 - 25 of 65
  • [Front cover]

    Page(s): c1
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  • [Title page and copyright notice]

    Page(s): i - ii
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  • Committee members

    Page(s): iii
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  • ICICDT tutorials

    Page(s): iv - vii
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    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • A sub 2W low power IA processor for Mobile Internet Devices in 45nm Hi-K metal gate CMOS

    Page(s): viii
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  • QorIQ P4080 Communications Processor design in 45nm SOI

    Page(s): viii
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  • Plenary & workshop sessions

    Page(s): ix - xii
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    Provides an abstract for each of the plenary presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Table of contents

    Page(s): xiii - xix
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  • Author index

    Page(s): 253 - 254
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  • [Back cover]

    Page(s): c4
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  • Custom design in a low-power/high-performance ASIC world

    Page(s): 1 - 2
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    Aggressive design cycle requirements are making it increasingly difficult to deploy custom and even semi-custom design techniques in consumer ASIC's. However, market requirements continue to push IP implementation teams harder and harder for increased performance and reduced power consumption. Given these two conflicting trends, new design methodologies are required, such that IP design teams can meet market expectations, without the large staffs and long schedules that have traditionally characterized custom design. This presentation reviews several high-ROI methodologies which can be utilized in this design environment to improve implementations without dramatic impact to budgets and schedules. View full abstract»

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  • A low-power and multi-mode design approach for reconfigurable MASH SDM

    Page(s): 3 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (408 KB) |  | HTML iconHTML  

    In this paper, a sixth order multi-stage sigma-delta modulator is designed for GSM/WCDMA/WiMAX communication systems. With the multi-stage noise shaped architecture, the proposed modulator can reconfigure to adapt different system specifications. Meanwhile, the power dissipation is also flexible for power optimization. A prototype is designed with the 0.13-mum 1P8M CMOS technology. The simulation results indicate dynamic ranges of 96/75/66 dB and peak signal to noise plus distortion ratios of 86/73/62 dB for GSM/WCDMA/WiMAX systems. View full abstract»

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  • Implementation and evaluation of fine-grain run-time power gating for a multiplier

    Page(s): 7 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (551 KB) |  | HTML iconHTML  

    In a 32btimes32b multiplier, when the bit width of both operands is less than 16-bit, the upper array of the multiplier computing the upper bits of the product does not need to operate and hence consumes wasteful leakage energy. We propose a technique to control run-time power gating (RTPG) for the upper array by dynamically detecting the operand width. Since RTPG suffers from energy overhead due to turning on/off power switches, the sleep time at each sleep event should be longer than the break-even time (BET) to gain in energy savings. Using an analytical model we built, we show that BET reduces exponentially with higher temperature. Since the chip temperature goes up during the operation, the sleep time becomes more likely to exceed the shortened BET, leading to the increase of energy savings. We evaluated our technique through designing a 32btimes32b multiplier and implementing in a commercial 90 nm CMOS technology. Post-layout simulation results showed that BET reduces from 32 cycles at 25degC to 10 cycles at 65degC and to 3 cycles at 100degC at 100 MHz. We also simulated energy dissipation by incorporating our multiplier into a MIPS R3000 based CPU and running a JPEG encoding program. Results showed that our technique reduces energy by 5% at 65degC and by 39% at 100degC over the PG-disabled case even counting the overhead. In contrast, energy was increased by 36% at 25degC. The ground bounce at the wakeup was effectively suppressed to 91 mV by using delay-skewed buffering for power switches, while achieving the wakeup time of 1.44 ns. View full abstract»

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  • Improvement of LDO's PSRR deteriorated by reducing power consumption : Implementation and experimental results

    Page(s): 11 - 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (564 KB) |  | HTML iconHTML  

    In this work, a Bulk-Gate Controlled Circuit, for improving power supply rejection ratio (PSRR) of a Low Dropout Voltage Regulator (LDO) which deteriorates due to lowering of power consumption is proposed. A test chip was fabricated using 0.18-mum CMOS process. Experimental results of the test chip demonstrate that the proposed circuit provides a high performance of PSRR which is up to 77 dB at 10 Hz, and 64.3 dB at 1 KHz, while the consumption current of the whole LDO which includes currents of all component circuits such as a reference circuit, an over current protection circuit, etc., is reduced to 8.5 muA without load, and 35 muA with full load. Comparing to the basic type of conventional LDOs, PSRR of the proposed bulk-gate controlled LDO achieves an improvement of 16 dB for 10 Hz and 27.8 dB for 1 KHz . View full abstract»

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  • Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1036 KB) |  | HTML iconHTML  

    We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-VTH) operation of highly scaled devices. We find that the sub-VTH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by channel dimension scaling and reducing the gate overdrive into the sub-VTH regime. These large RTN fluctuations greatly impact circuit variability and represent a troubling obstacle that must be solved if sub-VTH operation is to become a viable solution for low-power applications. View full abstract»

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  • Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (949 KB) |  | HTML iconHTML  

    A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit, composed of the SCR device and new ESD detection circuit, has been designed with consideration of gate current to reduce the total standby leakage current under normal circuit operating conditions. After fabrication in a 1-V 65-nm fully-silicided CMOS process, the proposed power-rail ESD clamp circuit can sustain 7 kV human-body-model (HBM) and 325 V machine model (MM) ESD tests which occupying an silicon area of only 49 mum times 21 mum and consuming a very low standby leakage current of 96 nA at room temperature. View full abstract»

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  • ESD protection for RF/AMS ICs: Design and optimization

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (413 KB) |  | HTML iconHTML  

    This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection design optimization and prediction for RF/AMS ICs to ensure 1st Si design success. View full abstract»

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  • A 0.9 V to 5 V mixed-voltage I/O buffer using NMOS clamping technique

    Page(s): 29 - 32
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    A 0.9 V to 5 V (0.9/1.2/1.8/2.5/3.5/5 V) mixed-voltage I/O buffer with NMOS clamping technique is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 3 times VDD voltage level signal without gate-oxide overstress hazard. Besides, the leakage current effect is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to 140/120/120/120/80/40 Mbps for 5/3.3/2.5/1.8/1.2/0.9 V, respectively, with a given capacitive load of 10 pF. View full abstract»

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  • Recent advances in RF-LDMOS high-power IC development

    Page(s): 35 - 38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1994 KB) |  | HTML iconHTML  

    RF-LDMOS is the dominant RF power device technology in the infrastructure market from cellular through WiMAX frequencies. High performance, low cost, and excellent reliability are just a few of the factors responsible for this dominant position. Base station suppliers and their customers continue to demand improvements in system efficiency while simultaneously providing lower cost solutions. RF-LDMOS continues to evolve to meet these demanding requirements. One key evolution that provides improved performance while lowering cost is the introduction of high power RFICs. By combining high Q integrated passives with RF-LDMOS device technology, multi-stage, high-power (>100 W) devices can be realized that offer superior performance and lower cost than the corresponding discrete transistor implementation can provide, with similar if not superior reliability. This paper will review recent RF-LDMOS high-power IC developments. View full abstract»

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  • Through Silicon Via stress characterization

    Page(s): 39 - 41
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    In this paper, we will present Micro Raman stress data of Through Silicon Vias (TSV) with different shapes and sizes & spacing, and discuss design considerations. View full abstract»

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  • A 30V complementary bipolar technology for xDSL line drivers

    Page(s): 43 - 46
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    A 30 volt, fully oxide isolated, complementary silicon bipolar technology with pnp cutoff frequencies greater than 3.5 GHz is presented in this paper. The process, developed within a fabless semiconductor company, provides high voltage, high speed analog components suitable for the xDSL line driver market. View full abstract»

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  • Cell Merge: A basic-pre-clustering clustering algorithm for placement

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (293 KB) |  | HTML iconHTML  

    In DSM era, digital circuits can contain millions placeable elements, and the complexity and the size of circuits have grown exponentially. For reducing the circuit sizes, clustering algorithm have become popular, so that the placement process can be performed faster and with higher quality. In this paper, we proposed a novel basic-pre-clustering clustering algorithm called Cell Merge which can reduce effectively the circuit size. The algorithm has proven a linear-time complexity of O(n), where n is the number of nets in a circuit. The numerical experiments on ISPD02 IBM-MS mixed-size benchmark suite for placement show that by applying Cell Merge as a processing step, the performance of state-of-the-art placer can be further improved. View full abstract»

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  • AKEBONO: A novel quick incremental placer

    Page(s): 51 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    In DSM era, the every stages of realistic design flow must interact with physical aspects of the design. For example, improvements in power timing may require replacing many modules with variants that have different shape and connectivity. In this paper, we present AKEBONO - a very quick incremental placement algorithm for performing Engineering Change Order (ECO). AKEBONO consists of two stages: first is an iterative net-driven standard-cell placement with hierarchical partitioning, second is a legalization to fit rows and to remove overlaps. As a radix-like sort algorithm is applied to AKEBONO, the total time complexity of it is O(n). Experimental results on ISPD04 IBM standard cell benchmark suite [3] show that run time of AKBONO is 30times faster than the state state-of-the-art academic placers Capo 10.5 legalizer with Greedy and RowIroning [4] on average. Though Capo 10.5 legalizer generally increases HPWL by 9.4% while our placer produces an increase of 13.8%, however we will claim that AKEBONO provides evener and practical placement results. View full abstract»

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  • Applications of network coding in global routing

    Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (895 KB) |  | HTML iconHTML  

    We study the applications of the network coding technique for interconnect optimization and improving the routability of VLSI designs. Network coding technique generalizes the traditional routing approach by enabling the intermediate nodes to generate new signals by combining the signals received over their incoming wires. This is in contrast to the traditional (routing) approach, in which each intermediate node can only forward the incoming signals. While the traditional methods of interconnect routing have attracted a large body of research, applications of network coding in VLSI design have received a relatively little interest from the research community. Accordingly, in this paper we focus on establishing efficient coding networks for VLSI designs. The paper makes the following contributions. First, we extend the Hanan theorem for multi-net rectilinear coding networks. Second, we present several heuristic solutions for finding near-optimal coding networks. Finally, we perform an extensive simulation study to evaluate the advantage of network coding over the traditional routing solutions and to identify routing instances where the network coding techniques are expected to be beneficial. Our results show that network coding can help to reduce the required wirelenght, in particular in the congested areas and in the presence of blockages. View full abstract»

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  • Timing analysis of dual-edge-triggered flip-flop based circuits with clock gating

    Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (426 KB) |  | HTML iconHTML  

    Dual-edge-triggered flip-flop (DETFF) allows us to use half the clock frequency while maintaining the same throughput, thereby cutting the clock power in half. DETFF-based design, however, requires multiple runs of timing analysis, which is critical for short turn-around time; to make it worse, the number of analysis increases if we use clock gating and multiple clock gating logic, both of which are typical in practical designs. Alternative approach is to perform analysis once assuming the tightest timing condition, which turns out to be too pessimistic. Timing analysis method for DETFF-based circuit with clock gating is proposed for the first time. The method is based on identifying a cluster of nets that have to be associated with multiple required arrival times (RATs); the remaining nets having a single RAT then can be processed by conventional timing analysis. Experiments with several benchmark circuits in 65-nm technology demonstrate that, at 50% point of cumulative slack histogram, the slack from our analysis was 1.78times on average of the slack from conventional timing analysis assuming the tightest timing condition, and 1.30times at 90% point. View full abstract»

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