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Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Date 24-27 May 2009

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Displaying Results 1 - 25 of 821
  • Author index

    Publication Year: 2009 , Page(s): iv - xliii
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    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2009 , Page(s): ii
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  • [Front cover]

    Publication Year: 2009 , Page(s): c1
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  • Table of contents

    Publication Year: 2009 , Page(s): iii
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    Freely Available from IEEE
  • A fast-lock synchronous multi-phase clock generator based on a time-to-digital converter

    Publication Year: 2009 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (918 KB) |  | HTML iconHTML  

    An all-digital fast-lock synchronous multi-phase clock generator is presented. By using a time-to-digital converter for fast-lock operation and delay measurement, the proposed multi-phase clock generator generates four-phase clocks and synchronizes the reference clock with the output clock within 45 cycles. Furthermore, the clock generator uses a fine binary scheme and de-skewing circuit for fine delay measurement and compensation. The proposed clock generator was designed in a 0.18 mum CMOS technology. It operates over a wide frequency range from 400 MHz to 1.22 GHz and consumes 34 mW at 1.22 GHz. View full abstract»

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  • Low-power clock reference circuit for intermittent operation of subthreshold LSIs

    Publication Year: 2009 , Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1231 KB) |  | HTML iconHTML  

    A low power on-chip reference clock generator consisting of subthreshold MOSFET circuits is proposed. It uses a simple frequency-locked loop technique with no inductor, quartz resonator, or MEMS oscillator. Theoretical analyses and a SPICE simulation with 0.35-mum CMOS parameters showed that the clock frequency could be controlled in the frequency range of 10-1000 kHz. When operated at 170 kHz, the generator showed a temperature coefficient of 100 ppm/degC, a line sensitivity of 3%/V, and a power consumption of 20 muW. Our clock generator can be used as a reference clock for intermittent operation in power aware LSIs. View full abstract»

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  • Hybrid BiST solution for Analog to Digital Converters with low-cost Automatic Test Equipment compatibility

    Publication Year: 2009 , Page(s): 9 - 12
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1262 KB) |  | HTML iconHTML  

    The cost of testing mixed signal circuitry with conventional analog-stimulus is significantly higher than digital circuitry due to higher cost automatic test equipment (ATE) required for generation of analog stimulus. Multiple variants of low cost testers have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hardware cost. Systems containing mixed-signal/RF components can thus not be tested on such ATE due to the cost and limitations of analog/RF stimulus and measurement modules. This paper proposes a hybrid BIST scheme for analog to digital converters (ADCs) to enable full production-quality testing with low cost ATE. The two major challenges addressed are generating the input stimulus, and a fully functional at-speed test to maintain the test quality of a pure analog ATE solution. View full abstract»

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  • Cost effective signal generators for ADC BIST

    Publication Year: 2009 , Page(s): 13 - 16
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (837 KB) |  | HTML iconHTML  

    ADC in SOC usually has no connection to the outside. Built-in self-test is a good way to verify this block's performance. Stringent requirement of stimulus generator is the most important limitation of ADC BIST. Several methods of using stimulus with low linearity to test ADC with high linearity have been reported for standalone production test. These methods can be adapted for ADC BIST to reduce the BIST cost overhead. This paper investigates signal patterns that can be used in low cost BIST scheme. Two cost effective stimulus generator structures are presented. Simulation results shows that the generated signal with less than 7 bits linearity can be used to test a 16 bits ADC. The estimation errors of INL are less than 0.65 LSB. View full abstract»

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  • A low energy two-step successive approximation algorithm for ADC design

    Publication Year: 2009 , Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB) |  | HTML iconHTML  

    This paper presents a new method for switching the capacitors in the DAC capacitor array of a successive approximation register (SAR) ADC. By separating the decoding of the most significant bits and the least significant bits, and using two different capacitor arrays with unequal size to determine their values, respectively, the average switching energy of the capacitor arrays is dramatically reduced compared to the traditional switching methods. Calibration registers are used to reduce the error of the most significant bits conversion due to the usage of a smaller capacitor array. Experiments were carried out on a 10-bit SAR-ADC designed using TSMC 0.18mum CMOS process. HSPICE simulations show that significant reduction in energy consumption is achieved using the proposed design. View full abstract»

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  • A new and efficient approach for high-speed and very compact realization of Secure Hash Algorithm

    Publication Year: 2009 , Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1787 KB) |  | HTML iconHTML  

    We are proposing that the recently proposed cell-FPGA-like hybrid CMOS/nanodevice architecture is an optimum platform to realize encryption algorithms. Such circuits will combine a semiconductor-transistor (CMOS) stack and a two-level nanowire crossbar with nanoscale two-terminal nanodevices (programmable diodes) formed at each crosspoint. The basic modules of the Secure Hash Algorithm (SHA-512) have been designed using this architecture. In addition, using a custom set of design automation tools, quasi-optimum gate placing, routing and rerouting are provided for SHA-512 building blocks. It is shown that such a design results in a circuit which is defect tolerant, much faster and strikingly denser than its CMOS counterpart. View full abstract»

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  • Flexible GF(2m) divider design for cryptographic applications

    Publication Year: 2009 , Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    In cryptographic applications, private key algorithms usually aim at high-throughput data communication, while public key algorithms require much lower throughput for private key exchange and authentication. To increase hardware utilization and reduce area overhead, this paper presents a flexible divider design in GF(2m), which can be configured to operate in either SIMD or SISD mode. When applied to SIMD applications, the divider can perform multiple divisions in parallel and output results per cycle; thus, it is suitable for AES cryptosystems demanding high throughput. In SISD applications, the divider is scalable and can handle different sizes of operand such as those specified in ECC standards. A scalable design can also relax the potential problem of high fanout control signals. Complexity analysis shows the proposed divider, operated in SIMD mode, has lower area complexity and higher throughput in comparison with related work. View full abstract»

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  • An improved publicly detectable watermarking scheme based on scan chain ordering

    Publication Year: 2009 , Page(s): 29 - 32
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (770 KB) |  | HTML iconHTML  

    This paper proposes an improved version of watermarking scheme at the Design-for-testability (DfT) stage for VLSI Intellectual Property (IP) protection. The improved scheme overcomes the weaknesses of previous scan chain watermarking scheme by imposing the extra ordering constraints generated by the IP owner's signature on all scan flip-flops impartially. IP authorship can be publicly authenticated in the field by injecting a given test vector and matching a permuted output response vector against a transformed reference pattern. Both the output response and the reference sequence are related to a pseudorandom sequence generated by a public-key cryptographic algorithm. Experimental results show that the improved method has a low probability of coincidence and low test power overhead. View full abstract»

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  • A low-complexity high-speed QR decomposition implementation for MIMO receivers

    Publication Year: 2009 , Page(s): 33 - 36
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (720 KB) |  | HTML iconHTML  

    QR decomposition (QRD) is an essential signal processing task for many MIMO signal detection schemes. However, decomposition of complex MIMO channel matrices with large dimensions leads to high computational complexity, and hence results in either large core area or low throughput. Moreover, for mobile communication applications that involve fast-varying channels, it is required to perform QR decomposition with low processing latency. In this paper, we propose a hybrid QRD scheme that uses a combination of multi-dimensional Givens rotations, Householder transformations and the conventional two-dimensional (2D) Givens rotations to both reduce the overall computational complexity and achieve higher execution parallelism. To prove the effectiveness of the proposed QRD scheme, a novel pipelined architecture is presented that uses un-rolled pipelined CORDIC processors iteratively to maximize throughput and resource utilization, while minimizing the gate count. The architectures of the main data processing modules, namely the 2D, Householder 3D and 4D/2D configurable pipelined CORDIC processors, are also presented. Synthesis results for a 4times4 MIMO detector in 0.13 mum CMOS process indicate that this QRD design computes a 4times4 complex R matrix and four updated 4times1 complex symbol vectors every 40 cycles, at a clock frequency of 270 MHz and requires 36 K gates. The proposed design achieves the lowest processing time and the highest throughput reported to-date for the same framework. View full abstract»

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  • A robust radio frequency identification system enhanced with spread spectrum technique

    Publication Year: 2009 , Page(s): 37 - 40
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB) |  | HTML iconHTML  

    A robust passive UHF RFID backscatter system enhanced with spread spectrum technique is presented in this paper. Due to the weak signal energy of the backscatter chain, traditional RFID backscatter communication is easily affected by the noises, interferences, and interceptions from the environment. To solve the problem, spread spectrum technique is introduced into the backscatter link of RFID system. Simulated results show that this approach largely reduces the bit error rate and improves the system's reliability and security. For hardware realization, spectrum spreading operation is implemented in a RFID tag baseband processor, which is finally applied into a complete RFID tag and fabricated using 0.18 um 1P6M CMOS technology. Furthermore, de-spreading operation including the PN acquisition is integrated into a FPGA implementation of RFID reader. Thus, a complete robust RFID backscatter system enhanced with spread spectrum technique is constructed. View full abstract»

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  • 1-bit digital tuning of continuous-time filter by the use of unstable sigma-delta modulation

    Publication Year: 2009 , Page(s): 41 - 44
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB) |  | HTML iconHTML  

    A 1-bit digital frequency tuning technique for continuous-time filter is presented. Unstable sigma-delta modulation is used. A 1-bit digital tuning signal can be generated by detecting the stability of a highly unstable sigma-delta modulation loop. Simulations on a third-order and a fourth-order sigma-delta modulation loops show up to 2% tuning accuracy that can be reached with the 1-bit tuning technique. View full abstract»

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  • Tuning elliptic filters with a ‘tuning biquad’

    Publication Year: 2009 , Page(s): 45 - 48
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1196 KB) |  | HTML iconHTML  

    This paper presents an optimum tuning procedure for high-order low-pass (LP) elliptic filters. Since elliptic filters are often used to satisfy very tight specifications, they often need to be tuned accurately. In this paper, we describe the tuning of one biquad, the dasiatuning biquadpsila, in a cascade of biquads. It is shown by Matlab simulations that the best choice for the tuning biquad consists of the pole pair with the highest pole Q (dasiamaximum-Q polespsila) combined with the zero pair with the lowest frequency (dasiaminimum-frequency zerospsila). We also show how standard tuning procedures, such as those for the Tow-Thomas biquad, lead to excellent results. As an example, the tuning procedure is performed on a normalized seventh-order elliptic LP filter. View full abstract»

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  • Capacitive crosscoupling biquad polyphase filter

    Publication Year: 2009 , Page(s): 49 - 52
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    In this paper, the design of biquad polyphase filters with capacitive crosscouplings is presented. Based on the elementary equation s rarr s - jomegac, which describes the frequency shifting, system theoretic modeling is used for design. Some important observations simplifying the design process are denoted. The developed structures have been simulated in Cadence using operational amplifier models with adjustable gain and bandwidth. Results are compared to those of a Tow-Thomas polyphase filter with comparable sum capacitance but with an operational amplifier amount twice as high. By limiting the gain bandwidth product of the models to reasonable values it is shown that operational amplifier performance does not need to be improved and hence a reduced power consumption can be expected. View full abstract»

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  • Compact lowpass ladder filters using tapped coils

    Publication Year: 2009 , Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (629 KB) |  | HTML iconHTML  

    Compact passive LC ladder lowpass filters for pulse shaping are realized using a single inductor with multiple taps. Mutual coupling between different inductors in a ladder results in zeros on the real and imaginary axis and can cause an undershoot in the step response and reduced attenuation in the stopband. Techniques to mitigate these effects are described. A seventh order Bessel filter is realized using the proposed technique in a 0.18 mum CMOS process. This filter exhibits an undershoot of 1.3% and provides a stopband attenuation of 37 dB. It occupies 0.048 mm2, which is at least 15% smaller than a realization with separate spirals for each inductor. View full abstract»

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  • New CMOS fully differential current conveyor and its application in realizing sixth order complex filter

    Publication Year: 2009 , Page(s): 57 - 60
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    A sixth order complex filter based on the usage of a newly proposed fully differential current conveyor (FDCC) is presented in this paper. The FDCC new structure is based on usage of differential difference operational floating amplifier (DDOFA) and floating current source circuits. The block is realized using 0.25 mum CMOS technology under plusmn1.5 V power supply. PSPICE simulation for the FDCC is done for testing the block. The simulation shows that the FDCC has plusmn0.5 V input dynamic range, 95 MHz 3-dB frequency at output terminal under 10 KOmega load and 7.21 mW total power dissipation. The FDCC is used to realize first order complex filter with 1 MHz center frequency and second order complex filter at 500 KHz center frequency. Finally; using cascading technique, a sixth order complex filter at 500 KHz center frequency is proposed. The proposed filter is suitable for applications like Bluetooth receivers. All the proposed filter circuits are simulated using ADS simulator. View full abstract»

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  • Ballistic deflection transistors and the emerging nanoscale era

    Publication Year: 2009 , Page(s): 61 - 64
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (790 KB) |  | HTML iconHTML  

    This paper presents a brief survey of the state of the art in nanoscale electronics, with special emphasis on room-temperature nanoscale ballistic deflection transistors (BDTs) and T-branch junctions (TBJs). Both devices are planar structures etched into a two-dimensional electron gas (2DEG). Extremely low capacitances (~0.2 fF) in the 2DEG system and low switching voltages (~0.15 V) predict THz performance and ultra-low power consumption, making BDTs and TBJs among the most promising and versatile of ballistic nanoelectronic devices. Obstacles in circuit and logic design using the BDT are presented along with potential solutions. I-V characteristics from a fabricated BDT and simulation results from a two-input BDT NAND gate are provided. Future plans to facilitate large-scale integration are discussed. View full abstract»

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  • Fabrication and characterization of emerging nanoscale memory

    Publication Year: 2009 , Page(s): 65 - 68
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1674 KB) |  | HTML iconHTML  

    Conventional solid state memory technologies such as flash memory, DRAM, and SRAM are facing scaling challenges due to fundamental limitations. Therefore, various new memory technologies are being widely researched and evaluated to continue the cost/performance improvement trend of solid state memory devices. To assess the potential scalability of emerging nanoscale memory beyond conventional limits, it is essential to characterize and understand how differently they perform at the nanoscale compared to known properties in the microscale. New nanoscale fabrication methods and new memory technologies offer a great opportunity for future memory device research. In this regard, we evaluated characteristics of nanoscale phase change memory and Ni oxide memory using nanofabrication technologies such as nanowire growth, nanocrystal synthesis, diblock copolymer patterning, and e-beam lithography. Evaluated characteristics include not only their device performance but also key material properties that might affect the ultimate device performance. The nanofabrication method for each memory material is also discussed due to its potential to overcome the difficulties of conventional semiconductor fabrication process. View full abstract»

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  • Graphene devices, interconnect and circuits — challenges and opportunities

    Publication Year: 2009 , Page(s): 69 - 72
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1360 KB) |  | HTML iconHTML  

    Graphene has recently emerged as a serious contender for the post silicon era. Graphene nanoribbon (GNR) devices have similar performance characteristics to carbon nanotube (CNT) ones. However, lithographic patterning methods applied to graphene can avoid the degree of chirality control and alignment issues typical of CNTs, and GNR devices and GNR interconnect can in principle be seamlessly obtained by patterning single graphene sheets, thus leading to monolithically device-interconnect structures. Electrically doped GNR devices in series and in parallel can be used for creating complex GNR FET digital circuits. There are also several important challenges facing the graphene ldquobrave new world,rdquo but many of the difficulties hopefully will have tractable solutions. This paper examines the topic of GNR FET circuit design from a bottom-up theoretical perspective, starting with GNR device and interconnect modeling and simulation, while trying to reconcile theory with some recent experimental results. View full abstract»

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  • Perspectives and issues in 3D-IC from designers' point of view

    Publication Year: 2009 , Page(s): 73 - 76
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    Recent progress of through-silicon-via (TSV) process is so impressive that everyone can expect real 3D-IC era. The most valuable advantages of 3D-IC is decreasing interconnects. Although analysis of this advantages has been reported in some specific case study, the general theory for quantitative analysis has not been studied. In some cases, the advantage of 3D-IC has been overestimated and much different from that of real chip designs expected. This paper presents the qualitative analysis of general 3D-IC design especially for sub-65nm CMOS generation from designers' point of view. What is understood from this paper is how important IC-design is for 3D-IC and how to gain a big advantage of 3D-IC. View full abstract»

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  • Adaptive design for nanometer technology

    Publication Year: 2009 , Page(s): 77 - 80
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1818 KB) |  | HTML iconHTML  

    Rising design uncertainties at advanced process nodes place conflicting demands on todays engineers. The widening safety-margins required to ensure robust designs in the face of such uncertainties lead to conservative designs with unacceptable power and performance overheads. On the other hand, low-power techniques such as dynamic voltage scaling (DVS) and clock-gating adversely affect circuit robustness. In this paper, we will review a number of techniques for adaptive design which mitigate the impact of margins by tuning system parameters (voltage and frequency) according to variations in runtime workload, environmental and process conditions. We will evaluate the margins that each of the different approaches require to guarantee correctness in the worst-case and typical operating point. We also propose a technique called Razor which is an aggressive method for eliminating all safety-margins through in situ error-detection and correction. Error-detection is achieved by a new type of Razor flip-flop that monitors critical path endpoints and flags timing errors upon detecting spurious transitions. Recovery is achieved through replay from a check-pointed state. We show the design of the transition-detecting Razor flip-flop and illustrate how it naturally detects SEU in combinational logic and inside latches. We present a 64 bit processor implementing Razor and show, on an average, 33% energy savings from our measurements on silicon. View full abstract»

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  • Direct design of orthogonal filter banks and wavelets

    Publication Year: 2009 , Page(s): 81 - 84
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (651 KB) |  | HTML iconHTML  

    This paper presents a new method for the design of two-channel conjugate quadrature (CQ) filter banks in which halfband filter and spectrum factorization are not required. Instead, a CQ filter is directly optimized subject to the perfect reconstruction and possibly other constraints (such as number of vanishing moments (VM)). We develop a design strategy in that the solution is approached sequentially with each update confined to within a small vicinity of the current iterate where the problem at hand behaves like a convex one, thus the update can be obtained as a solution of a convex problem. Four design scenarios are considered, namely the least squares designs with or without VM requirement, and equiripple designs with or without VM requirement. The simulation studies demonstrate that the proposed method is reliable to design high-order CQ filters with improved performance. View full abstract»

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