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Embedded Software and Systems, 2009. ICESS '09. International Conference on

Date 25-27 May 2009

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  • [Front cover]

    Page(s): C1
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  • [Title page i]

    Page(s): i
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  • [Title page iii]

    Page(s): iii
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  • [Copyright notice]

    Page(s): iv
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  • Table of contents

    Page(s): v - xii
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  • Preface

    Page(s): xiii
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  • Message from Symposium Co-chairs

    Page(s): xiv
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  • Organizing Committee

    Page(s): xv
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  • Technical Program Committee

    Page(s): xvi - xviii
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  • Reviewers

    Page(s): xix
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  • Keynote: Endurance Barriers and Solutions for Flash Memory

    Page(s): xx
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    Flash memory has penetrated many facets of consumer technology in recent years. Within one decade after its invention, we had witnessed the tremendous growth of the flash market. As flash memory gains its momentum, new challenges also emerge. In this talk, we will address endurance issues in the designs of flash-memory storage/file systems. Challenges on the design methodologies will also be presented. In particular, we will present solutions in wear leveling. Related issues in performance enhancement and disturbing problems will be addressed. Multi-stage programming is a paradigm for writing generic programs that do not pay a runtime overhead. The key underlying technology is program generation. View full abstract»

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  • Keynote: Event Driven Software Quality

    Page(s): xxi
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    Summary form only given. Event-driven programming has found pervasive acceptance, from high-performance servers to embedded systems, as an efficient method for interacting with a complex world. The fastest research Web servers are event- driven, as is the most common operating system for sensor nodes. An event-driven program handles concurrent logical tasks using a cooperative, application-level scheduler. The application developer separates each logical task into event handlers; the scheduler runs multiple handlers in an interleaved fashion. Unfortunately, the loose coupling of the event handlers obscures the program's control flow and makes dependencies hard to express and detect, leading to subtle bugs. As a result, event-driven programs can be difficult to understand, making them hard to debug, maintain, extend, and validate. This talk presents recent approaches to event-driven software quality based on static analysis and testing, along with some open problems. We will discuss progress on how to avoid buffer overflow in TCP servers, stack overflow and missed deadlines in microcontrollers, and rapid battery drain in sensor networks. Our work is part of the Event Driven Software Quality project at UCLA, which is aimed at building the next generation of language and tool support for event-driven programming. View full abstract»

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  • Keynote: Wireless Sensor Network in Industrial Automation

    Page(s): xxii
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    Although reports on actual implementations are rare, and potential applications in the projected areas are still under consideration, the wireless sensor networks are in the deployment stage by the manufacturing industry. The use of wireless links with field devices, such as sensors and actuators, allow for flexible installation and maintenance, mobile operation required in case of mobile robots, and alleviates problems with cabling. A wireless communication system to operate effectively in the industrial/factory floor environment has to guarantee high reliability, low and predictable delay of data transfer (typically, less than 10 ms for real time applications), support for high number of sensor/actuators (typically over 100 in a cell of a few meters radius, in a discrete manufacturing environment), and low power consumption, to mention some. This presentation will give a general overview of some of the most important requirements dictated by industrial automation applications most of wireless sensor networks have to comply with; to mention: availability and reliability, safety, survivability, security, and dependability. Then main characteristics of wireless sensor networks used in industrial automation applications are discussed including network topology and architectures, real-time restrictions, reliability, power consumption, and life-time issues. The presentation introduces four communication protocols used with wireless sensor networks: IEEE 802.15.4/ZigBee, and dedicated solutions to include wireless interface to sensors and actuators (WISA), and two most notable standardization initiatives aiming at wireless sensor networks for industrial applications: WirelessHART and ISA100. Some of the deployment issues and solutions are illustrated by an example of a wireless sensor/actuator network developed by ABB and deployed in a discrete manufacturing environment - in a robotic assembly cell. View full abstract»

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  • Tutorial: Multi-stage Programming for Circuit Generation

    Page(s): xxiii
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    Multi-stage programming is a paradigm for writing generic programs that do not pay a runtime overhead. The key underlying technology is program generation. In addition, languages designed to support this paradigm (such as MetaOCaml) help the programmer avoid many of the difficulties that are traditionally encountered in developing program generators. This tutorial will introduce you to the basics of this paradigm as well as of programming in MetaOCaml. The focus of this particular tutorial will be on using MetaOCaml to generate hardware circuits. View full abstract»

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  • Model-Based Design of Embedded Control Systems by Means of a Synchronous Intermediate Model

    Page(s): 3 - 10
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    Model-based design (MBD) involves designing a model of a control system, simulating and debugging it with dedicated tools, and finally generating automatically code corresponding to this model. In the domain of embedded systems, it offers the huge advantage of avoiding the time-consuming and error-prone final coding phase. The main issue raised by MBD is the faithfulness of the generated code with respect to the initial model, the latter being defined by the simulation semantics. To bridge the gap between the high-level model and the low-level implementation, we use the synchronous programming language Lustre as an intermediate formal model. Concretely, starting from a high-level model specified in the de-facto standard Simulink, we first generate Lustre code along with some structured "glue code", and then we generate embedded real-time code for the Xenomai RTOS. Thanks to Lustre's clean mathematical semantics, we are able to guarantee the faithfulness of the generated multi-tasked real-time code. View full abstract»

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  • Efficient Model-Checking for Real-Time Task Networks

    Page(s): 11 - 18
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    Formal methods play an important role in the development of safety-critical systems. Their well-defined semantics can be employed for automatic formal system verification. Model-checking, a well-established formal verification technique, is however often restricted to an abstract level due to complexity reasons. For example, checking temporal system behavior with respect to hardware architectures and operating systems is often not possible.Real-time scheduling theory on the other hand provides efficient techniques for temporal analysis of real-world systems at architecture level.However, models used in real-time scheduling theory usually lack a semantics that is compatible to those used by formal specifications. This prevents to verify temporal system behavior at the architecture level with the same formal methods.We present an approach that combines a timed automata representation of task networks and efficient scheduling analysis techniques. Based on existing task network formalisms we define a consistent timed automaton model, and a mapping between both formalisms. We prove that the mapping induces behavioral equivalence of the models.We show an application of the approach by verifying task networks against Live Sequence Charts (LSC). View full abstract»

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  • A Formal Model for Component-Based Embedded Software Development

    Page(s): 19 - 23
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    This paper presents a formal model for specification, verification, and composition of component-based embedded software. We describe how components are specified from the syntactical view, functional view, QoS view and synchronization view. The refinement rules for functionality, QoS, and synchronous behavior are defined for the verification purpose. And a lightweight composition method is provided for the purpose of composition. View full abstract»

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  • RAM-Based Reconfigurable Implementation of the MD6 Hash Function

    Page(s): 27 - 31
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    Recent breakthroughs in cryptanalysis of standard hash functions like SHA-1 and MD5 raise the need for alternatives. The MD6 hash function is developed by a team led by Professor Ronald L. Rivest in response to the call for proposals for a SHA-3 cryptographic hash algorithm by the National Institute of Standards and Technology. The hardware performance evaluation of hash chip design mainly includes efficiency and flexibility. In this paper, a RAM-based reconfigurable FPGA implantation of the MD6-224/256/384 /512 hash function is presented. The design achieves a throughput ranges from 118 to 227 Mbps at the maximum frequency of 104 MHz on low-cost Cyclone III device. The implementation of MD6 core functionality uses mainly embedded block RAMs and small resources of logic elements in Altera FPGA, which satisfies the needs of most embedded applications, including wireless communication. The implementation results also show that the MD6 hash function has good reconfigurability. View full abstract»

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  • A Parallel Reconfigurable Architecture for Real-Time Stereo Vision

    Page(s): 32 - 39
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    In this paper, a parallel reconfigurable architecture is proposed for real-time stereo vision computation. The architecture is divided into four components: input port, output port, memory and processor. We use task partition methods to achieve the maximum parallel and full pipeline processing of the algorithm implementation. We also adopt memory management to decrease the latency of memory access time and accelerate the processing speed. Data bandwidth control is employed to reduce the hardware resource consumption while maintaining precision demand of computation. Based on the proposed architecture and design method, we have developed a miniature stereo vision machine (MSVM33) to generate high-resolution dense disparity maps at the video rate for real-time applications. View full abstract»

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  • Automatic Code Generation for Synchronous Reactive Communication

    Page(s): 40 - 47
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    Synchronous reactive models are used in model-based design to define embedded control applications. The advantage of model-based design is that system properties can be verified on the model and applied to its software implementation if the translation of the model into code preserves its semantics. In this paper, we present an automatic code generation framework for the semantics-preserving implementation of communication in multi-rate systems. The proposed solution applies to the widely used MATLABreg and Simulinkreg products. It leverages the target language compiler template language of Real-Time Workshopreg and extends the applicability of available commercial code generators. The overhead in memory of the presented solution is analyzed and compared with other implementations. View full abstract»

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  • A Scheduling Algorithm for Hybrid Distributed Real-Time Systems

    Page(s): 51 - 56
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    Real-time systems that support only a finite set of discrete configurations can be referred to as hybrid systems. However, recent feedback control scheduling (FCS) algorithms for hybrid real-time systems are only applicable to single processor systems. And existing FCS algorithms for distributed systems often assume that the systems have continuous control inputs. This paper proposes a FCS algorithm for hybrid distributed real-time systems, which include both tasks supporting continuous configurations and tasks supporting discrete configurations. The algorithm is based on a mixed integer predictive control approach. The experimental results show that this algorithm can provide real-time performance guarantees efficiently, even in open environments. View full abstract»

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  • Earliest Deadline Scheduling for Continuous Queries over Data Streams

    Page(s): 57 - 64
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    Many stream-based applications have real-time performance requirements for continuous queries over time varying data streams. In order to address this challenge, a real-time continuous query model is presented to process multiple queries with timing constraints. In this model, the execution of one tuple passing through an operator path is modeled as a real-time task instance. A fine-grained scheduling strategy named OP-EDF is proposed for real-time scheduling, which schedules the operator path with the earliest deadline of the waiting tuples at any time slot. The performance of the OP-EDF is analyzed from three aspects: schedulability, response time and system overhead. Furthermore, two improved batch scheduling algorithms, termed OP-EDF-Batch and OP-EDF-Gate, are introduced to decrease system overhead of the OP-EDF. The experiment results show that the proposed continuous query model and improved scheduling algorithms are effective in real-time query processing for data streams with bursty arrival rates. View full abstract»

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  • A Survey of WCET Analysis of Real-Time Operating Systems

    Page(s): 65 - 72
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    Timing correctness of hard real-time systems is guaranteed by schedulability analysis and worst-case execution time (WCET) analysis of programs. Traditional WCET analysis mainly deals with application programs and has achieved success in industry. Timing analysis of application programs along cannot guarantee correctness of complete systems consisting RTOS. WCET tools designed for application program analysis have been applied to analyze RTOS routines by several research groups, but poor WCET estimations have been reported. Timing analysis of real-time systems considering both applications and RTOS has not been fully studied. So we intend to give a survey of related work on WCET analysis of RTOS. By summarizing previous work, challenges of WCET analysis of complete real-time systems are presented, and some possible further research potentials are unleashed. View full abstract»

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  • A Case Study on Controller Synthesis for Data-Intensive Embedded Systems

    Page(s): 75 - 82
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    This paper presents an approach for the safe design of data-intensive embedded systems. A multimedia application module of last generation cellular phones is considered as a case study. The OMG standard profile MARTE is used to adequately model the application. The resulting model is then transformed into a synchronous program from which a controller is synthesized by using a formal technique, in order to enforce the safe behavior of the modeled application while meeting quality of service requirements. The whole study is carried out in a design framework, GASPARD, dedicated to high-performance embedded systems. View full abstract»

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  • Abstract Simulation: A Static Analysis of Simulink Models

    Page(s): 83 - 92
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    Simulink is one of the most widely used industrial tools to design embedded systems. Applying formal methods sooner in the cycle of development is an important industrial challenge in order to reduce the cost of bug fixing. In this article, we introduce a new method, called abstract simulation and based on abstract interpretation of Simulink models. Abstract simulation uses several numerical domains such as a domain for Taylor forms or floating-point numbers with errors. These domains allow us to estimate errors introduced by numerical algorithms and by computations during simulations. As a result, our method makes it possible to validate numerical behaviors of embedded systems modeled in Simulink. A prototype has been implemented and experimental results are commented. View full abstract»

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