Proceedings International Test Conference 1997

1-6 Nov 1997

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Displaying Results 1 - 25 of 138
  • The application of novel failure analysis techniques for advanced multi-layered CMOS devices

    Publication Year: 1997, Page(s):304 - 309
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1392 KB)

    The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection.... View full abstract»

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  • Proceedings International Test Conference 1997

    Publication Year: 1997
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    Freely Available from IEEE
  • Scan encoded test pattern generation for BIST

    Publication Year: 1997, Page(s):548 - 556
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (914 KB)

    This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test ... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):1053 - 1054
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    Freely Available from IEEE
  • Design for primitive delay fault testability

    Publication Year: 1997, Page(s):436 - 445
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (872 KB)

    To guarantee the temporal correctness of a digital circuit a set of multiple path delay faults called primitive faults need to be tested. Primitive faults can contain one or more faulty paths. Existing techniques can identify and test primitive faults containing up to two or three paths. Identifying and testing primitive faults that consist of a larger number of paths is impractical for large desi... View full abstract»

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  • The search for the universal probe card solution

    Publication Year: 1997, Page(s):533 - 538
    Cited by:  Papers (5)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    Epoxy Ring, Cobra, and other new products are evaluated against the demand for high pin count, high frequency, high temperature, multi-DUT, long life, etc. There doesn't appear to be a single universal solution, but rather each technology provides a usable response to the growing wafer test requirements. However, the climate is right for creativity and innovation to meet the challenges of the futu... View full abstract»

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  • IC diagnosis: industry issues

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (108 KB)

    A new failure analysis paradigm is necessary-a shift from hardware-based techniques to software-based methods. The transition is a daunting task because of its complexity. As with other successful practices in microelectronics, including design and testing, it is expected that a suite of software applications will be necessary to thoroughly diagnose complex ICs. These tools should be able to run c... View full abstract»

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  • Logical diagnosis solutions must drive yield improvement

    Publication Year: 1997
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (92 KB)

    The author discusses automated production-worthy solutions for high-volume manufacturing. He suggests that Design for Test (DFT) techniques such as scan (particularly full scan) provide design hooks that enable more effective solutions, while advances in realistic defect behavior modeling and simulation are improving both the accuracy and the ability to localize more difficult defect types. Given ... View full abstract»

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  • A new probe card technology using compliant MicrospringsTM

    Publication Year: 1997, Page(s):527 - 532
    Cited by:  Papers (8)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (940 KB)

    Recent trends in the semiconductor industry such as the widespread use of C4, ever increasing demands for testing more chips in parallel, and faster edge rates, have conspired to present major challenges to currently available probe card technologies. This paper describes a new probe card technology, its characteristics, and how it successfully addresses these challenges View full abstract»

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  • Logic diagnosis-diversion or necessity?

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (100 KB)

    Failure diagnosis is resource intensive, frustrating, and often impossible. However, it is also critical and necessary for aggressive designs and manufacturing processes. Research in this area is making rapid progress, but the challenges are also rapidly growing in magnitude and importance View full abstract»

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  • Design of cache test hardware on the HP PA8500

    Publication Year: 1997, Page(s):286 - 293
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (604 KB)

    There are many difficulties inherent in the testing of large on-chip caches. This paper presents some of these problems and provides motivation for solving them. After the motive has been established, the techniques used to test the PA8500 on-chip caches are described. This is followed by a detailed explanation of the test hardware, and an example of how it is used View full abstract»

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  • IDDQ characterization in submicron CMOS

    Publication Year: 1997, Page(s):136 - 145
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (776 KB)

    The effectiveness of IDDQ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective IDDQ current characterization. The dependence of IDDQ on the channel length spread in scaled down devices is exam... View full abstract»

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  • A simplified polynomial-fitting algorithm for DAC and ADC BIST

    Publication Year: 1997, Page(s):389 - 395
    Cited by:  Papers (77)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (544 KB)

    An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to... View full abstract»

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  • High-performance production test contactors for fine-pitch integrated circuit

    Publication Year: 1997, Page(s):518 - 526
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (804 KB)

    This paper describes the design of two contactors intended for testing fine-pitch BGA devices, specifically 0.75 mm and 0.5 mm pitches. The design emphasis is on high performance and high-volume production. The devices described provide superior electrical performance while being subjected to the rigors of production test. The paper describes the electrical and mechanical requirements of the conta... View full abstract»

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  • A case study of the test development for the 2nd generation ColdFireR microprocessors

    Publication Year: 1997, Page(s):424 - 432
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (920 KB)

    A case study of the development of the design for test methodology of the second generation of the ColdFireR Microprocessor Family is described from the viewpoint of goals, initial strategy and implementation. Methodology includes at-speed scan path design, path delay testing, IDDQ and direct access test modes for embedded memories. Scan tests are applied with timing identica... View full abstract»

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  • Manufacturing pattern development for the Alpha 21164 microprocessor

    Publication Year: 1997, Page(s):278 - 285
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (680 KB)

    Functional test patterns play a key role in the test strategy of many microprocessors. This paper describes the process of creating and fault grading an initial set of functional test vectors. The fault simulation results are used to identify design verification test (DVT) hard faults and to guide additional test development. Moreover, this paper details the effectiveness of test creation heuristi... View full abstract»

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  • Tree-structured linear cellular automata and their applications as PRPGs

    Publication Year: 1997, Page(s):858 - 867
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (808 KB)

    This paper introduces a family of pseudorandom test pattern generators, named tree-structured linear cellular automata (TLCA). The empirical study on the ISCAS'85 benchmark circuits shows the effectiveness of TLCA for testing sequential faults View full abstract»

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  • Experiences with implementation of IDDQ test for identification and automotive products

    Publication Year: 1997, Page(s):127 - 135
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (868 KB)

    Quality improvements for CMOS devices by using IDDQ/I SSQ tests are a popular topic since early 1990s. This is a report about experiences with the implementation of novel IDDQ test methods for Identification & Automotive products at Philips Semiconductors. The aim is to describe the considerations, quality assurance strategy and its realization for Identificati... View full abstract»

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  • Real time in-situ monitoring and characterization of production wafer probing process

    Publication Year: 1997, Page(s):802 - 808
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (468 KB)

    This paper introduces a new technique that enables real-time monitoring and characterization of a production wafer probing process. Using this new technique, probing contact resistance data taken from production wafers has been correlated with wafer yield. Data are presented showing that production wafers are better suited for characterizing probing contact resistance than metalized setup wafers View full abstract»

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  • Dynamic testing of ADCs using wavelet transforms

    Publication Year: 1997, Page(s):379 - 388
    Cited by:  Papers (9)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (668 KB)

    This paper introduces a new method for evaluating non-idealities in ADCs using wavelet transforms. Compared with conventional testing methods, this method can shorten the test time and improve test quality during production testing of ADCs View full abstract»

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  • Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure

    Publication Year: 1997, Page(s):509 - 517
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (676 KB)

    The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture o... View full abstract»

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  • To DFT or not to DFT?

    Publication Year: 1997, Page(s):557 - 566
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (900 KB)

    Despite a substantial amount of prior work in design-for-testability (DFT) cost modeling, the decision whether or not and how to use DFT is still not an easy one. The problem is that the relationship between DFT benefits and costs are still far from being well understood. The objective of this paper is to study the DFT decision-making process and to identify its missing or weak links. The first st... View full abstract»

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  • Next generation PowerPCTM microprocessor test strategy improvements

    Publication Year: 1997, Page(s):414 - 423
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1056 KB)

    The first PowerPC microprocessor in the new G3 generation of designs, the MPC750, incorporates new test strategy approaches to improve the product test quality, reliability, and debug, and to reduce the total time to market View full abstract»

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  • On-line testing scheme for clock's faults

    Publication Year: 1997, Page(s):587 - 596
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (832 KB)

    This paper proposes an on-line testing scheme for permanent and temporary faults which affect signals of the clock distribution network of synchronous systems, and which make them stuck-at, or change with incorrect frequency or duty-cycle. By means of straightforward modifications, the proposed scheme can be also used to detect on-line undesired skews between couples of clock signals View full abstract»

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  • Low cost ATE pin electronics for multigigabit-per-second at-speed test

    Publication Year: 1997, Page(s):94 - 100
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (668 KB)

    This paper describes the design and performance of low-cost electronics modules which can be used for testing multigigabit-per-second digital components and subsystems within an automated test environment. Pattern stimuli are generated at rates up to 2.67 Gbps with timing errors less than 50 ps. Pattern sensitivity is less than 40 ps and RMS jitter is typically about 8 ps. A high-speed differentia... View full abstract»

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