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Proceedings International Test Conference 1997

1-6 Nov 1997

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Displaying Results 1 - 25 of 138
  • The application of novel failure analysis techniques for advanced multi-layered CMOS devices

    Publication Year: 1997, Page(s):304 - 309
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection.... View full abstract»

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  • Proceedings International Test Conference 1997

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (636 KB)
    Freely Available from IEEE
  • Scan encoded test pattern generation for BIST

    Publication Year: 1997, Page(s):548 - 556
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (914 KB)

    This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test ... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):1053 - 1054
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    Freely Available from IEEE
  • Pin margin analysis

    Publication Year: 1997, Page(s):655 - 662
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    A method and tool is described to increase test program standards and lower program maintenance cost through Pin Margin Analysis. Exposure of DUT and ATE characteristics during test program operation will lead to maximizing test margins View full abstract»

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  • Board level automated fault injection for fault coverage and diagnostic efficiency

    Publication Year: 1997, Page(s):649 - 654
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper discusses the value of determining the fault coverage and diagnostic resolution of an at-speed functional test. State-of-the-art electronic card assemblies require testing for correct operation at their rated speed. In many cases, an at-speed functional test serves this purpose. Automated fault injection as a means of determining at-speed functional test fault coverages and diagnostics ... View full abstract»

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  • Analog fault diagnosis for unpowered circuit boards

    Publication Year: 1997, Page(s):640 - 648
    Cited by:  Papers (2)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    We present key portions of a method for automatic analog fault diagnosis for unpowered circuit boards. Our work consists of two major parts: (1) test point selection and (2) stimuli selection for diagnostic test generation. For test point selection, we propose an efficient graph-based algorithm achieving a desired level of diagnosibility. The stimuli selection algorithm uses a cost function derive... View full abstract»

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  • Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure

    Publication Year: 1997, Page(s):509 - 517
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture o... View full abstract»

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  • System level boundary scan in a highly integrated switch

    Publication Year: 1997, Page(s):636 - 639
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    JTAG and continuity testing can only go so far at a board or module testing level. When all of the pieces come together, employing boundary scan (IEEE 1149.1) techniques at a system level can significantly reduce the time it takes to test a large product with literally thousands of interconnections. Although there are many benefits to system level JTAG, there are pitfalls as well. This paper descr... View full abstract»

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  • Parasitic effect removal for analog measurement in P1149.4 environment

    Publication Year: 1997, Page(s):499 - 508
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    An intrinsic response extraction algorithm is derived and implemented to remove the parasitic effects in P1149.4 analog measurement. The methodology is tested on and verified by SPICE simulation results and real measurement data View full abstract»

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  • Weak Write Test Mode: an SRAM cell stability design for test technique

    Publication Year: 1997, Page(s):1043 - 1052
    Cited by:  Papers (23)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Test Mode (WWTM). This technique applies test circuitry which attempts to overwrite the data stored in SRAM cells. It is designed so that only defective cells are overwritren. The resulting test has a shorter test time and ... View full abstract»

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  • H-SCAN+: a practical low-overhead RTL design-for-testability technique for industrial designs

    Publication Year: 1997, Page(s):265 - 274
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    H-SCAN (1996) was presented as a low overhead design-for-testability strategy which is applicable to RT-level controller-data path circuits. However, from the view-point of practical use, there is a possibility that the area overhead of H-SCAN is larger than that of full-scan. Moreover, H-SCAN is unable to handle many features present in actual designs. In this paper, we propose a modified H-SCAN ... View full abstract»

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  • An effective BIST scheme for arithmetic logic units

    Publication Year: 1997, Page(s):868 - 877
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    Multifunction arithmetic logic units (ALUs) that realize complex arithmetic and logic operations (like the operations of the 74×181 family) are widely used in today's complex integrated circuits, such as commercial microprocessors and digital signal processors. These ALUs are built around either ripple-carry (RC) adders, carry-lookahead (CLA) adders or mixed CLA/RC adders depending on area a... View full abstract»

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  • Optical communication channel test using BIST approaches

    Publication Year: 1997, Page(s):626 - 635
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    Novel Built-In Self-Test (BIST) approaches for integrated optoelectronic systems are presented The methods are compatible with scan chain design and allow testing the internal functionality of the device, the interconnection between modules, the analog characteristics of the transmitters and receivers and the Bit Error Rate (BER) of the channels. The proposed approaches enable system evaluation un... View full abstract»

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  • Thoughts on core integration and test

    Publication Year: 1997
    Cited by:  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    A number of initiatives have begun to address the integration and test of core-based chip design. Several organizations, including an IEEE Test Technology Technical Committee (TTTC) and working groups of the Virtual Socket Interface Alliance (VSIA), meet regularly to consider standards and solutions. The most immediate issue that a chip designer must face is the integration of a core (or cores) in... View full abstract»

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  • Design, fabrication and use of mixed-signal IC testability structures

    Publication Year: 1997, Page(s):489 - 498
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    The goals of the studies of the MNABST-1 IC device were as follows: study the technical and economic feasibility of adding P1149.4 structures into mixed-signal devices; elicit design considerations at the silicon level and for silicon design software; study the interoperability of P1149.4 with 1149.1 interconnection test algorithms; study the efficacy of discrete component and network value measur... View full abstract»

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  • BIST-based diagnostics of FPGA logic blocks

    Publication Year: 1997, Page(s):539 - 547
    Cited by:  Papers (54)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance. In this paper we present the first approach able to diagnose faulty programmable logic blocks (PLBs) in Field Programmable Gate Arrays (FPGAs) with maximal diagnostic resolution. Our approach is based on a new Built-In Se... View full abstract»

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  • 1149.5: now it's a standard, so what?

    Publication Year: 1997, Page(s):166 - 173
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    The 1149.5 standard provides an extensible and robust infrastructure for the communication of test and maintenance messages within a system. This infrastructure offers many advantages over other backplane test bus solutions in terms of both its extensibility, and error handling capabilities. Since becoming a standard, 1149.5 has been gaining momentum within the electronic community and has been su... View full abstract»

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  • A low overhead design for testability and test generation technique for core-based systems

    Publication Year: 1997, Page(s):50 - 59
    Cited by:  Papers (29)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagati... View full abstract»

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  • A simulation-based JTAG ATPG optimized for MCMS

    Publication Year: 1997, Page(s):101 - 105
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Boundary scan test generation tools generate tests based on the netlist of the design. Netlist-based tools are very efficient in designs with a high percentage of boundary scan devices, but can be inefficient in designs containing a significant percentage of non-compatible ICs. An alternative method, in which the user defines the nets to test, is explored View full abstract»

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  • Design of cache test hardware on the HP PA8500

    Publication Year: 1997, Page(s):286 - 293
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    There are many difficulties inherent in the testing of large on-chip caches. This paper presents some of these problems and provides motivation for solving them. After the motive has been established, the techniques used to test the PA8500 on-chip caches are described. This is followed by a detailed explanation of the test hardware, and an example of how it is used View full abstract»

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  • Unpowered opens test with X-ray laminography

    Publication Year: 1997
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    It is shown how X-ray laminography can be used to detect solder opens. With this method X-ray images are taken of the device under test (DUT). The lead content in solder makes the solder joints appear clearly in the image. Using image processing algorithms and also calibration information, the captured image of the solder joint is automatically translated into key mechanical measurements of the so... View full abstract»

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  • On-line testing for VLSI

    Publication Year: 1997
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A large variety of on-line testing techniques for VLSI was developed in the past and are still enriched by new developments. They can respond efficiently to the increasing complexity of VLSI circuits under the condition that available CAD tools simplify their implementation. Amongst the advanced online testing techniques are: self-checking design, allowing high quality concurrent checking by means... View full abstract»

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  • Test requirements for embedded core-based systems and IEEE P1500

    Publication Year: 1997, Page(s):191 - 199
    Cited by:  Papers (76)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (968 KB)

    Chips comprising reusable cores, i.e. pre-designed Intellectual Property (IP) blocks, have become an important part of IC-based system design. Using embedded cores enables the design of high-complexity system-chips with densities as high as millions of gates on a single die. The increase in using pre-designed IP cores in system-chips adds to the complexity of test. To test system-chips adequately,... View full abstract»

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  • Analytic models for crosstalk delay and pulse analysis under non-ideal inputs

    Publication Year: 1997, Page(s):809 - 818
    Cited by:  Papers (87)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (820 KB)

    In this paper we develop a general methodology to analyze crosstalk to obtain insight into effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupling between a pair of lines. We first consider the case where crosstalk noise manifests as a pulse and characterize the maximum amplitude, width, energy and timing of this pulse. Closed... View full abstract»

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