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Proceedings International Test Conference 1997

1-6 Nov 1997

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Displaying Results 1 - 25 of 138
  • The application of novel failure analysis techniques for advanced multi-layered CMOS devices

    Publication Year: 1997, Page(s):304 - 309
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    The major focus of this paper is on innovative fault localisation approaches that make use of DFT (design for testability) features, fanin tree, assembly code programming and functional model simulation as FA tools. Besides these, defect localisation techniques and revolutionary backside FA techniques are discussed. All these tools enhance FA activities and increase the chance of defect detection.... View full abstract»

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  • Proceedings International Test Conference 1997

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (636 KB)
    Freely Available from IEEE
  • Scan encoded test pattern generation for BIST

    Publication Year: 1997, Page(s):548 - 556
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (914 KB)

    This paper presents an improved scan-based BIST scheme which achieves very high fault coverage without any modification of the mission logic, i.e. no test point insertion, no test data to store and very simple BIST hardware which does not depend on the size of the circuit. The approach utilizes scan order and its polarity in scan synthesis, effectively converting it into a ROM encoding a few test ... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):1053 - 1054
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    Freely Available from IEEE
  • Current signatures: application

    Publication Year: 1997, Page(s):156 - 165
    Cited by:  Papers (76)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (920 KB)

    Analysis of IC technology trends indicates that Iddq testing may be approaching its limits of applicability. The new concept of the current signature may expand this limit under the condition that an appropriate current-signature-based test methodology is developed. This paper is a first step toward such a goal. It is focused on current signature step detection in a noisy test environment. Applica... View full abstract»

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  • Intrinsic leakage in low power deep submicron CMOS ICs

    Publication Year: 1997, Page(s):146 - 155
    Cited by:  Papers (105)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    The large leakage currents in deep submicron transistors threaten future products and established quality manufacturing techniques. These include the ability to manufacture low power and battery operated products, and the ability to perform IDDQ sensitive measurements with the significant ensuing benefits to test, reliability, and failure analysis. This paper reports transistor intrinsi... View full abstract»

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  • IDDQ characterization in submicron CMOS

    Publication Year: 1997, Page(s):136 - 145
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    The effectiveness of IDDQ testing requires appropriate discriminability of defective and non-defective quiescent currents. Consequently, the interest in characterizing these currents is growing. In this paper we focus our attention on the non-defective IDDQ current characterization. The dependence of IDDQ on the channel length spread in scaled down devices is exam... View full abstract»

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  • Experiences with implementation of IDDQ test for identification and automotive products

    Publication Year: 1997, Page(s):127 - 135
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB)

    Quality improvements for CMOS devices by using IDDQ/I SSQ tests are a popular topic since early 1990s. This is a report about experiences with the implementation of novel IDDQ test methods for Identification & Automotive products at Philips Semiconductors. The aim is to describe the considerations, quality assurance strategy and its realization for Identificati... View full abstract»

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  • Memory test-debugging test vectors without ATE

    Publication Year: 1997, Page(s):663 - 669
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    A method for debugging functional production test vectors for memory devices without the use of Automated Test Equipment (ATE) is presented. The method described involves the use of a digital simulation environment; a reactive Hardware Description Language (HDL) ATE model; and ATE rules checking. The method allows for rapidly debugging vectors and rest program flows without requiring the use of AT... View full abstract»

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  • Analog AC harmonic method for detecting solder opens

    Publication Year: 1997, Page(s):125 - 126
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Vectorless test techniques are attractive methods to quickly and inexpensively identify and diagnose common process related defects on manufacturers printed wiring boards. Junction Xpress is a new AC method developed to locate open and marginal solder connections without the use of digital vectors or overclamp style capacitive probes. Measuring response harmonics rather than simply the fundamental... View full abstract»

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  • Advances in Probe Technology: Best Sessions of the '97 Southwest Test Workshop

    Publication Year: 1997, Page(s): 1030
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    First Page of the Article
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  • Pin margin analysis

    Publication Year: 1997, Page(s):655 - 662
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    A method and tool is described to increase test program standards and lower program maintenance cost through Pin Margin Analysis. Exposure of DUT and ATE characteristics during test program operation will lead to maximizing test margins View full abstract»

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  • HABIST: histogram-based analog built in self test

    Publication Year: 1997, Page(s):760 - 767
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    This histogram based method of test collects a statistical representation of the activity at a node and processes that representation using a template histogram as a reference. In most cases, no special stimulus is required-data is collected in-situ, while the circuit under test is functioning. (Alternatively, analog stimulus, e.g. using a pseudo random sequence generator or stored digital vectors... View full abstract»

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  • Capacitive leadframe testing

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Reliable pin-level diagnosis of open solder joints allows manufacturers to tune SMT process for maximum output. Repair time and repair-induced damage are both significantly reduced with pin-level diagnostics. Detection of misoriented capacitors prevents expensive and reputation-damaging field failures. Ability to test both sides of PCBs allows maximum fault coverage View full abstract»

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  • Board level automated fault injection for fault coverage and diagnostic efficiency

    Publication Year: 1997, Page(s):649 - 654
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper discusses the value of determining the fault coverage and diagnostic resolution of an at-speed functional test. State-of-the-art electronic card assemblies require testing for correct operation at their rated speed. In many cases, an at-speed functional test serves this purpose. Automated fault injection as a means of determining at-speed functional test fault coverages and diagnostics ... View full abstract»

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  • Testability analysis and ATPG on behavioral RT-level VHDL

    Publication Year: 1997, Page(s):753 - 759
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    This paper proposes an environment to address testability analysis and test pattern generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fault model and an ATPG algorithm, is experimentally shown to provide a good estimate of the final gate-level fault coverage, and to give test patterns with excellent fault coverage properties. The approach, being based on a... View full abstract»

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  • Testing the enterprise IBM System/390TM multi processor

    Publication Year: 1997, Page(s):115 - 123
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    This paper describes the test generation strategies, novel test generation techniques and the tester strategy for testing the IBM System/390TM Generation-3 Enterprise System Multi-Processor Module. The paper provides a review of the key test methodologies and a review of actual test results as seen at the product tester View full abstract»

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  • Analog fault diagnosis for unpowered circuit boards

    Publication Year: 1997, Page(s):640 - 648
    Cited by:  Papers (2)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    We present key portions of a method for automatic analog fault diagnosis for unpowered circuit boards. Our work consists of two major parts: (1) test point selection and (2) stimuli selection for diagnostic test generation. For test point selection, we propose an efficient graph-based algorithm achieving a desired level of diagnosibility. The stimuli selection algorithm uses a cost function derive... View full abstract»

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  • A novel functional test generation method for processors using commercial ATPG

    Publication Year: 1997, Page(s):743 - 752
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests for them is becoming a serious problem in industry. This paper describes a novel method for hierarchical functional test generation for processors which targets one embedded module at a time and uses commercial ATPG tools to derive tests for faults within the module. Applying the te... View full abstract»

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  • High-performance production test contactors for fine-pitch integrated circuit

    Publication Year: 1997, Page(s):518 - 526
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    This paper describes the design of two contactors intended for testing fine-pitch BGA devices, specifically 0.75 mm and 0.5 mm pitches. The design emphasis is on high performance and high-volume production. The devices described provide superior electrical performance while being subjected to the rigors of production test. The paper describes the electrical and mechanical requirements of the conta... View full abstract»

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  • Delay testing with clock control: an alternative to enhanced scan

    Publication Year: 1997, Page(s):454 - 462
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Path delay fault testing in non-scan sequential circuits is complicated by the limited state transitions during normal operation. An accepted method for overcoming this difficulty is to use a scan chain consisting of enhanced scan flip-flops which makes the application of arbitrary vector pairs possible. However, the method results in increased path delays because of the enhanced scan flip-flops t... View full abstract»

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  • A low overhead design for testability and test generation technique for core-based systems

    Publication Year: 1997, Page(s):50 - 59
    Cited by:  Papers (29)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagati... View full abstract»

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  • Testing the 400 MHz IBM generation-4 CMOS chip

    Publication Year: 1997, Page(s):106 - 114
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    This paper describes the design-for-test framework of the 400 MHz CMOS central processor (CP) used in the fourth generation (G4) of the IBM S/390(R) line of servers. It will describe details of modeling logic to achieve correct and effective tests as well as describe the test sets required to test all portions of the design. This includes built-in self-test, array self-test, weighted random patter... View full abstract»

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  • Sequential test generation with advanced illegal state search

    Publication Year: 1997, Page(s):733 - 742
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity. P... View full abstract»

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  • Implementation of mixed current/voltage testing using the IEEE P1149.4 infrastructure

    Publication Year: 1997, Page(s):509 - 517
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The development of a mixed-signal test bus infrastructure-IEEE P1149.4-is now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well established standard. This paper presents experiments carried out with a test chip provided by the P1149.4 working group, which explore the architecture o... View full abstract»

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