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Advanced Research in VLSI, 1997. Proceedings., Seventeenth Conference on

Date 15-16 Sept. 1997

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  • Proceedings Seventeenth Conference on Advanced Research in VLSI

    Publication Year: 1997
    Save to Project icon | Request Permissions | PDF file iconPDF (178 KB)  
    Freely Available from IEEE
  • Author index

    Publication Year: 1997 , Page(s): 320
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    Freely Available from IEEE
  • Asynchronous microengines for efficient high-level control

    Publication Year: 1997 , Page(s): 201 - 218
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1220 KB)  

    Asynchronous (self-timed) circuits are quite natural for realizing control-intensive designs. Many such designs are of reactive nature and inherently complex due to complicated communication protocols. In these situations programmable controllers are preferable over hardwired controllers to allow design decisions to be bound late, help connect errors that may slip through the verification process,... View full abstract»

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  • Architectural design of a three dimensional FPGA

    Publication Year: 1997 , Page(s): 256 - 268
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (732 KB)  

    The design and evaluation of a 3-dimensional FPGA architecture called Rothko are described. Rothko takes advantage of a novel 3-dimensional VLSI circuit technology developed at Northeastern University that is based on transferred circuits with interconnections between layers of circuits. The Rothko 3-D FPGA architecture is based on a sea-of-gates FPGA model first proposed in the Triptych architect... View full abstract»

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  • Scalability in computing for today and tomorrow

    Publication Year: 1997 , Page(s): 12 - 29
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (988 KB)  

    Achieving scalability in computer systems without sacrificing usability, requires a synergistic combination of system architecture, fundamental technologies, and implementation. This paper discusses how the Silicon Graphics Origin system utilizes these elements to create a truly scalable microprocessor and makes predictions of how these elements will evolve to provide performance growth into the n... View full abstract»

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  • A VLSI architecture for modeling intersegmental coordination

    Publication Year: 1997 , Page(s): 182 - 200
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1188 KB)  

    A hybrid analog/digital VLSI architecture that models the coordination of neurobiological segmental oscillators is presented. This architecture facilitates the modeling of systems such as those that produce swimming in vertebrates and fish, as well as motivates the creation of a class of biologically inspired, “intelligent” motion-control systems. The two primary components of the arch... View full abstract»

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  • Trends of key advanced device technologies

    Publication Year: 1997 , Page(s): 78 - 81
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (212 KB)  

    Silicon CMOS technology has followed Moore's law over the past two decodes. It is still on the predicted curve, and it appears that the trend will continue into the next decade. The SIA roadmap published by Sematech in 1994 predicted the progress of semiconductor technology fairly well. Expectations based on the SIA roadmap are now being exceeded; for example, as announced by many companies, the p... View full abstract»

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  • Image edge enhancement, dynamic compression and noise suppression using analog circuit processing

    Publication Year: 1997 , Page(s): 114 - 126
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (544 KB)  

    We designed circuits that have potential use as preprocessors of noisy image data, which vary in intensity over as much as four orders of magnitude. The circuits are based on equations representing a stage of the Boundary Contour System/Feature Contour System model. We compared the model performance (equations) using Gaussian and exponential filters with the simulated circuit performance. Our circ... View full abstract»

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  • Interfacing synchronous and asynchronous modules within a high-speed pipeline

    Publication Year: 1997 , Page(s): 47 - 61
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (808 KB)  

    This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits... View full abstract»

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  • Next-generation RF circuits and systems

    Publication Year: 1997 , Page(s): 270 - 282
    Cited by:  Papers (1)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (572 KB)  

    This paper describes developments foreseen to occur in the near future in the RF industry. Applications such as wireless local loops, wireless local area networks, RF identification devices, multi-standard transceivers, and cable modems are considered. The choice of IC technologies and CAD tools is also discussed View full abstract»

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  • Design implementation of intrinsic area array ICs

    Publication Year: 1997 , Page(s): 82 - 93
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1000 KB)  

    Arranging I/O in a matrix array over the core circuitry of an IC generally provides 5-10 times more I/O than the traditional method of restricting pads to the periphery. This approach also minimizes overall die size. This method was pioneered by IBM over thirty years ago and has recently become attractive for new designs requiring several hundred I/O. In this paper we describe the development of a... View full abstract»

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  • Fault scanner for reconfigurable logic

    Publication Year: 1997 , Page(s): 238 - 255
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (912 KB)  

    We propose a technique for online built-in self-test of Field Programmable Gate Arrays (FPGAs). The goal of this system is to detect deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. A system that solves these problems would be useful for mission-critical applications with resour... View full abstract»

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  • Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow-control

    Publication Year: 1997 , Page(s): 127 - 144
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1004 KB)  

    We describe the queue management block of ATLAS I, a single-chip ATM switch (roster) with optional credit-based (backpressure) flow control. ATLAS I is a 4-million-transistor 0.35-micron CMOS chip, currently under development, offering 20 Gbit/s aggregate I/O throughput, sub-microsecond cut-through latency, 256-cell shared buffer containing multiple logical output queues, priorities, multicasting,... View full abstract»

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  • Clock distribution using cooperative ring oscillators

    Publication Year: 1997 , Page(s): 62 - 75
    Cited by:  Papers (12)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (912 KB)  

    This paper presents a new form of integrated ring oscillator, the Cooperative Ring Oscillator (CRO), in which the controllable delay elements are distributed throughout a VLSI chip. Specifically, each stage of the CRO consists of many electrically parallel delay elements that are spatially distributed. The high degree of parallelism in the CRO provides strong signal aggregation that significantly ... View full abstract»

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  • The design of an asynchronous MIPS R3000 microprocessor

    Publication Year: 1997 , Page(s): 164 - 181
    Cited by:  Papers (167)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1032 KB)  

    The design of an asynchronous clone of a MIPS R3000 microprocessor is presented. In 0.6 μm CMOS, we expect performance close to 280 MIPS, for a power consumption of 7 W. The paper describes the structure of a high-performance asynchronous pipeline, in particular precise exceptions, pipelined caches, arithmetic, and registers, and the circuit techniques developed to achieve high throughput View full abstract»

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  • Compact signed-digit adder using multiple-valued logic

    Publication Year: 1997 , Page(s): 96 - 113
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (876 KB)  

    As minimum feature sizes shrink and the number of transistors integrated in a single chip grow, interconnect complexity is one of the most important issues to be solved in future VLSI chips. The use of multivalued logic is one way to effectively solve this problem because multiple-valued signals convey more information than binary signals and thus, require a lower number of interconnecting wires t... View full abstract»

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  • Circuits and microarchitecture for gigahertz VLSI designs

    Publication Year: 1997 , Page(s): 284 - 287
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (192 KB)  

    IBM founded the Austin Research Laboratory to investigate high-performance microprocessor-based systems. Initial efforts have focused on design for high frequency. This resulted in the completion prototype for a 64-bit PowerPC processor core early in 1997. The prototype is expected to run at 800 MHz in 0.25 micron CMOS technology. We discuss clocking strategy, circuit design, microarchitecture, me... View full abstract»

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  • An embedded DRAM for CMOS ASICs

    Publication Year: 1997 , Page(s): 288 - 302
    Cited by:  Papers (5)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (924 KB)  

    The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, will also require more memory than can be supported easily on logic-oriented ASIC processes. Most ASIC memory systems are P-load SRAM, but this circuit technology is neither dense nor power efficient. This paper describes... View full abstract»

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  • A high-speed asynchronous decompression circuit for embedded processors

    Publication Year: 1997 , Page(s): 219 - 236
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1064 KB)  

    This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs are stored in compressed form, and decompressed at runtime during instruction cache refill. The decompression engine uses a unique asynchronous variable decompression rate architecture to process Huffman-encoded instruct... View full abstract»

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  • Signal delay in coupled, distributed RC lines in the presence of temporal proximity

    Publication Year: 1997 , Page(s): 32 - 46
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (700 KB)  

    With improvements in technology, accurate delay modeling of interconnects is becoming increasingly important. Due to decreasing feature sizes, the spacing between the signal lines is also decreasing. Consequently, the switching activities on the neighboring lines can have a significant impact on the delay of the line of interest, and can no longer be ignored. Accurate modeling of this phenomenon, ... View full abstract»

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  • Kestrel: design of an 8-bit SIMD parallel processor

    Publication Year: 1997 , Page(s): 145 - 162
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1284 KB)  

    Kestrel is a high-performance programmable parallel co-processor. Its design is the result of examination and reexamination of algorithmic, architectural, packaging, and silicon design issues, and the interrelations between them. The final system features a linear array of 8-bit processing elements, each with local memory, an arithmetic logic unit (ALU), a multiplier, and other functional units. S... View full abstract»

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  • Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology]

    Publication Year: 1997 , Page(s): 2 - 11
    Cited by:  Papers (14)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (468 KB)  

    Since the introduction of the first ALPHA microprocessor in 1992, Digital has maintained leadership in absolute CPU performance. During the past year, Digital's StrongARM processor has also achieved a leadership position as the fastest CPU capable of operating from a single AA battery cell. Some of the key techniques used to achieve this performance are described in this invited paper View full abstract»

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  • The hierarchical multi-bank DRAM: a high-performance architecture for memory integrated with processors

    Publication Year: 1997 , Page(s): 303 - 319
    Cited by:  Papers (8)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1100 KB)  

    A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However a high performance microprocessor will typically send more accesses than the DRAM can handle due to the long cycle time of the embedded DRAM, especially in applications with significant memory requirements. A multi-bank DRA... View full abstract»

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