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Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1994. Technical Digest 1994., 16th Annual

Date 16-19 Oct. 1994

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Displaying Results 1 - 25 of 80
  • Proceedings of 1994 IEEE GaAs IC Symposium [Front Cover]

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    Freely Available from IEEE
  • Author index

    Page(s): xiv - xv
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    Freely Available from IEEE
  • MMIC's for space-borne systems: status and prospects

    Page(s): 3 - 6
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    Fifteen years after their first demonstration, MMIC's are now rapidly conquering the world of space electronics. The driving forces behind MMIC development have been miniaturization, cost reduction and higher reliability. MMIC's have first been introduced into GEO Telecommunication satellites with a new generation of compact channel amplifier (CAMP). Receiver and solid state power amplifiers (SSPA) are following. After the first convincing demonstrations, MMIC's have now become an absolute necessity for turning into reality future satellites with active antennas, observation radars or future systems such as LEO constellations. View full abstract»

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  • Gigabit networking technologies and beyond

    Page(s): 7 - 8
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    Gives a survey of the ongoing gigabit testbeds in the U.S. and other countries. This is followed by a review of the recent progress in SONET- and ATM-based gigabit networking technologies, and a projection of the technology trends in the near future. The author also discusses the potential opportunities and challenges of migrating the ongoing experimental gigabit testbeds to an ubiquitous and highly reliable National Information Infrastructure. View full abstract»

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  • Progress in quantum functional devices to overcome barriers to ULSI scaling

    Page(s): 9 - 12
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    Barriers to traditional scaling in silicon technology, primarily gate tunneling leakage current and drain-induced barrier lowering, will begin to emerge with the 1 Gb DRAM. Further scaling will involve performance fall-offs as critical dimensions are relaxed in order to reduce leakage currents. Compound semiconductor HFETs will suffer similar scaling penalties. Thin film SOI can extend silicon scaling by two or three generations. However, by the year 2000, a new technology will be necessary to continue the performance trend. That technology will likely utilize quantum effects to increase the functionality of individual electronic devices. The barriers to scaling MOSFETs and HFETs as well as examples of worldwide progress in developing quantum-based technology for future ULSI applications operating at room temperature are discussed. View full abstract»

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  • Advanced III-V materials processing in the vacuum of space

    Page(s): 13 - 16
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    GaAs films, both silicon doped and undoped, have been deposited by Molecular Beam Epitaxy (MBE) in Low Earth Orbit (LEO) in an ultra vacuum environment created by the Wake Shield Facility (WSF). The WSF is a 12 foot diameter stainless steel disk that sweeps out a volume of space thus creating an ultra vacuum in its wake. It was developed specifically to take advantage of the ultra vacuum for the deposition of thin film materials. The WSF was flown for the first time on STS-60 in February, 1994. The mission objectives were to measure the unique wake vacuum environment formed by the Wake Shield, and to epitaxially deposit GaAs thin films. In this paper we describe the films deposited and report on the characterization performed to date. Films were deposited in two basic structures. The first structure consisted of undoped GaAs films of thicknesses ranging from 2 to 4 /spl mu/m with a thin (/spl ap/200 mn) highly silicon doped layer (n/spl ap/5/spl times/10/sup 17//cc) on top. This is basically a metal-semiconductor field effect transistor (MESFET) structure. The second structure was a lightly silicon doped GaAs film (n/spl ap/5/spl times/10/sup 15//cc). We have obtained Photoluminescence (PL), Secondary Ion Mass Spectrometry (SIMS) and X-Ray diffraction data on selected films. The data indicate nominal quality single crystal films with oxygen and carbon contamination. The source of the contamination and further characterization are discussed. View full abstract»

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  • GaAs performance in Si technology: SiGe HBTs for mixed analog-digital applications

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    Summary form only given. Reviews the short but successful history of SiGe HBTs, from the first functionality demonstration in 1987 to the performance of a 1 GHz, 12-bit DAC in 1993. Availability of 60 GHz Fmax bipolar devices in a fully integrated 0.5/0.25 um BiCMOS process, allows high performance mixed signal applications to be implemented in Si technology, achieving unmatched performance and functionality. The intrinsic performance of SiGe transistors has been extended to 115 GHz fT with an Early voltage of 110 V, demonstrating the potential for microwave analog applications. View full abstract»

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  • MMIC phase locked L-S band oscillators

    Page(s): 27 - 29
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    We describe the design and measured performance of GaAs MMIC phase-locked oscillators (PLOs) operating concurrently at 1.353 GHz and 2.030 GHz. All the active components, including reference oscillator, phase/frequency comparators, charge pumps, voltage controlled oscillators (VCOs) and frequency dividers, are integrated on GaAs MMICs. The packaged MMICs are attached to a duroid mother board along with a small number of discrete components, resulting in a rugged dual PLO subassembly. Single sideband phase noise at 1 kHz offset is -87 dBc/Hz and -84 dBc/Hz, respectively. Phase lock is maintained over wide variations of temperature and power supply voltage. View full abstract»

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  • A V-band AlGaAs/InGaAs heterojunction FET MMIC dielectric resonator oscillator

    Page(s): 30 - 33
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    This paper reports a high performance V-band MMIC dielectric resonator oscillator (DRO). The DRO utilizing a 0.15 /spl mu/m gate AlGaAs/InGaAs heterojunction FET has exhibited stabilized oscillation with low phase noise of -88 dBc/Hz at 100 kHz off-carrier and the output power of 3.7 dBm at 55.135 GHz. The oscillation frequency stability of -1.9 ppm//spl deg/C was obtained with a dielectric resonator of +3.3 ppm//spl deg/C temperature coefficient. View full abstract»

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  • An 800 MHz monolithic GaAs HBT serrodyne modulator

    Page(s): 34 - 37
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    An 800 MHz monolithic mixed-signal serrodyne modulator IC has been developed in GaAs/AlGaAs HBT HI/sup 2/L process optimized for digital applications. This 3/spl times/2.8 mm, 2000+ transistor chip consists of a 7-bit phase accumulator driving a vector modulator, implemented as of a pair of balanced mixers, 5-bit switched-attenuators, buffer amplifiers, and control circuits. The balanced mixer's LO leakage and 3-1 products are typically 25 dB below the carrier at the nominal operating point, with all other spurs better than -50 dBc. Over a 32 dB control range, the 5-bit switched attenuator typically achieves worst-case amplitude and phase errors of 1.5 dB and 1.5/spl deg/, respectively, from 50 to 250 MHz. This first generation chip consumes 2.5 W of dc power and clocks to speeds in excess of 925 MHz. View full abstract»

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  • MMIC gyrator bandstop filter with ultra-wideband tuning

    Page(s): 38 - 40
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    This paper describes the first monolithic microwave integrated circuit bandstop filter using an inverted gyrator design. Operating up to 3 GHz it also represents the highest reported frequency application of a gyrator filter design. New active bias configurations were developed to achieve a stable gyrator response and assessment of the filters' tuning speed and control voltage requirements has shown its suitability for digital control in applications requiring frequency agility. The individual MMICs are capable of tuning a 3%, -30 dB attenuation bandwidth, over greater than an octave, and a series combination of two MMICs have a tuneable stopband from 0.7 to 3.3 GHz. View full abstract»

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  • Active, self-adjusting L-S band MMIC filters

    Page(s): 41 - 44
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    We describe the design and measured performance of active, tunable GaAs MMIC band-pass filters and matched closed-loop MMIC control circuits, both fabricated using a standard 1 /spl mu/m foundry process. Separate, 3-section filter circuits covered the 1.34-2.2 GHz and 1.84-2.7 GHz bands, with -3 dB bandwidths of 91/spl plusmn/7 MHz and 123/spl plusmn/12 MHz, respectively, and mean pass-band insertion losses of 0 dB at each tuning frequency. The control circuits generate filter tuning and Q-control bias voltages by tracking a sub-harmonic reference signal. This circuit automatically maintains the filter insertion loss to within /spl plusmn/0.5 dB over more than a 1.3:1 frequency-tuning range, and regulates the center-frequency and insertion loss to within better than /spl plusmn/1.2 MHz and /spl plusmn/0.3 dB over a temperature range of -50/spl deg/C to +75/spl deg/C. View full abstract»

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  • A GaAs BiFET LSI technology

    Page(s): 47 - 50
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    A GaAs BiFET LSI technology has been successfully developed for low power, mixed mode communication circuit applications. The direct placement of the FET on the HBT emitter cap layer simplifies the device epitaxial growth and process integration. High integration levels and functional circuit yield have been achieved. Excellent HBT and FET characteristics have been produced with the noise figure of the FETs comparable to those of traditional MESFETs, enabling them to perform well in front end receiver applications. Through this technology, several LSI circuits, including 32-bit by 2-bit shift registers and a single-chip DRFM have been successfully demonstrated. View full abstract»

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  • An ultra low power AlGaAs/InGaAs HJFET SCFL circuit for 10 Gbps applications with 1.3 V supply voltage

    Page(s): 51 - 54
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    SCFL D-FFs with supply voltage as low as 1.3 V are designed and fabricated. The supply voltage is decreased by optimizing the logic swing and the voltage shift in the source followers. The D-FFs, using 0.25 /spl mu/m AlGaAs/InGaAs HJFETs, operate at up to 10 Gbps, with power consumption as low as 19 mW. View full abstract»

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  • 0.9 V DSP blocks: a 15 ns 4 K SRAM and a 45 ns 16-bit multiply/accumulator

    Page(s): 55 - 58
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    4 K SRAM and 16 bit multiply/accumulate DSP blocks have been designed and fabricated in Complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0 /spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, total power is 0.36 mW. The CGaAs multiplier uses a 16-bit modified Booth architecture with a 3-way 40-bit accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, total current is less than 0.4 mA. View full abstract»

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  • Complementary GaAs junction-gated heterostructure field effect transistor technology

    Page(s): 59 - 62
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    The first circuit results for a new GaAs complementary logic technology are presented. The technology allows for independently optimizable p- and nchannel transistors with junction gates. Excellent loaded gate delays of 179 ps at 1.2 V and 319 ps at 0.8 V have been demonstrated at low power supply voltages. A power-delay product of 8.9 fJ was obtained at 0.8 V. View full abstract»

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  • 2.5 Gb/s 8/spl times/8 self-routing switch GaAs LSIs for ATM switching systems

    Page(s): 63 - 66
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    2.5 Gb/s 8/spl times/8 self-routing switch LSIs have been developed for the asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. This switching system consists of three LSIs using a 0.5 /spl mu/m gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells, a "NEMAWASHI" network LSI for previously detecting the cells with the same output port address, and a demultiplexer LSI for converting the cells from the switching network into the eight streams per a channel. These LSIs are mounted in a 520 pin multi-chip module package. The number of total logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and the throughput is 20.8 Gb/s. View full abstract»

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  • A variable-voltage bidirectional I/O pad for digital GaAs applications

    Page(s): 67 - 70
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    A bidirectional I/O pad for digital GaAs applications has been designed, fabricated, and tested using Vitesse Semiconductor process technology. The I/O pad is designed to operate at frequencies up to 500 MHz and at GTL, ECL, or Rambus voltage levels. The I/O pads can be calibrated to these voltage levels either manually using external signals or internally using on-chip digital calibration logic. View full abstract»

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  • Power rail logic: a low power logic style for digital GaAs circuits

    Page(s): 71 - 74
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    This paper describes a new logic style called Power Rail Logic (PRL) which is compatible with DCFL circuits. Multiplexors, latches, flip-flops and exclusive-OR gates can be built using this logic style. Compared to DCFL, PRL uses fewer transistors, has larger noise margins, and up to 40% lower power-delay products. A test chip containing 32-bit barrel shifters designed in DCFL and in PRL, were successfully fabricated and tested. Test results are given for both circuits. View full abstract»

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  • Developments in transport telematics in Europe. The case of automatic debiting at speed

    Page(s): 81 - 83
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    Transport in the UK and most other European countries, during the latter half of this century, has been dominated by the growth of private car ownership. All the attendant problems of congestion, pollution and accidents are conspiring to undermine the huge personal and social benefits that individuals and households derive from car ownership and use. Nor has this process run its full course; the UK Department of Transport in its National Road Traffic Forecasts (NRTF) foresee the possibility of the total annual vehicle-kms more than doubling between now and the year 2030, before some kind of "saturation" in car-use might be reached. The extent to which these forecasts are reflecting the powerful economic forces that determine future traffic demand or are themselves driven by current transport policy is the subject of much debate. More radical policies, such as tolling inter-urban motorways, congestion-pricing and traffic-calming in urban areas and encouraging the spread of tele-commuting could modify and reshape future travel-demands substantially, with significant implications for daily life. Throughout this transport "informatics" revolution, the Transport Operations Research Group (TORG) at the University of Newcastle upon Tyne has played a leading role. In particular, TORG has acted as the prime contractor in a 16-partner European project called ADEPT (Automatic Debiting and Electronic Payment for Transport), financed by the EC DRIVE programme. This is described and plans for future research outlined. View full abstract»

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  • W-band monolithic single sideband transceiver for automotive radar applications

    Page(s): 84 - 87
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    This paper reports the first W-band monolithic single sideband FMCW transceiver with direct digital synthesizer modulation. This heterodyne transceiver improves the system sensitivity over the previously reported homodyne approach. The complete transceiver has better than 12-dB suppression of the image sideband with a nominal LO drive of 9 dBm and is estimated to exhibit a 11-dB noise figure for IF as low as 1 MHz. This MMIC chip was fabricated using TRW production line process and is suitable for automotive radar applications. View full abstract»

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  • 60-GHz HEMT-based MMIC receiver with on-chip LO

    Page(s): 88 - 91
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    Using InGaP-InGaAs-GaAs technology, we designed, fabricated, and evaluated a 60-GHz fully integrated HEMT-based MMIC receiver. The receiver consists of a four-stage low-noise amplifier (LNA) and a single-balanced active-gate mixer, a 60 GHz local oscillator (LO), and a buffer amplifier for the LO. The HEMTs in the receiver have gates 0.1 /spl mu/m long and 100 /spl mu/m wide. The receiver had a conversion gain of greater than 17 dB from 60.2 GHz to 62.3 GHz, and the maximum conversion gain was 20 dB at 62.2 GHz. The noise figure of the receiver was less than 6 db for IF frequencies between 100 MHz and 1 GHz for a 61.536 GHz LO, and the minimum noise figure was 49 dB at 1 GHz IF. View full abstract»

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  • A novel W-band monolithic push-pull power amplifier

    Page(s): 92 - 95
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    A monolithic W-band push-pull two-stage power amplifier has been developed using 0.1 pm AlGaAs-InGaAs-GaAs pseudomorphic T-gate power HEMT technology. This novel design utilizes the push-pull scheme to take the advantage of a virtual ground in a push-pull HEMT device pair which eliminates the via hole inductance, and improves the power amplifier performance at millimeter-wave frequency. The measurement results show that a small signal gain of 12 dB, an output power of 19.4 dBm, and a power added efficiency of 13.3% have been achieved at 90 GHz, and presents state-of-the-art performance for a monolithic power amplifiers at this frequency. To our knowledge, this is the first reported monolithic push-pull amplifier at millimeter-wave frequencies. View full abstract»

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  • A 16-dB DC-to-50-GHz InAlAs/InGaAs HEMT distributed baseband amplifier using a new loss compensation technique

    Page(s): 96 - 99
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    This paper reports an InAlAs/InGaAs HEMT distributed baseband amplifier IC using a new loss compensation technique for the drain artificial line. The amplifier has a gain of 16 dB with a DC-to-47-GHz bandwidth. The Gain BandWidth Product (GBWF) is about 300 GHz, which is the highest among all reported single-stage distributed amplifier ICs. It also has a flat gain from DC and operates as a baseband amplifier without any off-chip components. View full abstract»

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  • A monolithic broadband 10-50 GHz distributed HEMT mixer including active LO-RF combiner

    Page(s): 100 - 103
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    A millimeter-wave GaAs HEMT MMIC distributed mixer covering the RF frequency range from 10 to 50 GHz with IF frequencies from several MHz to 5 GHz was developed. The active devices are AlGaAs-GaAs HEMTs with a gatelength of 0.2 /spl mu/m and a gatewidth of 2/spl times/25 /spl mu/m. The conversion gain of the mixer is better than -3 dB over the frequency range at an LO power of less than 5 dBm without IF amplification. The RF and the LO signals are fed through an active distributed combiner with 2 dB gain and LO to RF port isolation of 20 dB. The size of the single mixer is 1.5/spl times/1 mm/sup 2/ and of the combiner including bias networks is 2/spl times/1 mm/sup 2/. An integrated broadband mixer chip including the LO and RF combiner was fabricated with a size of 4/spl times/1 mm/sup 2/. View full abstract»

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