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2009 15th IEEE Symposium on Asynchronous Circuits and Systems

17-20 May 2009

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  • [Front cover]

    Publication Year: 2009, Page(s): C1
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  • [Title page i]

    Publication Year: 2009, Page(s): i
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  • [Title page iii]

    Publication Year: 2009, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - vi
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  • Message from Chairs

    Publication Year: 2009, Page(s):vii - viii
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  • Organizing Committee

    Publication Year: 2009, Page(s): ix
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  • Technical Program Committee

    Publication Year: 2009, Page(s): x
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  • Keynote speakers

    Publication Year: 2009, Page(s): xi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (60 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Programmable/Stoppable Oscillator Based on Self-Timed Rings

    Publication Year: 2009, Page(s):3 - 12
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    In this paper a Programmable/Stoppable oscillator is designed based on a Self-Timed Ring. A new model is proposed to calculate the oscillation frequency of the ring. Different solutions for introducing programmability to self timed rings are designed and implemented. Using different techniques, the implemented oscillator achieves a frequency range of 3 GHz down to 400 MHz with a smallest step of 1... View full abstract»

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  • Design and Implementation of a GALS Adapter for ANoC Based Architectures

    Publication Year: 2009, Page(s):13 - 22
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB) | HTML iconHTML

    As Globally Asynchronous Locally Synchronous (GALS) systems are becoming preponderant in complex SoC and NoC, we present the design and implementation of a new GALS adapter to be used in ANoC, an asynchronous NoC architecture. The proposed GALS adapter is a complete IP integration module, including a new FIFO based design using a Johnson-encoding principle for timing domains interfacing, and a loc... View full abstract»

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  • A Programmable Adaptive Router for a GALS Parallel System

    Publication Year: 2009, Page(s):23 - 31
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    This paper describes a router which is the key component of a scalable asynchronous on-chip and inter-chip communication infrastructure for an application-specific parallel computing system. We use this system as a universal platform for real time simulations of large-scale neural networks. The communications router supports multiple routing algorithms, and is pipelined to boost its throughput. Th... View full abstract»

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  • Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links

    Publication Year: 2009, Page(s):35 - 44
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (417 KB) | HTML iconHTML

    To the casual observer, glitches occurring in quasi delay-insensitive logic would appear to cause incorrect operation and render the circuits unusable. This paper presents an informal analysis of the effects of glitches occurring on the long interconnect wires connecting logical units of a network-on-chip (NoC) using quasi delay-insensitive (QDI) techniques. This is followed by the introduction an... View full abstract»

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  • The Lackey Self-Timed Switch-Fabric Design Framework

    Publication Year: 2009, Page(s):45 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (321 KB) | HTML iconHTML

    This paper demonstrates how to rapidly build useful, and high performance self-timed or elastic communication networks. The networks are elegantly extensible to include an arbitrary number of Producers and Consumers. Each switch within the network is built from multiple instances of a Latch Control Element (LaCkEy). The Lackey is a general circuit for self-timed data control. It is built once and ... View full abstract»

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  • A Delay-Insensitive Address-Event Link

    Publication Year: 2009, Page(s):55 - 62
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1039 KB) | HTML iconHTML

    We present a delay-insensitive (DI) link that provides virtual point-to-point channels between ports at corresponding locations in two-dimensional arrays on separate chips. A communication, or event, on any particular channel is represented by its input port's address, which the link encodes, conveys, and decodes. Previous work cut pad-count by transmitting row and column addresses sequentially, a... View full abstract»

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  • A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits

    Publication Year: 2009, Page(s):65 - 76
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    This paper presents a proof that the adversary path timing assumption is both necessary and sufficient for correct SI circuit operation. This assumption requires that the delay of a wire on one branch of a fork be less than the delay through a gate sequence beginning at another branch in the same fork. Both the definition of the timing assumption and the proof build on a general, formal notion of ... View full abstract»

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  • Fault Tolerant Delay Insensitive Inter-chip Communication

    Publication Year: 2009, Page(s):77 - 84
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (370 KB) | HTML iconHTML

    Asynchronous interconnect is a promising technology for communication systems. Delay Insensitive (DI) interconnect eliminates relative timing assumptions, offering a robust and flexible approach to on- and inter-chip communication. In the SpiNNaker system - a massively parallel computation platform -a DI system-wide communication infrastructure is employed which uses a 4-phase 3-of-6 code for on-c... View full abstract»

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  • GHz Asynchronous SRAM in 65nm

    Publication Year: 2009, Page(s):85 - 94
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3630 KB) | HTML iconHTML

    This paper details the design of > 1 GHz pipelined asynchronous SRAMs in TSMC's 65 nm GP process. We show how targeted timing assumptions improve an otherwise quasi delay-insensitive (QDI) design. The speed, area, and power of our SRAMs are compared to commercially available synchronous SRAMs in the same technology. We also present novel techniques for implementing large pseudo dual-ported memo... View full abstract»

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  • Synthesis of Multiple Rail Phase Encoding Circuits

    Publication Year: 2009, Page(s):95 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (973 KB) | HTML iconHTML

    Multiple rail phase encoding communication protocol has several unexploited advantages over traditional encodings. The main impediment to its use is the absence of practical and scalable implementations of controllers for phase encoded data transmission.The paper shows that phase encoding controllers belong to a wide class of circuits which convert combinatorial codes to partial orders of events a... View full abstract»

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  • Modular Approach to Multi-resource Arbiter Design

    Publication Year: 2009, Page(s):107 - 116
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (635 KB) | HTML iconHTML

    When circuits need to be constructed out of several self timed parts that access shared resources, asynchronous arbitration is often required. We consider the creation of the general purpose arbiter delegating M resources to N clients for the cases when the resources can be either active or passive participants of the arbitration. Firstly, the problem is solved for the case of two active resources... View full abstract»

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  • Synchronizer Behavior and Analysis

    Publication Year: 2009, Page(s):117 - 126
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB) | HTML iconHTML

    Synchronizer characterization is non-trivial. The exponential response to parameter changes makes this task a challenge, which is further hampered by numerical instability and precision limitations of circuit simulators. The analysis of multi-stage synchronizers is extremely difficult due to the compounding of these exponential factors. We present results and discoveries from analyzing a variety o... View full abstract»

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  • On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme

    Publication Year: 2009, Page(s):127 - 136
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (371 KB) | HTML iconHTML

    Due to their handshake-based flow control, asynchronous circuits generally do not suffer from metastability issues as much as synchronous circuits do. We will show, however, that fault effects like single-event transients can force (sequential) asynchronous building blocks such as Muller C-Elements into a metastable state. At the example of a fault-tolerant clock generation scheme, we will illustr... View full abstract»

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  • Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

    Publication Year: 2009, Page(s):139 - 150
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB) | HTML iconHTML

    Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. This paper presents a novel method for synthesising indicating implementations of arbitrary encoded function blocks. The synthesis method reduces the cost of the implementations by distributing indication between the individual outpu... View full abstract»

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  • Characterization of Asynchronous Templates for Integration into Clocked CAD Flows

    Publication Year: 2009, Page(s):151 - 161
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (291 KB) | HTML iconHTML

    Asynchronous circuit design can result in substantial benefits of reduced power, improved performance, and high modularity. However,asynchronous design styles are largely incompatible with clocked CAD,which has prevented wide-scale adoption. The key incompatibility istiming. Thus most commercial work relies on custom CAD or untimeddelay-insensitive design methodologies. This paper proposes a newme... View full abstract»

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  • Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines

    Publication Year: 2009, Page(s):162 - 172
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (575 KB) | HTML iconHTML

    We present a heuristic based approach towards analyzing and optimizing the throughput of asynchronous pipelined circuits. Optimization allows specification of the target throughput. A variety of handshaking protocols and implementations are supported through a library approach.Timing arcs specified for library cells serve as a basis for throughput analysis. The algorithms described in the paper ar... View full abstract»

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