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1990 IEEE SOS/SOI Technology Conference. Proceedings

2-4 Oct. 1990

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Displaying Results 1 - 25 of 81
  • Modelling of breakdown voltage in sub-micron SOI transistors

    Publication Year: 1990, Page(s):17 - 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (134 KB)

    Model validation for submicron SIMOX (separation by implantation of oxygen) transistors by careful comparison of the simulated and measured snapback voltages as a function of gate length is reported. The transistors were fabricated in SIMOX material with an estimated film thickness of 0.2 mu m, a buried insulator thickness of 0.4 mu m, and a gate oxide thickness of 20 nm. The measured threshold vo... View full abstract»

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  • 1990 IEEE SOS/SOI Technology Conference. (Cat. No.90CH2891-0)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Significant improvement in characteristics of SOS/MOSFETs by CW-Ar laser-recrystallization

    Publication Year: 1990, Page(s):134 - 135
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    Generally in SOS (silicon on sapphire) films, the density of Si defects such as twins and stacking faults is quite high, especially near the Si/sapphire interface, mainly due to the lattice mismatch between Si and sapphire. This leads to inferior electrical properties compared to their bulk counterparts. Although it has been reported that the characteristics of SOS devices can be improved by a pul... View full abstract»

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  • Interface characterization in fully depleted SOI MOSFETs by dynamic transconductance

    Publication Year: 1990, Page(s):42 - 43
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The interface characterization for very thin (fully depleted) SOI (silicon-on-insulator) layers is addressed. A new technique, dynamic transconductance, has recently been developed for bulk MOSFETs and exhibited important advantages. The technique has been successfully adapted to partially depleted and depletion mode SOI MOSFETs. A model for the application of the dynamic transconductance techniqu... View full abstract»

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  • Single event charge enhancement in SOI devices

    Publication Year: 1990, Page(s):27 - 28
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Studies of single-particle ion effects in SOI (silicon-on-insulator) devices show that a new mechanism can contribute to soft error rates: the electron-hole pairs generated in the silicon substrate can charge the back Si-SiO2-Si capacitor. An analysis with the 2-D device simulator JUPIN shows that the bulk Si substrate current contribution to the charging current is greater than the nor... View full abstract»

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  • Substrate floating effects of p-channel SOI MOSFETs

    Publication Year: 1990, Page(s):87 - 88
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    The floating substrate effects of p-channel MOSFETs fabricated on SOI substrates formed by oxygen implantation are studied. The kink effect occurs in the saturation regime for p-channel SOI MOSFETs when electrons are generated by impact ionization near the drain and swept by the electric field into the neutral floating substrate. This lowers substrate potential and thus changes the threshold volta... View full abstract»

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  • A general model of the thin-film SOI-MOSFET

    Publication Year: 1990, Page(s):105 - 106
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    A model for a thin-film SOI MOSFET which is valid in all regions of inversion is presented. It takes into account all conditions at the back surface of the silicon film, including inversion. To achieve an analytical expression for the inversion layer charge as a function of the front and back surface potentials, the contribution of the accumulation layer to the total charge is neglected. Two-dimen... View full abstract»

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  • Residual defects in SIMOX: threading dislocations and pipes

    Publication Year: 1990, Page(s):154 - 155
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    Some techniques are discussed for monitoring dislocations and stacking faults in SIMOX (separation by implantation of oxygen) films. Also, a different type of defect, a silicon pipe running through the buried oxide, has been observed. The origin of these defects and a technique for detecting them are described View full abstract»

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  • Rounded edge mesa for submicron SOI CMOS process

    Publication Year: 1990, Page(s):132 - 133
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    Different isolation features have been proposed for silicon on insulator (SOI): LOCOS, mesa, and reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. The rounded edge mesa (REM) presented allows accurate control of the gate dimensions without shorts. A 0.8 μm DL... View full abstract»

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  • Noise overshoot at drain current kink in SOI MOSFET

    Publication Year: 1990, Page(s):40 - 41
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (... View full abstract»

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  • Negative conductance model for short-channel SOI MOSFET

    Publication Year: 1990, Page(s):25 - 26
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    A short-channel SOI (silicon on insulator) n-channel MOSFET when source/drain junctions bottom out to the buried oxide may display a negative conductance in the output characteristics when the body tie is connected to the source. This phenomenon has been recently attributed to a temperature effect. However, the temperature effect is too small to account for the observation. Based on the theory of ... View full abstract»

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  • P-JFET on SIMOX for rad-hard analog devices

    Publication Year: 1990, Page(s):85 - 86
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    Development of a fully CMOS and bipolar compatible JFET process on SIMOX is reported. The main characteristics obtained on a two-junction-type JFET realized in 1-μm silicon epitaxy on SOI material are presented. A mesa-structure has been chosen for lateral isolation. A deep junction is arsenic implanted before epitaxy at 1000°C; the channel and drain/source doping levels are controlled by i... View full abstract»

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  • Low frequency noise spectroscopy in thin SIMOX MOS transistors

    Publication Year: 1990, Page(s):103 - 104
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    The analysis of the low-frequency noise in SOI MOSFETs is addressed. A simple model is presented which takes into consideration the parallel combination of three sources of noise, associated respectively with the two interfaces and the SI film volume. This model is also convenient for the analysis of depletion-mode SOI transistors. The original point in partially-depleted N N View full abstract»

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  • Salicide technology for fully-depleted SOI CMOS devices

    Publication Year: 1990, Page(s):79 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Self-aligned silicide (salicide) is necessary to reduce device resistances associated with an ultra-thin film fully-depleted (UTF/FD) CMOS SOI technology. A salicide process for use with UTF/FD CMOS SOI devices is developed, and subsequent transistor characteristics are shown. Process optimization was achieved through experimental design techniques by minimizing salicide sheet resistance and impro... View full abstract»

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  • SIMOX layers and interfaces studies with a new fast multichannel spectroscopic ellipsometer

    Publication Year: 1990, Page(s):152 - 153
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    A nondestructive optical technique, spectroscopic ellipsometry (SE), used to control top SiO2, silicon, and buried SiO2 layer thicknesses, as well as interfaces of these layers during SIMOX (separation by implantation of oxygen) wafer fabrication, is addressed. New improvements on SE give the capability to measure a complete spectrum within 1 s without losing useful informat... View full abstract»

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  • Novel diffusion effects in a dielectrically isolated BIMOS process using SOI substrates

    Publication Year: 1990, Page(s):130 - 131
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    The implementaton is discussed of a bulk BIMOS process which incorporates vertical bipolar devices on a thick (5 μm) film silicon-on-insulator (SOI) substrate. When trench isolation is incorporated in such a process, fully dielectrically isolated devices can be fabricated. By appropriate application of the trench technology, no change in the electrical device parameters will be produced by such... View full abstract»

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  • Advances in recrystallization technology

    Publication Year: 1990, Page(s):53 - 54
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    A program is briefly reported aimed at the development of SOI material using a seeded zone melting recrystallization (ZMR) technique which is known as isolated silicon epitaxy (ISE). The ISE process has the flexibility required to meet the demands of a variety of different applications. Specifically, thin films of epitaxial Si (0.10 μm) on thin SiO2 (0.4 μm) layers are being produ... View full abstract»

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  • Hot carrier-induced aging of short channel SIMOX devices

    Publication Year: 1990, Page(s):38 - 39
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Degradation of submicron MOSFETs by hot carrier injection is addressed. Results illustrating the sensitivity of the front and bank interfaces to various hot-carrier injection conditions are presented. The influence of gate, substrate, and drain biases, duration, and channel length is evaluated. The devices were LOCOS isolated, N-channel LDD, and conventional P-channel MOSFETs with 1-μm length. ... View full abstract»

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  • Consideration of the structure design for thin SOI/MOSFET under and beyond the half micron regime

    Publication Year: 1990, Page(s):23 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    A salicide process for thin SIMOX MOSFETs was developed, and the prospect of device application in the submicron regime was examined by evaluating the current drivability of MOSFETs and analyzing its limiting factors in both short and long channel regions. One problem in the scaling of thin-SOI MOSFETs (especially for NMOS) was the lowered drain breakdown voltage caused by parasitic bipolar operat... View full abstract»

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  • Generation lifetime in fully depleted, enhancement mode SOI MOSFETs

    Publication Year: 1990, Page(s):139 - 140
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    A new technique for determining the generation lifetime in fully-depleted, enhancement-mode SOI (silicon-on-insulator) MOSFETs is described. Island isolated, fully depleted n-channel MOSFETs of various widths and lengths fabricated in different thicknesses of SIMOX (separation by implantation of oxygen) SOI films were used in this experiment. The nature of the charge generation and the charge accu... View full abstract»

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  • Incorporation of an engineering mobility model in an accurate analytical I-V description for SOI devices

    Publication Year: 1990, Page(s):109 - 110
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    An accurate circuit-simulation-level mobility model for fully depleted SOI MOS devices is presented. It forms a solid basis for further optimization of specific thin-film properties. It is based on a local semiempirical carrier mobility model. The model can include all possible scattering mechanisms. It can also be used for low temperature ranges, where Coulomb scattering is dominant. A satisfacto... View full abstract»

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  • A trench isolated SOI bipolar process

    Publication Year: 1990, Page(s):83 - 84
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    BESOI (bond and etchback silicon-on-insulator) substrates were used to create a trench isolated SOI process. The SOI substrates reduce the substrate capacitance and achieve better decoupling between digital and analog portions of the circuits. Changes were made to the process to incorporate the SOI substrates, but overall the process complexity was reduced using these substrates. The BESOI substra... View full abstract»

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  • Limitations to fully-depleted SOI structures

    Publication Year: 1990, Page(s):101 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    The authors demonstrate the mobility and threshold voltage behavior for fully depleted transistors of various geometries on various epitaxial silicon thicknesses. Electrical characterization techniques were used to examine fully depleted SIMOX SOI front- and back-gate transistors of gate geometries between 0.6 and 3 μm on epitaxial silicon of thicknesses between 150 and 300 nm. Degradation in N... View full abstract»

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  • Charge densities at silicon interfaces prepared by wafer bonding

    Publication Year: 1990, Page(s):77 - 78
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    It is found that Si/Si and Si/SiO2 interfaces exhibit different interface charge properties when bonded at comparable temperatures and surface treatments. Thermally grown oxides were bonded to bare silicon surfaces and the bonded Si/SiO2 interface was investigated on MOS-structures by the C-V technique. Interfaces prepared at temperatures in the range 900-11... View full abstract»

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  • Radiation induced kink effects on SOI PMOS transistors

    Publication Year: 1990, Page(s):97 - 98
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    The authors discuss the influence of back oxide trapped charges on the degradation of the output characteristics of irradiated SOI PMOS transistors. It is found that a positive back gate bias during gamma irradiation promotes an accumulation of trapped holes at the Si-SiO2 interface in the buried oxide. The induced parasitic kink effect, which is usually present in SOI NMOS, has been ob... View full abstract»

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