Scheduled System Maintenance
On Thursday, July 20, IEEE Xplore will undergo scheduled maintenance from 1:00-3:00 PM ET.
During this time, there may be intermittent impact on performance. We apologize for any inconvenience.
By Topic

Computer Architecture for Machine Perception, 1997. CAMP 97. Proceedings. 1997 Fourth IEEE International Workshop on

20-22 Oct. 1997

Filter Results

Displaying Results 1 - 25 of 41
  • Proceedings Fourth IEEE International Workshop On Computer Architecture For Machine Perception [front matter]

    Publication Year: 1997, Page(s):i - vii
    Request permission for commercial reuse | PDF file iconPDF (1667 KB)
    Freely Available from IEEE
  • Proceedings Fourth IEEE International Workshop on Computer Architecture for Machine Perception. CAMP'97

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (904 KB)
    Freely Available from IEEE
  • Investigating real-time validation of real-time image processing ASICs

    Publication Year: 1997, Page(s):116 - 125
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB)

    The research presented in this paper aims at designing real-time image processing Application Specific Integrated Circuits (ASICs), with emphasis on the need for correct circuits. The methodology is based on a dedicated emulator, the Data-Flow Functional Computer (DFFC), whose peak capacity is 20 million gates operating at 25 MHz. Applications are firstly validated in their target environment (rea... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An interactive tool for C.V. tutorials

    Publication Year: 1997, Page(s):170 - 174
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1147 KB)

    This work proposes TuLIP: a tool for the creation and fruition of tutorials on image processing and analysis. TuLIP is built around the idea that code in a very high level language can work both as as the way of performing a task and as the reference of the task it implements. TuLIP supports users and authors with tailored working modalities and supplies an interactive environment leading to pract... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Page segmentation using a pyramidal architecture

    Publication Year: 1997, Page(s):195 - 199
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    In this paper we propose a new page segmentation method for recognizing text and graphics based on a multiresolution representation of the page image. Our approach is based on the analysis of a set of feature maps available at different resolution levels. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Image processing in a tree of peano coded images

    Publication Year: 1997, Page(s):229 - 234
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (598 KB)

    The authors investigate some attractive features of the 1-D sequence of pixels produced by the peano traversal of an image. They introduce two new hardware operations called bit-spreaded-meshing and its inverse brit-collation to produce and invert the sequence in real-time. A compact binary tree built using this sequence at its base implicitly contains the well known quadtree of the image also. Th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Author index

    Publication Year: 1997, Page(s):300 - 301
    Request permission for commercial reuse | PDF file iconPDF (73 KB)
    Freely Available from IEEE
  • Parallel object recognition on an FPGA-based configurable computing platform

    Publication Year: 1997, Page(s):143 - 152
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (996 KB)

    Object recognition involves identifying known objects in a given scene. It plays a key role in image understanding. Geometric hashing has been proposed as a technique for model-based object recognition in occluded scenes. However, parallel techniques are needed to realize real-time vision systems employing geometric hashing. In this paper, we develop a design technique for parallelizing geometric ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multilayer perceptrons on Splash 2

    Publication Year: 1997, Page(s):138 - 142
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Multilayer perceptrons (MLPs) are one of the most popular neural network models for solving pattern classification and image classification problems. Because of their ability to learn complex decision boundaries, MLPs are used in many practical computer vision applications involving classification (or supervised segmentation). Once the connection weights in a MLP have been learnt, the network can ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A cost-effective morphological filter architecture

    Publication Year: 1997, Page(s):285 - 289
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce the hardware cost by using a feedback loop path and a decoder/encoder pair comparator. The feedback loop path can reuse partial results and the decoder/encoder pair comparator can reduce the gate delay and the gate count especially whe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • FPGA-based computing in computer vision

    Publication Year: 1997, Page(s):128 - 137
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1048 KB)

    Algorithms in computer vision are characterized by (i) complex and repetitive operations; (ii) large amount of data and (iii) a variety of data interaction (e.g., point operations, neighborhood operations, global operations). Based on the computation and communication complexity, vision algorithms have been characterized into three categories: (i) low-level, (ii) intermediate-level and (iii) high-... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A scalable architecture for low and intermediate level image processing

    Publication Year: 1997, Page(s):270 - 274
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    This paper proposes a design for a scalable architecture for low and intermediate level image processing in real-time applications. The architecture is envisioned as a plug-in extension to plain personal workstations or MIMD systems. The main focus points of the architecture design are the scalability, handling of different image sizes, and providing hardware support for a technique named bucket p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Vision chip architecture using general-purpose processing elements for 1 ms vision system

    Publication Year: 1997, Page(s):276 - 279
    Cited by:  Papers (34)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    This paper describes a vision chip architecture for high-speed vision systems that we propose. The chip has general-purpose processing elements (PEs) in massively parallel architecture, with each PE directly connected to photo-detectors. Control programs allow various visual processing applications and algorithms to be implemented. A sampling rate of 1 ms is enough to realize high-speed visual fee... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The DARPA image understanding motion benchmark

    Publication Year: 1997, Page(s):260 - 269
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    Benchmarks and test suites are an essential element of the architectural evaluation process. At the conclusion of the last DARPA workshop on vision benchmarks to test the performance of parallel architectures, it was recommended that the DARPA Image Understanding Benchmark be extended with a second level task to add motion and tracking to the original task. We have now developed this new benchmark... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Image processing PCI-based shared memory architecture design

    Publication Year: 1997, Page(s):244 - 252
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    The object of the GFLOPS project was to study all aspects concerning the design of a low cost parallel architecture. The project's aim was to develop a parallel architecture as well as its software environment to implement image processing applications efficiently. The proposed architecture supports up to 512 processor nodes, which are PC mother boards, connected over a scalable and cost-effective... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware-software aspects of shift-register based NEWS networks for the focal plane

    Publication Year: 1997, Page(s):84 - 93
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1112 KB)

    Processing medium-size images in the chip where they are sensed has now become technologically possible. Such devices are called artificial retinas. In order to set up a whole programmable boolean array processor in the focal plane, a specific NEWS interconnection network is required that trades off between speed, silicon area, energy consumption, and controllability. Shift-register based solution... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Making a dataparallel language portable for massively parallel array computers

    Publication Year: 1997, Page(s):160 - 169
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (972 KB)

    A key goal in language design is to simultaneously achieve portability and efficiency. Achieving a general solution to this problem is quite difficult: virtually all attempts have emphasized one or the other requirement by restricting either the architecture domain, the application domain, or both. In this study we present (i) a framework that explains why meeting these requirements simultaneously... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new real time edge linking algorithm and its VLSI implementation

    Publication Year: 1997, Page(s):280 - 284
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Edges produced by existing edge detection algorithms often contain discontinuities. Edge linking as a post-processing step is an important step for computer vision and pattern recognition. We present a real-time algorithm and its VLSI implementation for linking broken edges. First, all broken edge points inside a 12×12 moving window are identified. The 12×12 window scans the input gray... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fast parallel algorithm for stereovision

    Publication Year: 1997, Page(s):200 - 203
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A new stereo algorithm based on local spatial filter operations and a fast coherence detection scheme is presented. The algorithm achieves performance similar to classical area-based approaches, but without the complicated hierarchical search structure typical for these approaches. The algorithm is fully parallel; disparity values and a corresponding verification count are calculated independently... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A dedicated image processor exploiting both spatial and instruction-level parallelism

    Publication Year: 1997, Page(s):106 - 115
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    This paper presents the PAPRICA-3 massively parallel SIMD system, designed as a hardware accelerator for real-time image processing tasks. It is composed of a linear array of single-bit processing elements, including a fairly complex pipelined controller, thus allowing the system to take advantage also of the intrinsic parallelism in a program. A programming environment has been developed to ease ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Context: a new paradigm to control distributed perceptual systems

    Publication Year: 1997, Page(s):175 - 179
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    This paper deals with problems of representation and handling of concurrent processes in multiprocessor machines or in distributed and co-operating systems oriented to image analysis. For this purpose a new synchronization mechanism, named context is presented. Contexts are introduced as object variables in pictorial languages to represent distributed computation on spatial data. In particular, de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hough transform implementation on a reconfigurable highly parallel architecture

    Publication Year: 1997, Page(s):186 - 194
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    A highly parallel hardware architecture for Hough Transform (HT)-based parametric curve and end-points extraction is described. It's based on CAM (Content Addressable Memory) concept. Through using advanced VLSI technology, to classical CAM implementations, three main features are provided: Parallel write, parallel search and single/multi hit response flag. Moreover the high number of CAM words av... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Asynchronous SIMD: an architectural concept for high performance image processing

    Publication Year: 1997, Page(s):235 - 242
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    Traditional single-instruction multiple-data (SIMD) array processors have fallen out of favor for a long list of reasons. Most of these problems can be traced to the synchronous and monolithic nature of the array. The article lists the problems that derive from those characteristics and then proposes an asynchronous variation on the SIMD array that appears to have considerable potential for addres... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Motion vision sensor architecture with asynchronous self-signaling pixels

    Publication Year: 1997, Page(s):75 - 83
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    A custom CMOS imager with integrated motion computation is described. The architecture is based on correlating in time moving edges. Edges are located in time by a custom sensor; and correlated in a coprocessing module. The sensor architecture is centered around a compact pixel with analog signal processing and digital self-signaling capabilities. The sensor pixels detect moving edges in the image... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A specific compilation scheme for image processing architecture

    Publication Year: 1997, Page(s):56 - 60
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper presents a compilation scheme for a high-level programming environment CT++ that allows to obtain good performance at a low engineering cost. CT++ is based on C++ and has been designed to easily develop algorithms on multi-SIMD parallel computers. We compare our implementation mechanism with others and show that it produces efficient code for ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.