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Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Date 17-19 Oct. 1994

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Displaying Results 1 - 25 of 36
  • IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

    Publication Year: 1994
    Request permission for commercial reuse | PDF file iconPDF (184 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1994, Page(s): 299
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (43 KB)

    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • Defect and fault tolerant scan chains

    Publication Year: 1994, Page(s):185 - 193
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    Several fault tolerant scan chain designs are proposed, including the combinational one data flow and two data flow approaches, and the counter based approach. It is shown that these designs have no critical portion, where a single defect would make the chain inoperative. The yield of these chains is evaluated to show that a long intolerant chain is a predominant yield or harvest detractor, while ... View full abstract»

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  • A fault-tolerant associative approach to on-line memory repair

    Publication Year: 1994, Page(s):168 - 176
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed sc... View full abstract»

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  • Reconfiguration in 3D meshes

    Publication Year: 1994, Page(s):194 - 202
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The 1½ track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. It is also shown that switch r... View full abstract»

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  • Fault tolerant design using error correcting code for multilayer neural networks

    Publication Year: 1994, Page(s):177 - 184
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A new fault tolerant multilayer neural network (NN) which can correct an error caused by a fault in the output layer neuron is proposed. The principle of the design is that an error correcting code is used for the output space of NN, and NN learns this code in the training phase. Simulation experiments for some examples in relatively small pattern recognition models are examined. As a result, it c... View full abstract»

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  • On fractal yield models: a statistical paradox

    Publication Year: 1994, Page(s):83 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Although the fractal yield model is very successful in VLSI applications, it also exposes a mathematical inconsistency. Expressing the average number of faults in each sub array, the average number of faults in the complete array, according to this approach, is not statistically correct. This, therefore, is a fractal paradox View full abstract»

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  • Laser processes for defect correction in large area VLSI systems

    Publication Year: 1994, Page(s):106 - 114
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    The post fabrication laser processing techniques of cutting lines and forming connections is effective in removing defects and enhancing fault tolerance in large area VLSI circuits. Successful applications require designs which include redundant sections for substitution and defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requi... View full abstract»

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  • On soft switch programming for reconfigurable array systems

    Publication Year: 1994, Page(s):203 - 211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper deals with the programming and control of non-permanent (soft) switching elements in an augmented interconnection network of a two-dimensional VLSI/WSI array. In particular, it is addressed the issue of cost for programming soft switches involved in the routing process for the interconnections from the primary pad pins. Cost is analyzed with respect to the complexity of the switches (as... View full abstract»

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  • Design of cover circuits for monitoring the output of a MISA

    Publication Year: 1994, Page(s):124 - 132
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper, an improved BIST structure is investigated. The output of the MISA is monitored by an error detection circuit during the application of the test sequence. The error detection circuit has to detect only those faults which are aliased by the MISA. By use of this method, no erroneous output sequence of the circuit under test can go undetected. It is demonstrated how the error detection... View full abstract»

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  • Fault-tolerant modular convolvers

    Publication Year: 1994, Page(s):37 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    A preceding research, concerning the architecture of a convolver capable of accepting a sequence of groups of p samples presented simultaneously and of generating at p output ports the corresponding sequence of convolution groups, is expanded with a new approach. In this architecture the convolver is decomposed into a linear array of p identical “phase-convolvers” associated with ident... View full abstract»

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  • Reliability estimation for time redundant error correcting adders and multipliers

    Publication Year: 1994, Page(s):159 - 167
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    There has been much study of concurrent error correction in arithmetic processors like adders and multipliers but they are not practical because of their high expense. The redundancy introduced to achieve fault-tolerance in a system can be in the form of either hardware, information, or time. The most straightforward method is to use hardware redundancy by triplicating the adder or multiplier and ... View full abstract»

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  • Highly testable and compact 1-out-of-n CMOS checkers

    Publication Year: 1994, Page(s):142 - 150
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    This paper presents an original concept for implementing 1-out-of-n (1/n) checkers (for any value of n), that are Totally Self Checking with respect to a set of realistic faults including also all resistive bridgings. With respect to other 1/n CMOS checkers, the proposed circuits feature higher self-testing capability and smaller silicon area. The advantages are obtained at the cost of a static po... View full abstract»

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  • Synthesis of multi-level self-checking logic

    Publication Year: 1994, Page(s):115 - 123
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The problem of implementing self-checking combinational circuits is taken into account, with the initial requirement that self-checking capabilities be provided for otherwise optimized multilevel circuits produced by standard CAD tools, without affecting the circuit topology. The solution proposed involves a preliminary reduction of the number of inverters present in the circuit (it is assumed tha... View full abstract»

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  • The effect of wire length minimization on yield

    Publication Year: 1994, Page(s):97 - 105
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    Wire length minimization (WLM) has received significant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may still exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns ... View full abstract»

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  • An approach to the development of a Iddq testable cell library

    Publication Year: 1994, Page(s):46 - 54
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Many VLSI integrated circuit processing defects can cause changes in the behaviour of the quiescent power supply current. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide range of physical defects. In this paper we present one approach to Iddq testing based on the application of BIC sensors to a cell library des... View full abstract»

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  • A self-reconfiguration architecture for mesh arrays

    Publication Year: 1994, Page(s):212 - 220
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Recent advances in VLSI technology has stimulated research in massively parallel computers to satisfy the continuously increasing demand for computer power in advanced science and technology applications. Mesh-interconnection is one of the most attractive interconnections and architectures for massively parallel computers. This paper addresses a new reconfigurable architecture to implement massive... View full abstract»

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  • Alternative approaches to fault detection in FSMs

    Publication Year: 1994, Page(s):271 - 279
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    This paper addresses the detection of permanent or transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. On-line test devices are automatically generated by a specific synthesis tool (ASYL-SdF), avoiding design time overhead. Two approaches based on control-flow checking methods are available to the designer and it is shown that each of these ap... View full abstract»

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  • A general method to design and reconfigure loop-based linear arrays

    Publication Year: 1994, Page(s):221 - 229
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Loop-based defect-tolerant design of linear arrays is easy to manufacture, test and reconfigure. Previous researchers have given ad hoc designs for specific number of neighbors and interconnection patterns. In this paper, we give general results on design and reconfiguration for any number of neighbors and interconnection patterns to achieve best cost/performance View full abstract»

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  • Using Fourier analyses to enhance IC testability

    Publication Year: 1994, Page(s):280 - 288
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    In this paper, we explore the potential of FFTs in digital IC tests. The effects of three parasite contact types are investigated. Results show that unappropriate logical values on output voltages are easily detected and that FFTs on supply current can make detectable undesired contacts causing additional delays. Application of the method to technologies with non small quiescent currents and to la... View full abstract»

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  • Efficient critical area algorithms and their application to yield improvement and test strategies

    Publication Year: 1994, Page(s):88 - 96
    Cited by:  Papers (14)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a ... View full abstract»

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  • Implementation of a gracefully degradable binary tree in programmable multi-chip modules

    Publication Year: 1994, Page(s):28 - 36
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A multi-chip module is proposed as a packaging scheme for a binary tree processing array in order to contain the whole system in a single package. Fault tolerance is provided to the array by a pass transistor switching network in the MCM silicon substrate. The benefits of an active substrate base can offset the expense and complexity of an MCM design when it has application to many circuits. The s... View full abstract»

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  • Statistical analysis of particle/defect data experiments using Poisson and logistic regression

    Publication Year: 1994, Page(s):230 - 238
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    This paper deals with the analysis of particle or defect data collected on silicon wafers at specific points during the IC manufacturing process, where a designed experiment was planned. To determine which experimental factors and settings have an impact on contamination is of primary concern when making decisions for reducing defects during the IC manufacturing process. This paper shows how one c... View full abstract»

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  • Augmenting scan path SRLs with an XOR network to enhance delay fault testing

    Publication Year: 1994, Page(s):55 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper, we present a technique to enhance transition delay and stuck-open fault testing in an LSSD environment. To reduce shift dependency in the scan path, thereby improving transition quality, a re-arrangement heuristic combined with a one level XOR network is proposed. The method is hierarchical, combining a simple re-arrangement, heuristic driven local reconfiguration, and finally a cir... View full abstract»

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  • Yield enhancement with particle defects reduction

    Publication Year: 1994, Page(s):246 - 253
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    Contamination control is a major issue in VLSI fabrication. Particle control, in particular, is crucial to the success and profitability of the manufacturing process. While most production lines have a particle monitoring system, the direct correlation between defect level and device yield is not always obvious, and therefore prioritizing quick yield improvement efforts can be difficult. This pape... View full abstract»

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