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Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on

Date 17-19 Oct. 1994

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  • IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

    Publication Year: 1994
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1994 , Page(s): 299
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    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • Implementation of a gracefully degradable binary tree in programmable multi-chip modules

    Publication Year: 1994 , Page(s): 28 - 36
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    A multi-chip module is proposed as a packaging scheme for a binary tree processing array in order to contain the whole system in a single package. Fault tolerance is provided to the array by a pass transistor switching network in the MCM silicon substrate. The benefits of an active substrate base can offset the expense and complexity of an MCM design when it has application to many circuits. The standard interconnect pattern of binary trees would allow many binary tree applications to share such a pre-fabricated substrate. The switching network provides reconfiguration of the original tree to a gracefully degraded binary tree. The largest functioning binary tree which can be extracted from the original tree will be connected to the existing I/O pads. The algorithm used to obtain this subtree is complete and also contains a heuristic approach in its search. A simple procedure is provided to control the reconfiguration switches. The benefits of this technique over previous reconfiguration schemes involving spare processing elements is that the scheme involves a minimum of hardware and signal delay View full abstract»

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  • Statistical analysis of particle/defect data experiments using Poisson and logistic regression

    Publication Year: 1994 , Page(s): 230 - 238
    Cited by:  Papers (1)  |  Patents (1)
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    This paper deals with the analysis of particle or defect data collected on silicon wafers at specific points during the IC manufacturing process, where a designed experiment was planned. To determine which experimental factors and settings have an impact on contamination is of primary concern when making decisions for reducing defects during the IC manufacturing process. This paper shows how one can fit models to particle data by means of Poisson regression while taking into account chip level correlations and wafer-to-wafer variability. It is shown that when these factors are not taken into account, the model specified does not fit the data properly and the significance levels of the test statistics are smaller than they should be. This can lead to declaring factors significant when in fact they are not. We provide several examples of particle data on wafers and also airborne particle data obtained from a fabrication facility experiment aimed at decreasing the level of microcontaminants in the fabrication facility itself. Finally, we show how to classify these particle data into “killed die” and thus the analysis of independent factors can be performed with the use of an overdispersed logistic model. Practical analysis considerations are given to make the reader aware of the possible pitfalls one can fall into if nor considered. Future directions and limitations are discussed briefly View full abstract»

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  • Highly testable and compact 1-out-of-n CMOS checkers

    Publication Year: 1994 , Page(s): 142 - 150
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    This paper presents an original concept for implementing 1-out-of-n (1/n) checkers (for any value of n), that are Totally Self Checking with respect to a set of realistic faults including also all resistive bridgings. With respect to other 1/n CMOS checkers, the proposed circuits feature higher self-testing capability and smaller silicon area. The advantages are obtained at the cost of a static power consumption that, however, compared with that typical of an alternate technique, will be shown to be not excessive and reducible by means of suitable techniques. In addition, as an example of the testability improvement achievable by means of the proposed implementations, the case of 1-out-of-3 will be explicitly treated View full abstract»

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  • A general method to design and reconfigure loop-based linear arrays

    Publication Year: 1994 , Page(s): 221 - 229
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    Loop-based defect-tolerant design of linear arrays is easy to manufacture, test and reconfigure. Previous researchers have given ad hoc designs for specific number of neighbors and interconnection patterns. In this paper, we give general results on design and reconfiguration for any number of neighbors and interconnection patterns to achieve best cost/performance View full abstract»

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  • Defect and fault tolerant scan chains

    Publication Year: 1994 , Page(s): 185 - 193
    Cited by:  Papers (1)
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    Several fault tolerant scan chain designs are proposed, including the combinational one data flow and two data flow approaches, and the counter based approach. It is shown that these designs have no critical portion, where a single defect would make the chain inoperative. The yield of these chains is evaluated to show that a long intolerant chain is a predominant yield or harvest detractor, while a tolerant chain becomes an insignificant factor to system yield or harvest View full abstract»

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  • Fault tolerant design using error correcting code for multilayer neural networks

    Publication Year: 1994 , Page(s): 177 - 184
    Cited by:  Papers (2)
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    A new fault tolerant multilayer neural network (NN) which can correct an error caused by a fault in the output layer neuron is proposed. The principle of the design is that an error correcting code is used for the output space of NN, and NN learns this code in the training phase. Simulation experiments for some examples in relatively small pattern recognition models are examined. As a result, it can be concluded that SEC-DED codes together with some training method are sufficient for the examples, and the proposed design can be adapted effectively to practical applications View full abstract»

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  • A yield study of VLSI adders

    Publication Year: 1994 , Page(s): 239 - 245
    Cited by:  Papers (2)
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    Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17% View full abstract»

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  • Reliability estimation for time redundant error correcting adders and multipliers

    Publication Year: 1994 , Page(s): 159 - 167
    Cited by:  Papers (4)
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    There has been much study of concurrent error correction in arithmetic processors like adders and multipliers but they are not practical because of their high expense. The redundancy introduced to achieve fault-tolerance in a system can be in the form of either hardware, information, or time. The most straightforward method is to use hardware redundancy by triplicating the adder or multiplier and taking a majority vote at the output. This is called Triple Modular Redundancy (TMR). The concept is simple but the hardware overhead is high. With the information redundancy approach, error correcting codes are used but the complexity is prohibitively high. Time redundancy is an approach to achieve fault-tolerance for arithmetic processors without introducing too much hardware overhead. It can be used in applications where minimizing the hardware complexity is the primary concern. REcomputing with Triplication With Voting (RETWV) is an error-correcting architecture using time redundancy. It is practical because its hardware overhead is much lower than that of the other approaches and their delay time is acceptable. In this paper, the reliability of VLSI time redundant error-correcting adders and multipliers is estimated. It is shown that RETWV has higher reliability improvement than that obtainable by TMR View full abstract»

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  • Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method

    Publication Year: 1994 , Page(s): 254 - 262
    Cited by:  Papers (3)
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    This paper presents a mixed approach for sequential circuit test pattern generation employing the accuracy of structural algorithms and the speed of a pattern generator working at the functional level. The new strategy selects from the State Transition Graph of a Finite State Machine the appropriate edges that allow a functional test pattern generator (FSMTest) to build test sequences covering 100% of the detectable single stuck-at and gate-delay faults. Experiments and comparisons are presented to justify the proposed test strategy View full abstract»

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  • Efficient critical area algorithms and their application to yield improvement and test strategies

    Publication Year: 1994 , Page(s): 88 - 96
    Cited by:  Papers (13)  |  Patents (5)
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    Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a given size. The edges are used to generate fault critical areas. These are critical areas that are classified by the list of circuit nodes that are shorted by a defect of the given size falling within that area. Fault critical areas generated for a range of defect sizes can be used to produce fault probabilities between individual circuit nodes and enable device test procedures and redundancy strategies to be optimised. The algorithms have the advantage that they are not restricted to Manhatten layout and that they are computationally efficient View full abstract»

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  • On fractal yield models: a statistical paradox

    Publication Year: 1994 , Page(s): 83 - 87
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    Although the fractal yield model is very successful in VLSI applications, it also exposes a mathematical inconsistency. Expressing the average number of faults in each sub array, the average number of faults in the complete array, according to this approach, is not statistically correct. This, therefore, is a fractal paradox View full abstract»

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  • An approach to the development of a Iddq testable cell library

    Publication Year: 1994 , Page(s): 46 - 54
    Cited by:  Papers (5)
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    Many VLSI integrated circuit processing defects can cause changes in the behaviour of the quiescent power supply current. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide range of physical defects. In this paper we present one approach to Iddq testing based on the application of BIC sensors to a cell library design methodology. The size of the sensor will depend on the length of the row as well as on the frequency of the circuit under test View full abstract»

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  • Reconfiguration in 3D meshes

    Publication Year: 1994 , Page(s): 194 - 202
    Cited by:  Papers (6)
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    The 1½ track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. It is also shown that switch reconfiguration after faults is local in the sense that the state of each switch is uniquely determined by the state of the processors connected to it View full abstract»

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  • Multi-layer interconnect yield model for mega bit BiCMOS SRAMs

    Publication Year: 1994 , Page(s): 289 - 297
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    Multi-layer interconnect yield model for mega bit BiCMOS SRAM utilizes the information from the multi-layer interconnect structure and details of the SRAM chip interconnect layout. The multi-layer interconnect yield accurate information concerning the defect size distribution which is a function of the interconnect process technology employed in the SRAM chip. The model is based on the interconnect defect density and multi-layer interconnect area. A case study of 4-Mb BiCMOS SRAM chip yield analysis results are presented View full abstract»

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  • A defect and fault tolerant interconnection network strategy for WASP devices

    Publication Year: 1994 , Page(s): 19 - 27
    Cited by:  Papers (5)
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    The paper presents an investigation on interconnect defect occurrences observed on a WASP (i.e. WSI Associative String Processor) device, the WASP 2B, as part of an ongoing WSI interconnect experimental study that started on a sister device, the WASP 2A. Thus, after a brief overview of the WASP 2B device and the analysis of observed defect data on its interconnect, this paper examines: (i) the implications of these experimental studies and (ii) strategies necessary for the implementation of a defect and fault tolerant interconnection network for future WASP devices (i.e. WASP 3, 4, and 5), in the light of the experiences gained View full abstract»

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  • Roundoff error-free tests in algorithm-based fault tolerant matrix operations on 2-D processor arrays

    Publication Year: 1994 , Page(s): 74 - 82
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    Assaad and Dutt [1992] proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the threshold test in their approach is still necessary in the floating-point addition part of the matrix multiplication, and the number of error detections decreases with the increase in the dynamic range of data. Here, instead of using the threshold floating-point checksum test, we present an effective method, called the concurrent floating-point checksum (CFPC) test. The proposed CFPC test provides complete error detection/correction capabilities in floating-point additions with less time latency and hardware overhead regardless of the dynamic range of input data View full abstract»

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  • Yield enhancement with particle defects reduction

    Publication Year: 1994 , Page(s): 246 - 253
    Cited by:  Papers (2)
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    Contamination control is a major issue in VLSI fabrication. Particle control, in particular, is crucial to the success and profitability of the manufacturing process. While most production lines have a particle monitoring system, the direct correlation between defect level and device yield is not always obvious, and therefore prioritizing quick yield improvement efforts can be difficult. This paper discusses a solution with the total particle control system which has provided a practical method for yield enhancement View full abstract»

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  • A self-reconfiguration architecture for mesh arrays

    Publication Year: 1994 , Page(s): 212 - 220
    Cited by:  Papers (5)
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    Recent advances in VLSI technology has stimulated research in massively parallel computers to satisfy the continuously increasing demand for computer power in advanced science and technology applications. Mesh-interconnection is one of the most attractive interconnections and architectures for massively parallel computers. This paper addresses a new reconfigurable architecture to implement massively parallel mesh-arrays on a silicon wafer by wafer scale integration (WSI), which is expected as a promising technology to construct massively parallel computers on silicon wafers. The performance of the proposed scheme is discussed with respect to system yield. It is confirmed that the reconfigurable architecture without global information on the fault distribution achieves the same system yield as the earlier designs based on a graph theory which requires global information View full abstract»

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  • On the analysis of routing, cells and adjacency faults in CMOS digital circuits

    Publication Year: 1994 , Page(s): 263 - 270
    Cited by:  Papers (1)
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    The continuous increase in integrated circuits (IC) complexity is pushing test preparation into higher levels of representation. High level techniques do not take into account the physical design; even logic level test preparation ignores it. As a consequence, estimations of test quality, and IC quality in the IC design environment are missing, or very inaccurate. Therefore, there is a need to capture low level (i.e., defects level) test information, for further use at higher levels. In this paper, two aspects have to be considered: (1) the efficient extraction of faults from the layout; and (2) the mapping of such faults into higher levels of representation. Bridging defects are selected, as they are associated with the most likely faults in today's process lines. The relative importance of routing, cells and adjacency faults is investigated, for digital CMOS standard cells layouts, generated with different libraries. It is shown that realistic routing faults can be used to achieve a good estimation of the defect level. However, depending on the layout of the cells, the cell and adjacency faults may play an important role in the defect level estimation. Results for commercial and proprietary cell libraries are presented, pointing out its influence on the overall quality of the IC's View full abstract»

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  • Scheduling policies for fault tolerance in a VLSI processor

    Publication Year: 1994 , Page(s): 1 - 9
    Cited by:  Papers (2)  |  Patents (1)
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    This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the results produced by comparing the outcomes of the two versions of the same job indicates that a fault may have occurred. Several methods for appropriately scheduling the primary and secondary versions of the jobs are proposed and analyzed View full abstract»

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  • The effect of wire length minimization on yield

    Publication Year: 1994 , Page(s): 97 - 105
    Cited by:  Papers (5)
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    Wire length minimization (WLM) has received significant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may still exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns and the spacing among them must be considered. The trade-off between these two features is analyzed on a set of benchmark layouts in this paper View full abstract»

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  • Design of cover circuits for monitoring the output of a MISA

    Publication Year: 1994 , Page(s): 124 - 132
    Cited by:  Papers (1)
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    In this paper, an improved BIST structure is investigated. The output of the MISA is monitored by an error detection circuit during the application of the test sequence. The error detection circuit has to detect only those faults which are aliased by the MISA. By use of this method, no erroneous output sequence of the circuit under test can go undetected. It is demonstrated how the error detection circuit can be realized by two simple cover circuits. Simulation experiments indicate that the hardware overhead for the cover circuits is less than 2% of the circuit under test. It is also demonstrated that in concrete designs the probability of an arbitrary fault-not necessarily in the fault model considered-remaining undetected is significantly smaller than with conventional BIST structure View full abstract»

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  • Augmenting scan path SRLs with an XOR network to enhance delay fault testing

    Publication Year: 1994 , Page(s): 55 - 63
    Cited by:  Papers (2)
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    In this paper, we present a technique to enhance transition delay and stuck-open fault testing in an LSSD environment. To reduce shift dependency in the scan path, thereby improving transition quality, a re-arrangement heuristic combined with a one level XOR network is proposed. The method is hierarchical, combining a simple re-arrangement, heuristic driven local reconfiguration, and finally a circuit modification to improve delay fault testing View full abstract»

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