IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

17-19 Oct. 1994

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  • IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

    Publication Year: 1994
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1994, Page(s): 299
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (43 KB)

    Presents an index of the authors whose papers are published in the conference. View full abstract»

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  • Alternative approaches to fault detection in FSMs

    Publication Year: 1994, Page(s):271 - 279
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    This paper addresses the detection of permanent or transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. On-line test devices are automatically generated by a specific synthesis tool (ASYL-SdF), avoiding design time overhead. Two approaches based on control-flow checking methods are available to the designer and it is shown that each of these ap... View full abstract»

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  • Roundoff error-free tests in algorithm-based fault tolerant matrix operations on 2-D processor arrays

    Publication Year: 1994, Page(s):74 - 82
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    Assaad and Dutt [1992] proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the threshold test in their approach is still necessary in the floating-point addition part of the matrix multiplication, and the number of error detections decreases with the increase in the dynamic ... View full abstract»

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  • On the analysis of routing, cells and adjacency faults in CMOS digital circuits

    Publication Year: 1994, Page(s):263 - 270
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    The continuous increase in integrated circuits (IC) complexity is pushing test preparation into higher levels of representation. High level techniques do not take into account the physical design; even logic level test preparation ignores it. As a consequence, estimations of test quality, and IC quality in the IC design environment are missing, or very inaccurate. Therefore, there is a need to cap... View full abstract»

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  • Laser processes for defect correction in large area VLSI systems

    Publication Year: 1994, Page(s):106 - 114
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (644 KB)

    The post fabrication laser processing techniques of cutting lines and forming connections is effective in removing defects and enhancing fault tolerance in large area VLSI circuits. Successful applications require designs which include redundant sections for substitution and defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requi... View full abstract»

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  • On the testability of CMOS feedback amplifiers

    Publication Year: 1994, Page(s):65 - 73
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    This paper examines the testability of a CMOS operational amplifier (op-amp) in four different feedback configurations. Feedback is often considered to complicate the testing problem. Here, we illustrate that it is possible to test the op-amp for catastrophic faults at wafer probe without having to remove feedback structures. Catastrophic, as well as parameter variation fault models, are used to s... View full abstract»

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  • Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method

    Publication Year: 1994, Page(s):254 - 262
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    This paper presents a mixed approach for sequential circuit test pattern generation employing the accuracy of structural algorithms and the speed of a pattern generator working at the functional level. The new strategy selects from the State Transition Graph of a Finite State Machine the appropriate edges that allow a functional test pattern generator (FSMTest) to build test sequences covering 100... View full abstract»

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  • The effect of wire length minimization on yield

    Publication Year: 1994, Page(s):97 - 105
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    Wire length minimization (WLM) has received significant attention in the compaction stage of VLSI layout synthesis. In most cases, reduction in wire length also results in better circuit yield. However, a trade-off may still exist between total wire length and yield. In WLM only the area/length of the layout patterns is considered whereas for yield enhancement both the area of the layout patterns ... View full abstract»

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  • Augmenting scan path SRLs with an XOR network to enhance delay fault testing

    Publication Year: 1994, Page(s):55 - 63
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    In this paper, we present a technique to enhance transition delay and stuck-open fault testing in an LSSD environment. To reduce shift dependency in the scan path, thereby improving transition quality, a re-arrangement heuristic combined with a one level XOR network is proposed. The method is hierarchical, combining a simple re-arrangement, heuristic driven local reconfiguration, and finally a cir... View full abstract»

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  • Yield enhancement with particle defects reduction

    Publication Year: 1994, Page(s):246 - 253
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    Contamination control is a major issue in VLSI fabrication. Particle control, in particular, is crucial to the success and profitability of the manufacturing process. While most production lines have a particle monitoring system, the direct correlation between defect level and device yield is not always obvious, and therefore prioritizing quick yield improvement efforts can be difficult. This pape... View full abstract»

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  • Implementation of a gracefully degradable binary tree in programmable multi-chip modules

    Publication Year: 1994, Page(s):28 - 36
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    A multi-chip module is proposed as a packaging scheme for a binary tree processing array in order to contain the whole system in a single package. Fault tolerance is provided to the array by a pass transistor switching network in the MCM silicon substrate. The benefits of an active substrate base can offset the expense and complexity of an MCM design when it has application to many circuits. The s... View full abstract»

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  • A general method to design and reconfigure loop-based linear arrays

    Publication Year: 1994, Page(s):221 - 229
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (352 KB)

    Loop-based defect-tolerant design of linear arrays is easy to manufacture, test and reconfigure. Previous researchers have given ad hoc designs for specific number of neighbors and interconnection patterns. In this paper, we give general results on design and reconfiguration for any number of neighbors and interconnection patterns to achieve best cost/performance View full abstract»

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  • A fault-tolerant associative approach to on-line memory repair

    Publication Year: 1994, Page(s):168 - 176
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed sc... View full abstract»

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  • Efficient critical area algorithms and their application to yield improvement and test strategies

    Publication Year: 1994, Page(s):88 - 96
    Cited by:  Papers (14)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    Two algorithms that calculate the critical areas of integrated circuit mask layout for extra material defects are presented. The first algorithm generates a set of edges that define the critical area of the layout for a given defect size. The second algorithm generates the set of fault critical area edges. These identify all possible extra material circuit faults that can occur from a defect of a ... View full abstract»

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  • An approach to the development of a Iddq testable cell library

    Publication Year: 1994, Page(s):46 - 54
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    Many VLSI integrated circuit processing defects can cause changes in the behaviour of the quiescent power supply current. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide range of physical defects. In this paper we present one approach to Iddq testing based on the application of BIC sensors to a cell library des... View full abstract»

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  • A yield study of VLSI adders

    Publication Year: 1994, Page(s):239 - 245
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    Several 64-bit adders have been designed and their expected yield has been estimated. Our results show that the yield of VLSI adders can be improved by modifying the layout of the original design and/or by choosing a different layout and circuit structure. In certain situations, these approaches can improve the yield by 10% to 17% View full abstract»

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  • A defect and fault tolerant interconnection network strategy for WASP devices

    Publication Year: 1994, Page(s):19 - 27
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (448 KB)

    The paper presents an investigation on interconnect defect occurrences observed on a WASP (i.e. WSI Associative String Processor) device, the WASP 2B, as part of an ongoing WSI interconnect experimental study that started on a sister device, the WASP 2A. Thus, after a brief overview of the WASP 2B device and the analysis of observed defect data on its interconnect, this paper examines: (i) the imp... View full abstract»

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  • A self-reconfiguration architecture for mesh arrays

    Publication Year: 1994, Page(s):212 - 220
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (364 KB)

    Recent advances in VLSI technology has stimulated research in massively parallel computers to satisfy the continuously increasing demand for computer power in advanced science and technology applications. Mesh-interconnection is one of the most attractive interconnections and architectures for massively parallel computers. This paper addresses a new reconfigurable architecture to implement massive... View full abstract»

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  • Scheduling policies for fault tolerance in a VLSI processor

    Publication Year: 1994, Page(s):1 - 9
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    This paper presents analytical and simulation models for evaluating the operation of a VLSI processor (in a uniprocessor configuration) which utilizes a time-redundant approach (such as recomputation by shifted operands) for fault-tolerant computing. In the proposed approach, all incoming jobs to the uniprocessor are duplicated, thus two versions of each job must be processed. A discrepancy in the... View full abstract»

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  • Reconfiguration in 3D meshes

    Publication Year: 1994, Page(s):194 - 202
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    The 1½ track model for fault tolerant 2D processor arrays is extended to 3D mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are considered. It is shown that when six directions in the 3D mesh are allowed for compensation paths, then switches with 13 states are needed to preserve the 3D mesh topology after faults. It is also shown that switch r... View full abstract»

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  • Reliability estimation for time redundant error correcting adders and multipliers

    Publication Year: 1994, Page(s):159 - 167
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (288 KB)

    There has been much study of concurrent error correction in arithmetic processors like adders and multipliers but they are not practical because of their high expense. The redundancy introduced to achieve fault-tolerance in a system can be in the form of either hardware, information, or time. The most straightforward method is to use hardware redundancy by triplicating the adder or multiplier and ... View full abstract»

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  • Using Fourier analyses to enhance IC testability

    Publication Year: 1994, Page(s):280 - 288
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    In this paper, we explore the potential of FFTs in digital IC tests. The effects of three parasite contact types are investigated. Results show that unappropriate logical values on output voltages are easily detected and that FFTs on supply current can make detectable undesired contacts causing additional delays. Application of the method to technologies with non small quiescent currents and to la... View full abstract»

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  • On fractal yield models: a statistical paradox

    Publication Year: 1994, Page(s):83 - 87
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    Although the fractal yield model is very successful in VLSI applications, it also exposes a mathematical inconsistency. Expressing the average number of faults in each sub array, the average number of faults in the complete array, according to this approach, is not statistically correct. This, therefore, is a fractal paradox View full abstract»

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  • Synthesis of multi-level self-checking logic

    Publication Year: 1994, Page(s):115 - 123
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    The problem of implementing self-checking combinational circuits is taken into account, with the initial requirement that self-checking capabilities be provided for otherwise optimized multilevel circuits produced by standard CAD tools, without affecting the circuit topology. The solution proposed involves a preliminary reduction of the number of inverters present in the circuit (it is assumed tha... View full abstract»

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