1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

8-10 Oct. 1997

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  • 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

    Publication Year: 1997
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    Freely Available from IEEE
  • The power of dynamic reconfiguration

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (42 KB)

    Summary form only given. Advances in semiconductor technology have led to many devices in which the computing devices can be configured as the computation proceeds. Field Programmable Gate Arrays is a typical commercially available configurable device. Such configurability offers several opportunities to speed-up computations. However, algorithmic innovations are needed to exploit such features to... View full abstract»

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  • Test strategy sensitivity to floating gate fault parameter

    Publication Year: 1997, Page(s):186 - 195
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (563 KB)

    This paper studies the detectability of floating gate faults considering static voltage, dynamic voltage and static current strategies. It is shown that the behavior of the defect depends on two classes of parameters: the predictable and unpredictable parameters (polysilicon-to-bulk capacitance). It is shown that a floating gate fault can induce abnormal logic values, additional delays or increase... View full abstract»

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  • Optical interconnects for commodity silicon technologies

    Publication Year: 1997, Page(s):201 - 202
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (130 KB)

    Summary form only given. The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. The development of such optoelectronic-VLSI technology and its compatibility with submicron CMOS technology, is discussed by the author. View full abstract»

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  • RF MEMS for digitally-controlled front-end components

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (61 KB)

    Summary form only given, as follows. In recent years the field of microelectromechanical systems (MEMS) has grown very fast and merged with many defense and commercial applications. Much of this activity has been driven by the ability of MEMS to miniaturize, reduce the cost, and improve the performance of transducers and actuators previously fabricated by hybrid techniques. These benefits have ste... View full abstract»

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  • Economics modeling of multichip systems testing strategies

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (54 KB)

    Summary form only given, as follows. To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply Design For Test (DFT) and Built-in Self Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to det... View full abstract»

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  • 1996 Innovative Systems In Silicon Conference - Index

    Publication Year: 1997, Page(s): 372
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    Freely Available from IEEE
  • Silicon micromachined gas chromatography system

    Publication Year: 1997, Page(s):117 - 125
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (780 KB)

    A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 μl sample loop; a 0.9-m long, rectangular-shaped (300 μm width and 10 μm height) capillary column coated with... View full abstract»

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  • A reconfigurable Markov chain simulator for analysis of parallel systems

    Publication Year: 1997, Page(s):107 - 116
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    Markov chain is a convenient tool to analyze parallel systems for architects who are not experts of theoretical analysis. However, it is sometimes difficult to use especially when the model becomes complicated or extremely small probabilities are used in the model. In this paper, we propose a reconfigurable Markov chain simulation system and evaluate on a reconfigurable testbed. In this system, a ... View full abstract»

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  • DSP architectures, algorithms, and code-generation: fission or fusion?

    Publication Year: 1997, Page(s):220 - 228
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (472 KB)

    Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x ... View full abstract»

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  • K-way partitioning under timing, pin, and area constraints

    Publication Year: 1997, Page(s):95 - 106
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (536 KB)

    Circuit partitioning is a very extensively studied problem. Our proposed methodology easily extends to multiple constraints that are very dominant in the design of large scale VLSI systems. In this paper we formulate the problem as a nonlinear program (NLP). The NLP is solved for the objective of minimum cutset size under the constraints of pins, area, and timing. We have tested the unified framew... View full abstract»

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  • High bit-rate 10 channel optical transmitter for sub-system interconnection

    Publication Year: 1997, Page(s):213 - 219
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (508 KB)

    Parallel optical interconnections allow for a substantial improvement in the capacity of systems associating an high bit-rate for each channel with a consistent reduction in the number of cables needed for interconnecting different system parts, such as boards or cabinets. We constructed a 10 channel parallel optical transmitter with 12.5 Gbit/s total bit-rate. The silicon CMOS (Complementary Meta... View full abstract»

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  • Electrical modeling and simulation for mixed-signal interconnect and packaging

    Publication Year: 1997, Page(s):82 - 94
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (744 KB)

    The explosive growth of wireless communications, combined with the rapid advances in high-performance portable computing, are driving the microelectronics industry toward the development of a variety of multi-functional, low-cost, compact, mixed-signal electronic products. These new products call for novel, often revolutionary, practices in functional block integration and packaging. Some of the c... View full abstract»

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  • Three-dimensional integration technology for real time micro-vision system

    Publication Year: 1997, Page(s):203 - 212
    Cited by:  Papers (13)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    It becomes possible to achieve the real time micro-vision system with extremely high image processing speed if three-dimensional LSI comes into reality because a higher level of parallel processing can be performed in three-dimensional LSI. Then, we have proposed a new three-dimensional integration technology for such real time micro-vision system with high image processing speed. Several key tech... View full abstract»

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  • A 16 GHz fast RISC engine using GaAs/AlGaAs and SiGe HBT technology

    Publication Year: 1997, Page(s):72 - 81
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (704 KB)

    Wafer Scale Hybrid Packages (WSHPs) or MultiChip Modules (MCMs) have provided a breakthrough in system packaging for high clock rate systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication. This design involved use of Heterojunction Bipolar Transistors (HBTs) in the GaAs/AlGaAs materials system. This pa... View full abstract»

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  • How to lay out arrays spared by rows and columns

    Publication Year: 1997, Page(s):30 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (632 KB)

    Perhaps the most common fault tolerant architecture configures a nominal t×at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t&ti... View full abstract»

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  • Architecture, defect tolerance, and buffer design for a new ATM switch

    Publication Year: 1997, Page(s):248 - 258
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (584 KB)

    This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, and the associated queueing, is distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fo... View full abstract»

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  • Clock cycle estimations for future microprocessor generations

    Publication Year: 1997, Page(s):61 - 71
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (568 KB)

    In the past 50 years, the semiconductor industry has experienced unprecedented growth. Identifying pivotal factors and technology trends in future generations will be key to understanding how we can maintain the historical growth and improve customer value. Processor performance will be one of the essential factors in this quest. This paper presents a high-level model of microprocessor clock-cycle... View full abstract»

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  • Architecture of a multiprocessor system with embedded DRAM for large area integration

    Publication Year: 1997, Page(s):274 - 281
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the process... View full abstract»

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  • Redundancy techniques for high-density DRAMs

    Publication Year: 1997, Page(s):22 - 29
    Cited by:  Papers (23)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (500 KB)

    This paper describes the redundancy techniques for high-density DRAMs to solve the following two problems which arise with the increase in memory capacity: (1) the increase in memory-array division reduces the replacement flexibility between defective lines and spare lines; (2) the defects causing DC-characteristics faults, especially excessive standby current faults cannot be repaired with the co... View full abstract»

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  • A scalar cost function for analyzing the quality of totally self-checking design methodologies

    Publication Year: 1997, Page(s):196 - 200, 200a, 200b
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (276 KB)

    This paper proposes a scalar cost function for analyzing the quality of Totally Self-Checking combinational devices; in particular the presented evaluator allows one to take into account other significant aspects affecting a TSC implementation rather than area overhead. The cost function is based on a measure which dynamically defines the probability to achieve the TSC goal at cycle t with respect... View full abstract»

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  • VLSI architecture for an advance DS/CDMA wireless communication receiver

    Publication Year: 1997, Page(s):237 - 247
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (496 KB)

    This paper presents an efficient VLSI Architecture for an advanced Direct Sequence CDMA Wireless Communication Receiver. Compensating for near/far effects is critical for the satisfactory performance of D/S CDMA systems. An effective approach to combat the near/far effect is multi-user detection. This approach has the potential of increasing the capacity by canceling co-channel interference. The r... View full abstract»

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  • The challenges in achieving sub-100 nm MOSFETs

    Publication Year: 1997, Page(s):52 - 60
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (576 KB)

    The continued scaling of the MOS transistor to smaller feature sizes has been the prime factor in the remarkable advancements in integrated circuits over the past 25-30 years. This is due to the fact that successively smaller devices have allowed continued rapid improvements in the level of integration and performance. While sub-100 nm MOSFETs have been built in the laboratory, it is by no means s... View full abstract»

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  • Comparative analysis of sensing schemes for multilevel non-volatile memories

    Publication Year: 1997, Page(s):266 - 273
    Cited by:  Papers (3)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (400 KB)

    Reading multilevel non-volatile memories is a very demanding task. Three sensing techniques (the parallel scheme, the binary-serial scheme and the mixed parallel-serial scheme) are considered here. Their operation principles are described and a comparative evaluation in terms of both access time and circuit complexity is carried out. The parallel approach is the most suitable for 4-level-cell memo... View full abstract»

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  • Efficient controller design for telescopic units

    Publication Year: 1997, Page(s):290 - 299
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (548 KB)

    Telescopic units represent an effective and innovative design option for increasing the average throughput of a combinational block. Throughput improvement is obtained at the price of a small reduction in average latency by allowing the unit to run with variable latency. Although this design paradigm has proved to be very effective, there are still some issues that need to be addressed before it c... View full abstract»

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