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Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on

Date 8-10 Oct. 1997

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  • 1997 Proceedings Second Annual IEEE International Conference on Innovative Systems in Silicon

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    Freely Available from IEEE
  • 1996 Innovative Systems In Silicon Conference - Index

    Page(s): 372
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    Freely Available from IEEE
  • RF MEMS for digitally-controlled front-end components

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    Summary form only given, as follows. In recent years the field of microelectromechanical systems (MEMS) has grown very fast and merged with many defense and commercial applications. Much of this activity has been driven by the ability of MEMS to miniaturize, reduce the cost, and improve the performance of transducers and actuators previously fabricated by hybrid techniques. These benefits have stemmed from the compatibility of MEMS with silicon-based microelectronics and surface micromachining. A recent development along these lines is RF MEMS which, broadly speaking, is a new class of passive devices (e.g., switches) and circuit components (e.g., tunable transmission lines) composed of or controlled by MEMS. The most investigated RF MEMS device has been the electrostatic switch, consisting of either a thin metallic cantilever, diaphragm, or some other form of membrane that when pulled down to a bottom electrode shorts or opens a high frequency transmission line. For example, working on the DARPA MAFET-3 Program, Texas Instruments has recently demonstrated a “BowTIe” switch having an on-state-insertion and return loss of 0.15 dB and -20 dB, respectively, at 20 GHz when fabricated across the center conductor of a coplanar waveguide. Other organizations in the DARPA Program are pursuing RF MEMS cantilevers for switchable antennas and filters (Hughes Research Labs), and quasioptical beam-steering grids (Rockwell and Northrop Grumman). In all of these applications, the RF MEMS is promising a major positive impact on performance and cost-a rare occurrence for any technology just entering the RF arena View full abstract»

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  • How to lay out arrays spared by rows and columns

    Page(s): 30 - 40
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    Perhaps the most common fault tolerant architecture configures a nominal t×at array using bt dedicated spare rows and ct dedicated spare columns. We counterexample an outstanding conjecture by constructively showing how dedicated sparing can be laid out in area proportional to the number of elements. However, we find that dedicated sparing is more costly than homogeneous extraction of a t×at array from a (1+b)t×(a+c)t array. i) In the presence of failures whose distribution is worst-case, iid, or clustered, the fault tolerance of either architecture is Θ(t-1). ii) At constant proportion of failures, the area of homogeneous arrays is Θ(exp t), while that of dedicated sparing is Ω(exp t). iii) The worst-case wirelength of either architecture is Θ(ct). iv) The best-case wirelength Θ(1) of homogeneous sparing is less than that Θ(t) of dedicated sparing. V) Probabilisticaily, homogeneous sparing has O(log t) wirelength, less than that Θ(t) of dedicated sparing. For large t, moreover, row-column sparing is more costly than local sparing View full abstract»

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  • Economics modeling of multichip systems testing strategies

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    Summary form only given, as follows. To produce high-quality and cost-effective multichip systems, they must be designed with test and fault diagnosis as critical design requirements. However, deciding on where and when to test, and whether to apply Design For Test (DFT) and Built-in Self Test (BIST) at the IC, multichip module (MCM) or board level requires considerable study and evaluation to determine the economics of the various solutions and the payback. In this paper we explore the tradeoffs between various test and rework strategies for multichip module designs. Some of these strategies incorporate various DFT options at both the MCM and IC levels. We analyze the impact of various cost, yield, and test effectiveness parameters on the final cost and quality of multichip modules. Experimental trade-off analysis data generated for some leading-edge multichip designs are also presented. The results clearly indicate that incorporating DFT and BIST with varying degrees at the chip or MCM levels is economically justifiable and results in cost reduction as well as quality improvement. The results also indicates that the MCM cost could vary by about 10-20% depending on the test strategy used. However, proper determination of where and how to test, and whether to employ DFT and BIST at the IC or MCM levels, requires an evaluation of the economics of the various solutions and the payback. That process is highly dependent on the design under consideration and the parameters associated with the available manufacturing environment(s) View full abstract»

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  • Redundancy techniques for high-density DRAMs

    Page(s): 22 - 29
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    This paper describes the redundancy techniques for high-density DRAMs to solve the following two problems which arise with the increase in memory capacity: (1) the increase in memory-array division reduces the replacement flexibility between defective lines and spare lines; (2) the defects causing DC-characteristics faults, especially excessive standby current faults cannot be repaired with the conventional redundancy techniques. First, two approaches to solve the first problem are discussed: enhancing the replacement flexibility within the limits of intra-subarray replacement, and the introduction of inter-subarray replacement. Next, the recent proposals to solve the second problem are reported. The DC-characteristics faults are repaired through the modification of bitline precharge circuit or the subarray-replacement redundancy View full abstract»

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  • Optical interconnects for commodity silicon technologies

    Page(s): 201 - 202
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    Summary form only given. The concept of a manufacturable technology that can provide parallel optical interconnects directly to a VLSI circuit now appears to be a reality. The development of such optoelectronic-VLSI technology and its compatibility with submicron CMOS technology, is discussed by the author View full abstract»

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  • The application of reconfigurable processors to MEMS calibration and signal processing in inertial navigation systems

    Page(s): 136 - 143
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    Advances in MEMS (micromechanical systems) and integrated circuits have made it feasible to further miniaturize smart sensor technology for inertial navigation systems. An element of smart sensor technology of particular interest is the use of reconfigurable logic, which is a method that can be employed to minimize the hardware needed to perform a variety of tasks concerned with sensor data reduction. Especially during subsystem development, using reconfigurable hardware facilitates rapid assessment and selection of different sensor instrumentation methods. Coordinate transformations and other computations involved in inertial navigation and GPS (global positioning system) data integration that can be performed with reconfigurable logic are described below. INS (inertial navigational system) and GPS readings are needed for future advances in terrestrial vehicle applications like geolocation and automatic target recognition. Preliminary experimental MEMS structures that are expected to be incorporated into accelerometer and other subsystem designs are also described below View full abstract»

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  • The microprocessor is no longer general purpose: why future reconfigurable platforms will win

    Page(s): 2 - 12
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    The paper is a proposal for a radical methodological change in R&D of dynamically reconfigurable circuits. The paper illustrates, that the current main stream approach based on placement and routing is not very likely to obtain the area-efficiency and throughput needed to cope with the emerging crisis cost of future silicon technology generations. The proposed changes include both: architectural principles and fundamental issues in application development support environments. The paper illustrates the feasibility of general purpose programmable accelerators and their commercialization. The paper highlights computer systems' increasing dependency on add-on accelerators. It shows, why only by a new methodology reconfigurable hardware will overcome its role as a niche technology and become competitive to ASICs and other hardwired accelerators. It illustrates the possible coming crisis of ASIC design based on wasting chip area by placement and routing and discusses the vision of software-only implementation of accelerators View full abstract»

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  • Three-dimensional integration technology for real time micro-vision system

    Page(s): 203 - 212
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    It becomes possible to achieve the real time micro-vision system with extremely high image processing speed if three-dimensional LSI comes into reality because a higher level of parallel processing can be performed in three-dimensional LSI. Then, we have proposed a new three-dimensional integration technology for such real time micro-vision system with high image processing speed. Several key technologies for three-dimensional integration such as formation of buried interconnection and micro-bump, wafer thinning, wafer alignment and wafer bonding have been developed View full abstract»

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  • Design and characterization of next-generation micromirrors fabricated in a four-level, planarized surface-micromachined polycrystalline silicon process

    Page(s): 144 - 154
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    This paper describes the design and characterization of several types of micromirror devices to include process capabilities, device modeling, and test data resulting in deflection versus applied potential curves. These micromirror devices are the first to be fabricated in the state-of-the-art four-level planarized polysilicon process available at Sandia National Laboratories known as the Sandia Ultra-planar Multi-level MEMS Technology (SUMMiT). This enabling process permits the development of micromirror devices with near-ideal characteristics which have previously been unrealizable in standard three-layer polysilicon processes. This paper describes such characteristics as elevated address electrodes, individual address wiring beneath the device, planarized mirror surfaces using Chemical Mechanical Polishing (CMP), unique post-process metallization, and the best active surface area to date. This paper presents the design, fabrication, modeling, and characterization of several variations of Flexure-Beam (FBMD) and Axial-Rotation Micromirror Devices (ARMD). The released devices are first metallized using a standard sputtering technique relying on metallization guards and masks that are fabricated next to the devices. Such guards are shown to enable the sharing of bond pads between numerous arrays of micromirrors in order to maximize the number of on-chip test arrays. The devices are modeled and then empirically characterized using a laser interferometer setup located at the Air Force Institute of Technology (AFIT) at Wright-Patterson AFB in Dayton, Ohio. Unique design considerations for these micromirror devices and the SUMMiT process are also discussed. The models are then compared with the empirical data to produce a complete characterization of the devices in a deflection versus applied potential curve View full abstract»

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  • Smartcards: portable security

    Page(s): 259 - 265
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    Smartcards are one of the fastest growing market segments in the field of microelectronics, since they offer an easy way to implement secure transactions. In this paper we will consider the main characteristics of smartcards, with special regard to the ones used for secure transactions, and discuss the main market and technology trends View full abstract»

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  • Programmable neural logic

    Page(s): 13 - 21
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    Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly analog process available from MOSIS. A long term goal of this research is to incorporate programmable threshold elements, as building blocks in Field Programmable Gate Arrays View full abstract»

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  • VLSI architecture for an advance DS/CDMA wireless communication receiver

    Page(s): 237 - 247
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    This paper presents an efficient VLSI Architecture for an advanced Direct Sequence CDMA Wireless Communication Receiver. Compensating for near/far effects is critical for the satisfactory performance of D/S CDMA systems. An effective approach to combat the near/far effect is multi-user detection. This approach has the potential of increasing the capacity by canceling co-channel interference. The receiver discussed here operates by successively canceling user interferences ranked in order of received power levels. The ranking is obtained from the (magnitude of) the correlations of user chip sequences with the received signal. We present an efficient VLSI architecture for its implementation. Further, we show that the performance of this receiver is vastly superior to the conventional receiver (without cancellation) View full abstract»

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  • High bit-rate 10 channel optical transmitter for sub-system interconnection

    Page(s): 213 - 219
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    Parallel optical interconnections allow for a substantial improvement in the capacity of systems associating an high bit-rate for each channel with a consistent reduction in the number of cables needed for interconnecting different system parts, such as boards or cabinets. We constructed a 10 channel parallel optical transmitter with 12.5 Gbit/s total bit-rate. The silicon CMOS (Complementary Metal Oxide Semiconductor) laser driver Integrated Circuit (IC), completely designed in CSELT, allows for low power consumption and low-cost even at the high bit-rate achieved with this device. The module as a metal package pigtailed with a 50/125 mm fibre ribbon with standard MPOTM/MTPTM push-pull multifibre connector. The laser array is a low threshold edge emitting Fabry-Perot commercial device with λ=1.3 μm, which makes it suitable for the fibres used in the telecom networks. During thorough lab tests the module has been operated up to 1.25 Gbit/s/ch with a good performance in terms of BER (Bit Error Ratio) characteristic, better than 1014, with a power budget of more than 10 dB and an overall power consumption of 1.3 W. The interconnection distance has been proven to be more than 500 m with a residual power margin of 4 dB with satisfactory BER figures View full abstract»

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  • A low power based partitioning and binding technique for single chip application specific DSP architectures

    Page(s): 350 - 361
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    In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given data flow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs View full abstract»

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  • Comparative analysis of sensing schemes for multilevel non-volatile memories

    Page(s): 266 - 273
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    Reading multilevel non-volatile memories is a very demanding task. Three sensing techniques (the parallel scheme, the binary-serial scheme and the mixed parallel-serial scheme) are considered here. Their operation principles are described and a comparative evaluation in terms of both access time and circuit complexity is carried out. The parallel approach is the most suitable for 4-level-cell memories (2 bit per cell). The mixed approach seems to be the most attractive for a large number of programmable levels (at least 16 levels per cell). In this case, the sensing area overhead is limited to less than 1% of the memory array while access time penalty is less than 50% View full abstract»

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  • A dual mode IEEE multiplier

    Page(s): 282 - 289
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    We present an IEEE floating-point multiplier capable of performing either a double-precision multiplication or a single-precision multiplication. In single-precision the latency is two clock cycles and in double-precision the latency is three clock cycles, where each pipeline stage contains roughly fifteen logic levels. A single-precision multiplication can be followed immediately by another multiplication of either single or double-precision, A double-precision multiplication requires one stall cycle, namely, two cycles after issuing a double-precision multiplication, a new multiplication of either precision can be issued. Therefore, the throughput in single-precision is one multiplication per clock cycle, and the throughput in double-precision is one multiplication per two clock cycles. Hardware cost is reduced by using only a half-sized multiplication array and by sharing the rounding circuitry for both precisions View full abstract»

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  • Silicon micromachined gas chromatography system

    Page(s): 117 - 125
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    A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 μl sample loop; a 0.9-m long, rectangular-shaped (300 μm width and 10 μm height) capillary column coated with a 0.2-μm thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-μm diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80°C). With a helium carrier gas and nitrogen diluent, a 10 μl sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8×105 Pa) can be separated in less than 30 minutes View full abstract»

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  • A parallel DSP testbed with a heterogeneous and reconfigurable network fabric

    Page(s): 310 - 322
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    A testbed for investigation of heterogeneous and reconfigurable data network fabrics supporting a parallel DSP computational accelerator is described. The DSP processors are large-grained processors (Analog Devices SHARC DSPs), with a variety of parallel DSP array architectures possible. The network fabric is intended to be reconfigurable (within a rich but necessarily limited set of structures) to adapt to the needs of a sequence of image processing algorithms being executed (e.g., in a medical image processing environment). The testbed will exploit conventional FPGA components to provide reconfigurable network structures and will exploit commercial high-speed interconnect components emerging for applications such as board-to-board applications. As a computational accelerator, the testbed is intended to be controlled by a host processor, with the host processor cooperating in the definition of the changes in the structure of the network structure as execution of a sequence of image processing algorithms proceeds View full abstract»

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  • DSP architectures, algorithms, and code-generation: fission or fusion?

    Page(s): 220 - 228
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    Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant advancements in code-generation technology. The TMS320C6x development program involved the codevelopment of the VelociTI architecture, a new code-generation environment, and a large set of representative benchmarks View full abstract»

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  • System-level power evaluation metrics

    Page(s): 323 - 330
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    High-level power estimation is a key issue for IC designers and system engineers. The goal is to widely explore the architectural design space and to compare alternative solutions, while maintaining an acceptable accuracy and a competitive design time. In this paper, an approach is proposed for evaluating the system-level power consumption of embedded systems implemented by using VLSI circuits. Accurate and efficient early power evaluation metrics have been defined to guide the system-level partitioning phase of a more general HW/SW co-design approach for control dominated embedded systems. The hardware and software contributions to the power consumption at the system-level have been considered as well as the contribution of the HW/SW communication View full abstract»

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  • Architecture, defect tolerance, and buffer design for a new ATM switch

    Page(s): 248 - 258
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    This paper presents a modular architecture for a scalable ATM-switch. The cell routing function, and the associated queueing, is distributed over many small clusters of nodes, called basic modules. These basic modules are hierarchically interconnected to form larger switches. In a basic module, every node is interconnected with adjacent nodes in the same module with three of its four links. The fourth link is used to connect either to external ports or to other basic modules at higher levels of the hierarchy. From a hardware implementation perspective, the simplicity of the architecture stems from the fact that each node in the switch consists of two small crossbar switches of low complexity and a buffer, plus a controller. The hierarchial nature of the topology allows for modular growth of the switch. Further, the interconnection topology of the switch makes it suitable for 3-D (stacked VLSI/WSI) implementation View full abstract»

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  • Microfluidic MEMS for semiconductor processing

    Page(s): 340 - 349
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    The advent of MEMS (microelectromechanical systems) will enable dramatic changes in MEMS-based devices offer opportunities to achieve higher with decreased size and increased reliability. In this work, we describe the achievement of several important devices for use in the semiconductor equipment industry. They include a low-flow mass flow controller, a high-precision pressure regulator, and an integrated gas panel. Compared to current technology, the devices are ultra-small in size, thus minimizing dead volumes and gas contact surface areas. With wettable surfaces comprised of ceramic and silicon (or, silicon coated with Si3N4 or SiC), they are resistant to corrosion, and generate virtually no particles. The devices are created from modular components. The science and technology of these components will be detailed. The modules examined are: normally-open proportional valves; normally-closed, low leak-rate shut-off valves; critical orifices (to extract information of flow rate); flow models (to extract flow rate from pressure and temperature information); silicon-based pressure sensors; and, the precision ceramic-based packages which integrate these modules into useful devices for semiconductor processing. The work finishes with a detailed description of the low-flow mass flow controller View full abstract»

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  • Architecture of a multiprocessor system with embedded DRAM for large area integration

    Page(s): 274 - 281
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    The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip View full abstract»

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