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Proceedings International Conference on Computer Design VLSI in Computers and Processors

12-15 Oct. 1997

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Displaying Results 1 - 25 of 107
  • Proceedings International Conference on Computer Design- VLSI in Computers and Processors [front matter]

    Publication Year: 1997, Page(s):iii - xiii
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    Freely Available from IEEE
  • Proceedings International Conference on Computer Design VLSI in Computers and Processors

    Publication Year: 1997
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    Freely Available from IEEE
  • Is wireless data dead?

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Summary form only given. In this presentation, we explore in greater detail the challenges faced by wireless data services, and some of the technology developments and possible solutions that lead us to be optimistic that wireless data is not yet dead, and in fact, has a very promising future. In particular, new spectrum allocations, coupled with integrated circuit technology breakthroughs, will e... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s):758 - 761
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    Freely Available from IEEE
  • Intelligent RAM (IRAM): the industrial setting, applications, and architectures

    Publication Year: 1997, Page(s):2 - 7
    Cited by:  Papers (21)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    The goal of intelligent RAM (IRAM) is to design a cost-effective computer by designing a processor in a memory fabrication process, instead of in a conventional logic fabrication process, and include memory on-chip. To design a processor in a DRAM process one must learn about the business and culture of the DRAMs, which is quite different from microprocessors. The authors describe some of those di... View full abstract»

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  • Effect of message length and processor speed on the performance of the bidirectional ring-based multiprocessor

    Publication Year: 1997, Page(s):267 - 272
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    This paper presents a comparative study of the performance of the bidirectional ring and the unidirectional ring multiprocessor, with emphasis on the effect of system parameters, specifically, the message length and the relative processor speed. The choice of these parameters may not be optimum due to the performance cost tradeoffs in practice. Our study shows that the use of bidirectional ring is... View full abstract»

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  • Estimation of maximum power for sequential circuits considering spurious transitions

    Publication Year: 1997, Page(s):746 - 751
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    With the high demand for reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maximum current, and hence, the maximum power, is NP-complete. Even for circuits with small num... View full abstract»

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  • BIST-based fault diagnosis in the presence of embedded memories

    Publication Year: 1997, Page(s):37 - 47
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1072 KB)

    An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previo... View full abstract»

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  • A comparative evaluation of hierarchical network architecture of the HP-Convex Exemplar

    Publication Year: 1997, Page(s):258 - 266
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1020 KB)

    The Convex Exemplar (SPP1000 and SPP2000 series) is a new commercial distributed shared-memory architecture. Using a set of system kernels and two application programs, we examine performance effects on network latency, hot spot contention, cache coherence and overall scaling capability, which result both from the choice of the network structure as well as from its CC-NUMA memory system feature. S... View full abstract»

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  • Divide and conquer: a strategy for synthesis of low power finite state machines

    Publication Year: 1997, Page(s):740 - 745
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    The authors propose a method to synthesize finite state machines (FSMs) for low power. The method consists of two stages-disjunctive partitioning and selective operation. In disjunctive partitioning, the state transitions of an FSM are judiciously partitioned such that all state transitions originating from a state are assigned to one partition. This partitioning can be directed by objectives such... View full abstract»

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  • Design and performance evaluation of a cache assist to implement selective caching

    Publication Year: 1997, Page(s):510 - 518
    Cited by:  Papers (9)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    Conventional cache architectures exploit locality, but do so rather blindly. By forcing all references through a single structure, the cache's effectiveness on many references is reduced. This paper presents a cache assist namely the annex cache which implements a selective caching scheme. Except for filling a main cache at cold start, all entries come to the cache via the annex cache. Items refer... View full abstract»

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  • Formally specifying and mechanically verifying programs for the Motorola complex arithmetic processor DSP

    Publication Year: 1997, Page(s):31 - 36
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    We describe our formal specification of Motorola's Complex Arithmetic Processor (CAP) DSP and our subsequent use of this specification to verify the correctness of several DSP algorithms. We wrote the specification in the ACL2 logic and carried out the mechanical proofs using the ACL2 theorem-proving system. Motorola's CAP is a super-scalar, pipelined DSP with seven memories and more than 20 funct... View full abstract»

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  • An evaluation of asynchronous and synchronous design for superscalar architectures

    Publication Year: 1997, Page(s):295 - 300
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    The high performance of superscalar architectures is obtained through the simultaneous execution of several machine operations upon multiple functional units. Traditional synchronous design techniques restrict the operation of these functional units to worst-case performance within discrete globally determined periods of time. However, asynchronous design techniques do not suffer from these restri... View full abstract»

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  • A 400 MHz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor

    Publication Year: 1997, Page(s):253 - 255
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    A high performance 2 K×72 CMOS ROM for fetching most frequently used complex instruction code in a high speed S/390-class microprocessor is described in this paper. The ROM has a nominal access/cycle time performance of 2.3 ns/2.5 ns and is physically organized as 128 word lines by 1152 bit lines. Personalization is done at the gate level of the device. The technology used was the IBM CMOS6S... View full abstract»

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  • PA-8000: a case study of static and dynamic branch prediction

    Publication Year: 1997, Page(s):97 - 105
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    While many dynamic branch prediction schemes have been proposed and studied, few have been compared to static branch prediction. Fewer yet have been implemented side-by-side on the same machine to allow full performance evaluation. The Hewlett-Packard PA-8000 microprocessor implements both a simple dynamic prediction scheme and static prediction, selectable by the application programmer. This pape... View full abstract»

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  • Critical voltage transition logic: an ultrafast CMOS logic family

    Publication Year: 1997, Page(s):732 - 737
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    The authors present a new kind of CMOS logic circuit that has a different structure and different operation mechanism compared to the existing logic circuits. Its unique delay propagation characteristic makes it much faster than the conventional CMOS logic gate. Gate outputs are preconditioned to a voltage level between Vdd and Vss using a new clocking scheme and circuit desi... View full abstract»

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  • A TSC evaluation function for combinational circuits

    Publication Year: 1997, Page(s):555 - 560
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (896 KB)

    The paper presents an innovative evaluation function for circuits with on-line detecting properties, which considers other aspects beyond area overhead. In particular, this function takes into account the probability of detecting a fault, once it occurs, with respect to the network structure and the application of input configurations. Different implementations of the same device designed to have ... View full abstract»

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  • Multi-column implementations for cache associativity

    Publication Year: 1997, Page(s):504 - 509
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    We propose two schemes for implementing higher associativity: the sequential multi-column cache, which is an extension of the column associative cache, and the parallel multi-column cache. In order to achieve the same access cycle time as that of a direct-mapped cache, data memory in the cache is organized into one bank in both schemes. We use the multiple MRU block technique to increase the first... View full abstract»

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  • Intertwined development and formal verification of a 60× bus model

    Publication Year: 1997, Page(s):25 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (668 KB)

    We describe a project in which the IBM/Motorola 60× bus protocol was incrementally modeled at an abstract level in Verilog and verified using Motorola's Verdict model checker. The primary purpose of the modeling activity was to acquaint verification personnel with details of the 60× bus protocol and to document specific properties of the 60× bus that are necessary to guarantee co... View full abstract»

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  • TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model

    Publication Year: 1997, Page(s):288 - 294
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design... View full abstract»

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  • Optimal clock period clustering for sequential circuits with retiming

    Publication Year: 1997, Page(s):122 - 127
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (644 KB)

    We consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing the flip-flops (FFs) and clustering the remaining combinational logic. This approach segments a circuit and assumes the positions... View full abstract»

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  • Transistor-level sizing and timing verification of domino circuits in the Power PCTM microprocessor

    Publication Year: 1997, Page(s):143 - 148
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1176 KB)

    This paper describes a tool called Focus that is currently being used for the timing verification and siting of domino CMOS circuits in a Power PCTM microprocessor. Domino CMOS circuits introduce more complex timing and sizing requirements compared to conventional static circuits. This paper shows how these requirements are addressed in Focus. Some case studies involving the application... View full abstract»

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  • High performance CMOS circuit techniques for the G-4 S/390 microprocessor

    Publication Year: 1997, Page(s):247 - 252
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    This paper describes the CMOS circuit techniques used in the design of the high performance Generation-4 S/390 microprocessor. Successful system operation at frequencies up to 400 MHz was achieved through careful static circuit design and timing optimization, along with the limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle t... View full abstract»

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  • Design and test: The Lost World

    Publication Year: 1997
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    In the film The Lost World released in the summer of 1997, based on the 1995 Michael Crichton novel, scientists speculate about whether remote areas exist, far from human view, where dinosaurs survived and prospered, in spite of their apparent extinction and replacement by other life forms. Is the same true in design and test today? Are there places unknown to us where practices are those of a byg... View full abstract»

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  • Design optimization for high-speed per-address two-level branch predictors

    Publication Year: 1997, Page(s):88 - 96
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1108 KB)

    Per-address two-level branch predictors have been shown to be among the best predictors and have been implemented in current microprocessors. However, as the cycle time of modern microprocessors continues to decrease, the implementation of set-associative per-address two-level branch predictors will become more difficult. Instead, direct-mapped designs may be more attractive. In this paper, we inv... View full abstract»

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