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Design and Diagnostics of Electronic Circuits & Systems, 2009. DDECS '09. 12th International Symposium on

Date 15-17 April 2009

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  • [Front and back covers]

    Publication Year: 2009, Page(s):c1 - c4
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  • [Title page]

    Publication Year: 2009, Page(s): i
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  • [Copyright notice]

    Publication Year: 2009, Page(s): ii
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  • Foreword to the 12th IEEE DDECS symposium

    Publication Year: 2009, Page(s): iii
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  • Symposium Committees

    Publication Year: 2009, Page(s): iv
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  • Table of contents

    Publication Year: 2009, Page(s):v - ix
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  • Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS

    Publication Year: 2009, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (79 KB)

    With the advanced scaling of CMOS technology in the nanometer range, highly integrated mixed-signal systems can be designed. The use of nanometer CMOS, however, poses many challenges. This keynote presentation gives an overview of problems due to increased variability and reliability. Both have to be addressed by the designer, either at IC design time or through reconfiguration at IC run time. Des... View full abstract»

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  • Cognitive self-adaptive computing and communication systems: Test, control and adaptation

    Publication Year: 2009, Page(s): 2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (81 KB)

    CMOS technology scaling along with the resulting large variability of circuit performance has made post-silicon circuit and algorithmic level built-in test and adaptation/tuning almost a necessity for deeply scaled technologies. Currently, circuits are designed to tolerate worst-case process corners. In addition, circuits as well as demodulation/signal processing algorithms must be designed for wo... View full abstract»

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  • Challenges for test and design for test

    Publication Year: 2009, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    If test is mentioned normally there are several remarks that have been repeated for the last 20 years. ICs are too fast, patterns are too big, testing is too slow, the test development too costly. Although, the advance of the technology has improved test in general, these statements seems to prevail and sound still valid. One reason is that on every improvement of test strategies there is also imp... View full abstract»

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  • An SOC platform for ADC test and measurement

    Publication Year: 2009, Page(s):4 - 7
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operat... View full abstract»

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  • A scheme of logic self repair including local interconnects

    Publication Year: 2009, Page(s):8 - 11
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (233 KB) | HTML iconHTML

    Technology forecasts concerning the development of CMOS technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in t... View full abstract»

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  • Investigating the linearity of MOSFET-only switched-capacitor ΔΣ modulators under low-voltage condition

    Publication Year: 2009, Page(s):12 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB) | HTML iconHTML

    Effect of asymmetric operating condition of depletion-mode MOS capacitors on the linearity of MOSFET-only switched-capacitor DeltaSigma modulators is investigated. In very low-voltage switched-capacitor circuits the opamp input and output common-mode levels are separated to provide maximum overdrive voltage for MOS switches. This causes an asymmetric voltage drop on capacitors during operation. On... View full abstract»

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  • Comparison of different test strategies on a mixed-signal circuit

    Publication Year: 2009, Page(s):16 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (200 KB) | HTML iconHTML

    An experiment comparing the efficiency of different test strategies on a moderate complexity mixed-signal circuit with 1300 nodes is presented. Selected test strategies from the groups of functional, structural and parametric approaches were considered. Bridging faults are taken into account and fault simulations results are shown, where fault coverage, efficiency and quality of the tests are eval... View full abstract»

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  • Case Study : A class E power amplifier for ISO-14443A

    Publication Year: 2009, Page(s):20 - 23
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (276 KB) | HTML iconHTML

    This paper reports on the design and implementation of a class E push-pull amplifier in order to increase the reading range of an ISO-14443A RFID system. With the aid of classical design formulas and some alterations due to parasitic and intrinsic capacitances, a working implementation was made that can provide the loop with an amplified modulated current wave. View full abstract»

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  • Fast congestion-aware timing-driven placement for island FPGA

    Publication Year: 2009, Page(s):24 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (258 KB) | HTML iconHTML

    A new fast timing-driven placement is presented in this paper, which is partitioning-based method, explicitly considering the congestion for island style FPGAs. The most distinct feature of this approach is that it not only reduces the circuit critical path delay efficiently, but also takes congestion into account. The harmony between partitioning objective and timing improvement goal is kept; mor... View full abstract»

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  • Analysis and optimization of ring oscillator using sub-feedback scheme

    Publication Year: 2009, Page(s):28 - 29
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (329 KB) | HTML iconHTML

    This work proposes a topology using a ring oscillator with sub-feedback loops to generate multiple phases. It is composed of an N-stage main ring (arbitrary N larger than 3) and k-stage sub-feedback loops, where k is not the common divisor of N, N output phases can be obtained. With a linear model analysis, it comes to a result that oscillating frequency is related to k, and the phase difference b... View full abstract»

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  • Improve clock gating through power-optimal enable function selection

    Publication Year: 2009, Page(s):30 - 33
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be r... View full abstract»

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  • An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions

    Publication Year: 2009, Page(s):34 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (334 KB) | HTML iconHTML

    The paper deals with the problems of input variables assigning to the free and bounded sets during logic function decomposition. The Ashenhurst decomposition is considered with respect to implementation of logic functions in LUT based FPGA. The method of finding profitable input variables partitioning is based on utilisation of Logic Differential Calculus. The elaborated method is very convenient ... View full abstract»

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  • A fast untestability proof for SAT-based ATPG

    Publication Year: 2009, Page(s):38 - 43
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (323 KB) | HTML iconHTML

    Automatic Test Pattern Generation (ATPG) based on Boolean satisfiability (SAT) has been shown to be a beneficial complement to traditional ATPG techniques. SAT solvers work on instances given in Conjunctive Normal Form (CNF). The required transformation of the ATPG problem into CNF is one main part of SAT-based ATPG and needs a significant portion of the overall run time. Solving the SAT instance ... View full abstract»

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  • The impact of EFSM composition on functional ATPG

    Publication Year: 2009, Page(s):44 - 49
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (354 KB) | HTML iconHTML

    The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influenced by the computational model adopted to represent the design under test. In this context the extended finite state machine (EFSM) is a valuable model which reduces the risk of state explosion preserving relevant features of more traditional FSMs. This paper. defines a particular variant of EFSMs ... View full abstract»

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  • An efficient fault simulation technique for transition faults in non-scan sequential circuits

    Publication Year: 2009, Page(s):50 - 55
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault sim... View full abstract»

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  • Self-timed full adder designs based on hybrid input encoding

    Publication Year: 2009, Page(s):56 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (305 KB) | HTML iconHTML

    Self-timed full adder designs based on commercial synchronous resources (standard cells), constructed using a mix of complete delay-insensitive codes adopted for inputs are described in this paper. While one of the adder designs incorporates redundancy into the logic, the other design does not. Comparisons have been carried out with respect to various self-timed full adder designs which employ onl... View full abstract»

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  • Optimization concepts for self-healing asynchronous circuits

    Publication Year: 2009, Page(s):62 - 67
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB) | HTML iconHTML

    Decreasing feature size and lower supply voltage cause integrated circuits to be more error-prone, during production as well as during runtime. At the same time the demand for higher reliability is increasing. In particular for applications with long mission times and where no repair is possible, complex fault tolerance mechanisms are required, leading to a dramatic increase of design and system c... View full abstract»

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  • Asynchronous two-level logic of reduced cost

    Publication Year: 2009, Page(s):68 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (281 KB) | HTML iconHTML

    We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed t... View full abstract»

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  • Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS

    Publication Year: 2009, Page(s):74 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (359 KB) | HTML iconHTML

    An innovative design with simulation results of a low-voltage bulk driven mixer for direct conversion receiver is presented. The circuit is designed in a 65 nm digital CMOS process without analog extensions. It offers a conversion gain of 22 dB at a clock frequency of 1.5 GHz for GALILEO/GPS applications. The design is capable of operating at up to 7 GHz with only 3 dB gain decrease. The simulated... View full abstract»

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