By Topic

Signal Processing Systems, 1997. SIPS 97 - Design and Implementation., 1997 IEEE Workshop on

Date 5-5 Nov. 1997

Filter Results

Displaying Results 1 - 25 of 56
  • 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (430 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s):551 - 552
    Request permission for commercial reuse | PDF file iconPDF (55 KB)
    Freely Available from IEEE
  • Aggressive dynamic execution of decoded traces

    Publication Year: 1997, Page(s):253 - 262
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We consider the increased performance that can be obtained by using in concert, three previously proposed (and in two cases used in commercial systems) ideas. These ideas are aggressive dynamic (run time) instruction scheduling, reuse of decoded instructions, and trace scheduling. We show that these ideas complement and support one another. Hence, while each of these ideas has been shown to have m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new cost-effective morphological filter chip

    Publication Year: 1997, Page(s):421 - 430
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The paper proposes a new VLSI architecture for morphological filters and presents its design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architectures by using a feedback loop path to reuse partial results and a decoder/encoder pair comparator to detect minimum/maximum values. In addition, the proposed architecture requires one commo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient multiplierless FIR filter chip with variable-length taps

    Publication Year: 1997, Page(s):412 - 420
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The paper proposes a novel VLSI architecture for a multiplierless FIR filter chip providing variable length taps. To change the number of taps, we propose two special features called a data reuse structure and a recurrent coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient code generation for digital signal processors with parallel and pipelined instructions

    Publication Year: 1997, Page(s):243 - 252
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules, mostly due to the limitation of the processor's internal structures, must be observed to achieve the full performance. These include the proper selection of operand data types, efficient usage of data and address registers, and novel instruction sch... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Pipelined Cordic based QRD-RLS adaptive filtering using matrix lookahead

    Publication Year: 1997, Page(s):131 - 140
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper, the matrix lookahead transformation is developed to achieve fine-grain pipelining for Cordic based QRD-RLS adaptive filtering algorithm. Various implementation styles are proposed. They include pipelining, block processing, and incremental block processing. The proposed architectures can operate at arbitrarily high sample rates, and consist of only Givens and a few Gaussian rotation... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Radix-differential 2D FIR filters

    Publication Year: 1997, Page(s):405 - 411
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    An approach to the realisation of 2D FIR filters based on a novel radix differential arithmetic is introduced. The differential algorithm is accomplished by coding the input video signal more efficiently using a DPCM coding system. Whereas the filter's coefficients are fed in digit serial fashion and specified using radix-2" arithmetic. The proposed approach provides a spectrum of architectures to... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new pipelined architecture for allpass digital filters based on the 3-port adaptor

    Publication Year: 1997, Page(s):431 - 437
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Allpass digital filters are major building blocks in many digital filter structures. A new pipelined architecture for the 2nd order allpass section based on the 3-port series adaptor is presented. It is shown how to maximise the sample rate whilst applying the minimum level of pipelining. The new architecture has up to double the maximum sample rate of other structures View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast VLSI binary addition

    Publication Year: 1997, Page(s):232 - 241
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Algebraic mapping network (AlMa-Net)

    Publication Year: 1997, Page(s):121 - 130
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper, the concept of Algebraic Mapping Network is introduced which will allow, for the first time, the inclusion of information about “when and where” within mathematical equations. This explicit mathematical description has the same structure as “implicit” mathematics and is used to map algebraic expressions into a Time-Space map. The main merit of AlMa-Net is tha... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • System-level power exploration for MPEG-2 decoder on embedded cores: a systematic approach

    Publication Year: 1997, Page(s):395 - 404
    Cited by:  Papers (10)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    The paper describes the impact of our system level data transfer and storage exploration methodology-as proposed in our mbox-ATOMIUM approach-in a software development context on embedded processors. The effectiveness of this methodology on power reduction is demonstrated by optimizing a public domain MPEG-2 video decoder program for an embedded processor. The result is an average factor 3.7 gaine... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Taurus: a multiprocessor DSP prototyping environment

    Publication Year: 1997, Page(s):263 - 272
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Many signal processing applications are computationally intensive, and cannot be implemented on a single processor. The concept of automatic parallel implementation of such applications on multiple connected processors has attracted attention in recent years. We present a new design environment, Taurus, which allows for automatic parallel mapping of DSP algorithms and applications onto multiproces... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementing area-time efficient VLSI residue to binary converters

    Publication Year: 1997, Page(s):163 - 172
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper, the authors present highly area-time efficient VLSI implementations of residue reverse converters called Compressed Multiply ACcumulate (CMAC) converters. The efficiency results from identifying and eliminating redundancy in previously reported designs. Specifically, the partial sum. Generation and addition are merged into a single carry save addition operation. Also, module multipl... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient Reed-Solomon decoder VLSI with erasure correction

    Publication Year: 1997, Page(s):193 - 201
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new architecture for implementing a Reed-Solomon error correction VLSI that utilizes the erasure information is developed. To reduce the number of arithmetic elements, we employed a serial expansion of the polynomials for the modified syndrome calculation, and used an overclocking scheme for fast internal operations. The Chien's search algorithm is also modified to find the errors in the same or... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware realization of a Java virtual machine for high performance multimedia applications

    Publication Year: 1997, Page(s):479 - 488
    Cited by:  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding proce... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Non-sequential processing: bridging the semantic gap left by the von Neumann architecture

    Publication Year: 1997, Page(s):35 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be described to demonstrate how to overcome this gap. A more radical solution will then be described which no longer defines programming as a procedure that operates on data, but as a specif... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Configurable structures for a primitive operator digital filter FPGA

    Publication Year: 1997, Page(s):532 - 540
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A number of configurable arithmetic structures for an FPGA architecture for the realisation of low complexity digital filters are investigated. The FPGA is based upon primitive operator design technique in which digital filters are realised using signal flow graphs comprising low complexity operations. The authors evaluate the structures with a number of filter examples and compare their performan... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A media processor for multimedia signal processing applications

    Publication Year: 1997, Page(s):86 - 96
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A multimedia system requires processing capabilities that include controlling functions as well as high throughput. For the consumer market, this processor must also satisfy low cost constraints. An efficient solution is the use of a dual-issue RISC architecture with key enhancements to target the high computation needs of multimedia applications. The RISC design methodology ensures its ease of pr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multithreaded systolic/SIMD DSP array processor-MUS2DAP

    Publication Year: 1997, Page(s):448 - 457
    Cited by:  Papers (2)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    This paper deals with architectural design of the systolic/SIMD DSP processing array called MUS2DAP optimized for the execution of DSP filtering, vector/matrix and linear algebra algorithms. Its main features are architectural support for multithreading, interprocessor communication based on virtual channels and exploitation of instruction level parallelism within each processing cell of the array... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new generation of parameterized and extensible DSP cores

    Publication Year: 1997, Page(s):320 - 329
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Traditional DSP cores based on off-the-shelf processors do not provide any possibilities to configure the core itself. This has been addressed by licensable, customizable cores. This paper introduces a new generation of parameterized and extensible DSP cores. The VS-DSP core features can be tailored to the application by changing the parameters. Furthermore, there are several extension mechanisms ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Compact inverse discrete cosine transform circuit for MPEG video decoding

    Publication Year: 1997, Page(s):364 - 373
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The discrete cosine transform (DCT) and its inverse transform (IDCT) are essential computations in many signal processing applications. IDCT, specifically, is used to decompress MPEG video bitstreams and, therefore, needs to be computed inside cost-sensitive end-user units. This paper presents a very compact IDCT design based on digit-serial arithmetic techniques and the even/odd decomposition alg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power architecture for phase-splitting passband equalizer

    Publication Year: 1997, Page(s):385 - 394
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    A low power architecture for phase splitting passband equalizer (PSPE) is proposed. Carrierless AM/PM (CAP) transmission scheme, which is a standard for numerous broadband communication systems including ATM-LAN networks, employs PSPE at the receiving end to combat channel distortion and crosstalk. The conventional PSPE requires two independent adaptive filters that form the in-phase and the quadr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Topological synthesis of clock trees for VLSI-based DSP systems

    Publication Year: 1997, Page(s):151 - 162
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper considers the problem of designing the topology of a clock distribution network for a synchronous digital signal processor so as to satisfy a non-zero clock skew schedule. A methodology and related algorithms for synthesizing the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of des... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel variable length decoding with inverse quantization for software MPEG-2 decoders

    Publication Year: 1997, Page(s):500 - 509
    Cited by:  Papers (9)  |  Patents (82)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Fast methods of variable length decoding (VLD) and inverse quantization (IQ) are proposed for software MPEG-2 video decoders. In these methods, microprocessors with SIMD type instructions execute VLD and IQ efficiently. The use of memory-efficient tables enables decoding multiple variable length codewords concurrently. In addition, the concurrently decoded data are inversely quantized in parallel ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.