1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

5-5 Nov. 1997

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  • 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (430 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s):551 - 552
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    Freely Available from IEEE
  • A programmable VLC core architecture for video compression DSP

    Publication Year: 1997, Page(s):469 - 478
    Cited by:  Papers (12)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A programmable Variable-Length Coder/decoder, “VLC core”, is developed for various video compression algorithms and standards. This paper describes the programmable architecture that allows the coding and the decoding process to be performed by the same logical units on a small chip. This VLC core is the first coder and decoder which shares the table memory, the barrel shifter and the ... View full abstract»

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  • Hardware realization of a Java virtual machine for high performance multimedia applications

    Publication Year: 1997, Page(s):479 - 488
    Cited by:  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding proce... View full abstract»

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  • Fast VLSI binary addition

    Publication Year: 1997, Page(s):232 - 241
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where... View full abstract»

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  • Implementation of the 2D DCT using a Xilinx XC6264 FPGA

    Publication Year: 1997, Page(s):541 - 550
    Cited by:  Papers (11)  |  Patents (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    This paper presents a novel FPGA implementation of a two dimensional (8×8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implement... View full abstract»

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  • A new pipelined architecture for allpass digital filters based on the 3-port adaptor

    Publication Year: 1997, Page(s):431 - 437
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Allpass digital filters are major building blocks in many digital filter structures. A new pipelined architecture for the 2nd order allpass section based on the 3-port series adaptor is presented. It is shown how to maximise the sample rate whilst applying the minimum level of pipelining. The new architecture has up to double the maximum sample rate of other structures View full abstract»

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  • A block processing unit in a single-chip MPEG-2 video encoder LSI

    Publication Year: 1997, Page(s):459 - 468
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-mult... View full abstract»

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  • Design and implementation of a complex multiplier using distributed arithmetic

    Publication Year: 1997, Page(s):222 - 231
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, m... View full abstract»

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  • Configurable structures for a primitive operator digital filter FPGA

    Publication Year: 1997, Page(s):532 - 540
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A number of configurable arithmetic structures for an FPGA architecture for the realisation of low complexity digital filters are investigated. The FPGA is based upon primitive operator design technique in which digital filters are realised using signal flow graphs comprising low complexity operations. The authors evaluate the structures with a number of filter examples and compare their performan... View full abstract»

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  • Design and implementation of a FPGA sigma-delta power DAC

    Publication Year: 1997, Page(s):511 - 521
    Cited by:  Papers (4)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    In this paper we discuss the design and implementation of a FPGA power DAC for digital audio applications. The paper concentrates on the sigma-delta modulator, which is used to convert an oversampled PCM input signal into a 1-bit code suitable for controlling a power switch. The design of the bit-flipping architecture used to reduce the pulse-repetition frequency of the output is discussed, togeth... View full abstract»

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  • DSP architectures, algorithms, and code-generation: fission or fusion?

    Publication Year: 1997, Page(s):50 - 59
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    Continuing dramatic improvements in semiconductor manufacturing processes are enabling radical new signal-processing architectures at the chip level. But how do we ensure that the radical becomes practical? The development of these new architectures must be coupled, a fusion, with clearly defined target applications, a thorough analysis of applicable signal processing algorithms, and significant a... View full abstract»

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  • VLSI design of DLMS adaptive IIR filters for high speed echo cancellation

    Publication Year: 1997, Page(s):341 - 350
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    In this paper we present a novel VLSI design of adaptive IIR filters for high speed channel echo cancellation. In the algorithm level, the delayed LMS adaptation algorithm is adopted to exploit the computing concurrency between the adaptation and the filtering sections. In addition, the non-recursive equation error criterion is employed to speed up the computation in the adaptation section. In the... View full abstract»

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  • An efficient Reed-Solomon decoder VLSI with erasure correction

    Publication Year: 1997, Page(s):193 - 201
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    A new architecture for implementing a Reed-Solomon error correction VLSI that utilizes the erasure information is developed. To reduce the number of arithmetic elements, we employed a serial expansion of the polynomials for the modified syndrome calculation, and used an overclocking scheme for fast internal operations. The Chien's search algorithm is also modified to find the errors in the same or... View full abstract»

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  • A media processor for multimedia signal processing applications

    Publication Year: 1997, Page(s):86 - 96
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A multimedia system requires processing capabilities that include controlling functions as well as high throughput. For the consumer market, this processor must also satisfy low cost constraints. An efficient solution is the use of a dual-issue RISC architecture with key enhancements to target the high computation needs of multimedia applications. The RISC design methodology ensures its ease of pr... View full abstract»

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  • The system implementation of I-phone hardware by using low bit rate speech coding

    Publication Year: 1997, Page(s):489 - 499
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    This paper presents a system implementation for Internet-phone communication with real-time speech coding schemes. A low-cost speech processing coprocessor is embedded. A CPLD device is used to implement the interface between the host processor and the coprocessor via conventional parallel port. At the headphone interface, there are a 16-bits PCM CODEC and an audio amplifier with acoustic echo can... View full abstract»

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  • Beamforming performance of a randomly distributed sensor array system

    Publication Year: 1997, Page(s):438 - 447
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We consider a digital signal processing sensor array system based on randomly distributed sensor nodes for intrusion and surveillance applications. The nodes having acoustical, seismic, and other sensors are self organized into a synchronized network using low powered spread spectrum transceivers. Beamforming array techniques for enhanced detection and estimation and performances under various ide... View full abstract»

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  • Optimising designs for hardware compilation to FPGAs

    Publication Year: 1997, Page(s):522 - 531
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    Field programmable gate arrays with their re-configurable architectures are a powerful tool for implementing re-configurable computing. Using the facility of re-programmability, designs can be optimised for specific cases and then implemented in hardware, achieving performance improvements over the software design. As the physical architecture itself places size and speed constraints on the design... View full abstract»

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  • Merged arithmetic revisited

    Publication Year: 1997, Page(s):212 - 221
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Alternative structures of merged arithmetic are examined for implementing the inner product function. Merged arithmetic dissolves the boundaries between multiplication and addition by synthesizing the entire function directly rather than decomposing the function into discrete multiplies and adds. Fully merged arithmetic eliminates these boundaries completely. A partially merged arithmetic is intro... View full abstract»

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  • On core and more: a design perspective for system-on-chip

    Publication Year: 1997, Page(s):60 - 63
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    This paper focuses on a main domain for core based DSP systems. In wireless applications it is an indispensable requirement to optimally utilize computational power and on-chip memory. It is well known that to achieve this goal, DSPs are almost exclusively programmed in assembly, due to the poor efficiency of the existing compilers. In view of the required drastic increase of the designer's produc... View full abstract»

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  • Generalised triangular basis multipliers for the design of Reed-Solomon codecs

    Publication Year: 1997, Page(s):202 - 211
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In this paper a generalised definition of a triangular basis for GF(2m) is presented. This definition is more flexible than the traditional definition and allows a number of triangular bases to be determined to any given basis. The triangular basis to the polynomial basis can then be used which has the simplest basis transformation in modified Hasan-Bhargava multipliers. It is shown tha... View full abstract»

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  • Parallel variable length decoding with inverse quantization for software MPEG-2 decoders

    Publication Year: 1997, Page(s):500 - 509
    Cited by:  Papers (9)  |  Patents (87)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Fast methods of variable length decoding (VLD) and inverse quantization (IQ) are proposed for software MPEG-2 video decoders. In these methods, microprocessors with SIMD type instructions execute VLD and IQ efficiently. The use of memory-efficient tables enables decoding multiple variable length codewords concurrently. In addition, the concurrently decoded data are inversely quantized in parallel ... View full abstract»

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  • Synthesisable FFT cores

    Publication Year: 1997, Page(s):351 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% process... View full abstract»

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  • Non-sequential processing: bridging the semantic gap left by the von Neumann architecture

    Publication Year: 1997, Page(s):35 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    Parallel processing has proven to be easy to implement in hardware but difficult to deliver because of the software problems. First, the distributed semantics in the Virtuoso RTOS, based on the CSP model, will be described to demonstrate how to overcome this gap. A more radical solution will then be described which no longer defines programming as a procedure that operates on data, but as a specif... View full abstract»

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  • Multimedia extensions for general-purpose processors

    Publication Year: 1997, Page(s):9 - 23
    Cited by:  Papers (46)  |  Patents (57)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (792 KB)

    This paper gives an overview of the multimedia instructions that have been added to the instruction set architectures of general-purpose microprocessors to accelerate media processing. Examples are MAX, MMX and VIS, the multimedia extensions for PA-RISC, ix86, and SPARC processor architectures. We describe subword parallelism, a low overhead form of SIMD parallelism, and the classes of instruction... View full abstract»

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