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1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

5-5 Nov. 1997

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  • 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing

    Publication Year: 1997
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    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s):551 - 552
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    Freely Available from IEEE
  • Aggressive dynamic execution of decoded traces

    Publication Year: 1997, Page(s):253 - 262
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We consider the increased performance that can be obtained by using in concert, three previously proposed (and in two cases used in commercial systems) ideas. These ideas are aggressive dynamic (run time) instruction scheduling, reuse of decoded instructions, and trace scheduling. We show that these ideas complement and support one another. Hence, while each of these ideas has been shown to have m... View full abstract»

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  • Optimal wordlength determination of AC-3 decoding hardware based on fixed-point analysis and simulations of AC-3 algorithm

    Publication Year: 1997, Page(s):301 - 310
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    In this paper, we perform a fixed-point analysis for Dolby AC-3 audio decoding algorithm, and determine the suitable multiplier wordlength (say, N) satisfying the required sound quality. After that, based on the similar simulations, we try to reduce the accumulator wordlength from the usual (8+ 2N) to (g+N+r) where g is the wordlength for overflow guard bits and r is the wordlength for rounding wi... View full abstract»

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  • A block processing unit in a single-chip MPEG-2 video encoder LSI

    Publication Year: 1997, Page(s):459 - 468
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-mult... View full abstract»

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  • Implementation strategy of MPEG-2 audio decoder and efficient multichannel architecture

    Publication Year: 1997, Page(s):293 - 300
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The paper describes an MPEG-2 audio decoder applied in multichannel extension. In the analysis of intelligent implementation strategy, the decoder can be divided into two hardware-oriented architecture stages. Also, an efficient architecture for multichannel processor is presented. The decoder is developed for the approach for simplicity and low-cost design View full abstract»

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  • VLSI design of DLMS adaptive IIR filters for high speed echo cancellation

    Publication Year: 1997, Page(s):341 - 350
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    In this paper we present a novel VLSI design of adaptive IIR filters for high speed channel echo cancellation. In the algorithm level, the delayed LMS adaptation algorithm is adopted to exploit the computing concurrency between the adaptation and the filtering sections. In addition, the non-recursive equation error criterion is employed to speed up the computation in the adaptation section. In the... View full abstract»

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  • Visual representation of the speech trace on a real time platform

    Publication Year: 1997, Page(s):283 - 292
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    Through the present paper a methodology to adapt a set of algorithms and techniques derived from the field of adaptive signal processing on a real time platform, based on a specific digital signal processing board is presented. An overview of the algorithms implemented is followed by a brief presentation of the low-cost hardware platform developed, based on the TMS320C31, interfacing with a host P... View full abstract»

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  • Pipelined Cordic based QRD-RLS adaptive filtering using matrix lookahead

    Publication Year: 1997, Page(s):131 - 140
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    In this paper, the matrix lookahead transformation is developed to achieve fine-grain pipelining for Cordic based QRD-RLS adaptive filtering algorithm. Various implementation styles are proposed. They include pipelining, block processing, and incremental block processing. The proposed architectures can operate at arbitrarily high sample rates, and consist of only Givens and a few Gaussian rotation... View full abstract»

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  • On core and more: a design perspective for system-on-chip

    Publication Year: 1997, Page(s):60 - 63
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    This paper focuses on a main domain for core based DSP systems. In wireless applications it is an indispensable requirement to optimally utilize computational power and on-chip memory. It is well known that to achieve this goal, DSPs are almost exclusively programmed in assembly, due to the poor efficiency of the existing compilers. In view of the required drastic increase of the designer's produc... View full abstract»

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  • Efficient code generation for digital signal processors with parallel and pipelined instructions

    Publication Year: 1997, Page(s):243 - 252
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Modern digital signal processors are capable of performing multiple pipelined instructions concurrently. However, strict and complicated coding rules, mostly due to the limitation of the processor's internal structures, must be observed to achieve the full performance. These include the proper selection of operand data types, efficient usage of data and address registers, and novel instruction sch... View full abstract»

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  • The system implementation of I-phone hardware by using low bit rate speech coding

    Publication Year: 1997, Page(s):489 - 499
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    This paper presents a system implementation for Internet-phone communication with real-time speech coding schemes. A low-cost speech processing coprocessor is embedded. A CPLD device is used to implement the interface between the host processor and the coprocessor via conventional parallel port. At the headphone interface, there are a 16-bits PCM CODEC and an audio amplifier with acoustic echo can... View full abstract»

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  • Merged arithmetic revisited

    Publication Year: 1997, Page(s):212 - 221
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    Alternative structures of merged arithmetic are examined for implementing the inner product function. Merged arithmetic dissolves the boundaries between multiplication and addition by synthesizing the entire function directly rather than decomposing the function into discrete multiplies and adds. Fully merged arithmetic eliminates these boundaries completely. A partially merged arithmetic is intro... View full abstract»

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  • A co-design methodology for telecommunication systems: a case study of an acoustic echo canceller

    Publication Year: 1997, Page(s):273 - 282
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Acoustic echo cancellation with large adaptive filters is a computationally intensive problem and needs a real time cost effective solution. To deal with these challenges, designers have increasingly turned to mixed hardware/software (HW/SW) implementation of echo canceller algorithms. We present a co-design methodology and environment for both hardware and software modules. We describe how high l... View full abstract»

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  • High-radix CORDIC algorithms for VLSI signal processing

    Publication Year: 1997, Page(s):183 - 192
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    This paper presents high-radix CORDIC algorithms for high-speed sine and cosine computation. Since the CORDIC calculation takes O(n) steps for evaluating a function in n-bit precision, significant reduction of processing latency is required for real-time signal processing applications. In this paper, we present a unified approach to low-latency CORDIC implementation based on high-radix algorithms,... View full abstract»

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  • Algebraic mapping network (AlMa-Net)

    Publication Year: 1997, Page(s):121 - 130
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    In this paper, the concept of Algebraic Mapping Network is introduced which will allow, for the first time, the inclusion of information about “when and where” within mathematical equations. This explicit mathematical description has the same structure as “implicit” mathematics and is used to map algebraic expressions into a Time-Space map. The main merit of AlMa-Net is tha... View full abstract»

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  • Fast VLSI binary addition

    Publication Year: 1997, Page(s):232 - 241
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wtfa to Wtmux where... View full abstract»

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  • An efficient multiplierless FIR filter chip with variable-length taps

    Publication Year: 1997, Page(s):412 - 420
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The paper proposes a novel VLSI architecture for a multiplierless FIR filter chip providing variable length taps. To change the number of taps, we propose two special features called a data reuse structure and a recurrent coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and... View full abstract»

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  • Beamforming performance of a randomly distributed sensor array system

    Publication Year: 1997, Page(s):438 - 447
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    We consider a digital signal processing sensor array system based on randomly distributed sensor nodes for intrusion and surveillance applications. The nodes having acoustical, seismic, and other sensors are self organized into a synchronized network using low powered spread spectrum transceivers. Beamforming array techniques for enhanced detection and estimation and performances under various ide... View full abstract»

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  • Topological synthesis of clock trees for VLSI-based DSP systems

    Publication Year: 1997, Page(s):151 - 162
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    This paper considers the problem of designing the topology of a clock distribution network for a synchronous digital signal processor so as to satisfy a non-zero clock skew schedule. A methodology and related algorithms for synthesizing the topology of the clock distribution network from a clock schedule derived from circuit timing information are presented. A new formulation of the problem of des... View full abstract»

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  • Synthesisable FFT cores

    Publication Year: 1997, Page(s):351 - 363
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    Methods are presented for developing synthesisable FFT cores. These are based on a modular approach in which parameterisable blocks are cascaded to implement the computations required across a range of typical FFT signal flow graphs. The underlying architectural approach combines the use of a digital serial data organisation with generic commutator blocks to produce systems that offer 100% process... View full abstract»

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  • Compact inverse discrete cosine transform circuit for MPEG video decoding

    Publication Year: 1997, Page(s):364 - 373
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The discrete cosine transform (DCT) and its inverse transform (IDCT) are essential computations in many signal processing applications. IDCT, specifically, is used to decompress MPEG video bitstreams and, therefore, needs to be computed inside cost-sensitive end-user units. This paper presents a very compact IDCT design based on digit-serial arithmetic techniques and the even/odd decomposition alg... View full abstract»

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  • Hearing music [human peripheral hearing system]

    Publication Year: 1997, Page(s):330 - 339
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1152 KB)

    Traditional spectrography commonly found in speech sciences laboratories, makes use of fixed bandwidth bandpass analysis filters. The bandwidth can be adjusted to optimise between time and frequency resolution of the output spectrogram as desired. Acoustic analysis by the human ear can be modelled as a bank of bandpass filters whose bandwidth varies as a function of centre frequency. We describe a... View full abstract»

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  • On-line architecture for the S.Mallat algorithm

    Publication Year: 1997, Page(s):173 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Wavelets have been a research matter in a variety of fields since they were created. They are developed in mathematics, algorithmic, architectures and physical applications. The S.MALLAT algorithm has been implemented in many ways and in different architectures by several research groups. In this paper we shall present an architecture for a circuit of reduced area, little cost and high speed, whic... View full abstract»

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  • Heterogeneous reconfigurable systems

    Publication Year: 1997, Page(s):24 - 34
    Cited by:  Papers (11)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (908 KB)

    The continually increasing integration density of integrated circuits portrays important paradigm shifts in next-generation designs, especially in the direction of systems-on-a-chip. Hybrid architectures mixing a variety of computational models are bound to be integrated on a single die. This opens the door for creative high-performance low-energy solutions to the programming problem using techniq... View full abstract»

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