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VLSI Test Symposium, 1991. 'Chip-to-System Test Concerns for the 90's', Digest of Papers

Date 15-17 April 1991

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Displaying Results 1 - 25 of 53
  • Using target faults to achieve a minimized partial scan path

    Publication Year: 1991 , Page(s): 4 - 9
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (458 KB)  

    Today the most often applied DFT-strategy is full scan path. To reduce its overhead a partial scan path can be selected. For minimizing the size of the partial scan path existing testpatterns are used which will detect a part of the faults. Only the remaining faults, so called target faults, have to be addressed using partial scan. Different methods are given to adapt a partial scan path to the target faults. They do not depend on ATPG and therefore have very short runtimes. Results on sequential ATPG-benchmarks show that a strong reduction in the size of the partial scan path is possible. Also the combination of the structural selection and the selection with respect to target faults is proposed. First results prove its effectiveness.<> View full abstract»

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  • A design-for-testability expert system for silicon compilers

    Publication Year: 1991 , Page(s): 10 - 15
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (474 KB)  

    This paper describes a design-for-testability expert system for the selection of the most appropriate test method for every macro within an IC. The interface with the system designer is user-friendly and together with an efficient search mechanism this expert system can be used as a framework for all types of macros. This tool will be used in a self-test compiler, which generates the layout of self-testable macros automatically. The self-test compiler can be part of a silicon compilation system and thus contribute to the integration of testability into the design process.<> View full abstract»

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  • Use of CrossCheck test technology in practical applications

    Publication Year: 1991 , Page(s): 16 - 21
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (346 KB)  

    The CrossCheck technique is beginning to gain acceptance as an effective low-cost solution to the ASIC testability problem. The technique provides massive observability by embedding test circuitry into the ASIC device. This allows highly accurate defect modeling and simulation with less computational resources than conventional techniques. This paper describes CrossCheck test technology and present results on its application to real-life designs. All these designs are sequential in nature with multiple, gated and asynchronous clocks. Bridging, comprehensive (opens and shorts) as well as conventional stuck-at I/O fault coverage, and CPU time and memory requirements are presented.<> View full abstract»

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  • Recent progress in synthesis for testability

    Publication Year: 1991 , Page(s): 22 - 29
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (882 KB)  

    Describes recent work involving the automatic synthesis of VLSI circuits with testability considerations. The first put of this paper explores the potential for logic synthesis to allow designers to more comprehensively test circuits while simultaneously diminishing the need for fault simulation and automatic test pattern generation. Logic optimization procedures can be used to produce circuits that are completely testable for single stuck-at faults. Testing for faults such as multiple stuck-at faults, gate delay faults and path delay faults is a greater challenge, but logic synthesis and optimization procedures can produce circuits that have high degrees of testability under these models as well. For each of these fault models test vectors can be produced as a by-product of the synthesis process and vector minimization algorithms can be used in the place of fault simulation to reduce the size of the test vector sets. The second part of the paper considers the difficult problem of synthesizing sequential circuits with high degrees of single stuck-at fault coverage without incurring the area and performance penalty of scan registers. Initial results at combining synthesis for testability approaches with register-transfer level automatic test-pattern generation to produce vector sets that give complete single stuck-at fault coverage without the use of scan.<> View full abstract»

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  • Power-down integrated circuit built-in self-test structures

    Publication Year: 1991 , Page(s): 30 - 33
    Cited by:  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB)  

    Built-in self-test structures composed of logic elements are isolated from the host circuitry by means of separate Test VDD, so that it appears as an open circuit during normal operation of the IC. The separate Test VDD is employed to re-configure the host circuit and operate the test circuitry in the test mode. When Test VDD is removed, the test circuit powers down and disconnects from the host becoming invisible to the normal operation of the IC.<> View full abstract»

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  • A partitioning method for achieving maximal test concurrency in pseudo-exhaustive testing

    Publication Year: 1991 , Page(s): 34 - 39
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB)  

    Pseudo-exhaustive testing of combinational circuits usually requires multiple test sessions and/or more than a minimum number of test signals, i.e. unique input sequences. This paper presents a methodology for partitioning combinational circuits such that they can be pseudo-exhaustively tested with a minimal number of test signals in a single test session. Circuits are logically partitioned during test mode and unrelated inputs are combined to achieve maximal test concurrency.<> View full abstract»

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  • Identification of structured automata for test evaluation

    Publication Year: 1991 , Page(s): 40 - 46
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB)  

    Presents an original approach to the evaluation of test sequences applied to sequential circuits represented by structured-functional models; the method is based on formal identification of the internal modules of the circuit studied. A prototype software tool has been implemented in PROLOG in order to validate the approach.<> View full abstract»

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  • Compact testing with intermediate signature analysis

    Publication Year: 1991 , Page(s): 47 - 52
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (383 KB)  

    Among a number of techniques for efficiently testing VLSI circuits, the BIST using compression technique is recognized as reliable and cost effective. While compact testing using signature analysis allows an efficient test, some faulty responses cannot be detected due to aliasing. This paper shows how the aliasing probability can be significantly reduced by a factor of 2/sup (k+1)/ when k intermediate signatures are checked. The proposed scheme can also quickly detect the fault using fewer hardware resources.<> View full abstract»

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  • An analysis of feedback bridging faults in MOS VLSI

    Publication Year: 1991 , Page(s): 53 - 58
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (335 KB)  

    The feedback bridging faults are examined in detail for MOS digital circuits. A necessary condition is obtained which needs to be satisfied for oscillations in the circuit. Expression are given to predict the frequency and amplitude of oscillations. It is shown that when a feedback bridging fault does not cause oscillations, it creates an anomalous output. Such faults may not be detected by logic testing: the authors recommend measurement of power supply current to detect such faults in CMOS circuit.<> View full abstract»

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  • Linear microcircuit fault modeling and detection

    Publication Year: 1991 , Page(s): 59 - 61
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (187 KB)  

    Classical discrimination analysis and neural network techniques are used to detect and classify possible faults in linear microcircuits. The success rates of simulated fault detection and classification are described for various types of analog and mixed-mode circuits.<> View full abstract»

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  • Fault modeling and testing of self-timed circuits

    Publication Year: 1991 , Page(s): 62 - 66
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    The problems of synchronizing communication and clock distribution to various circuit parts has led to interest in self-timed circuits, particularly in ASIC signal processing designs. Self-timed circuits employ computational components which generate completion signals to indicate that their data are available for use by other circuit components. Therefore, other circuit components wait for completion signals rather than clock signals. One of the drawbacks of self-timed circuits is that they are difficult to test because they are asynchronous. This paper is concerned with a class of self-timed systems because each logic components generate its completion signals automatically. This paper studies the behaviour of DCVSL logic in the presence of physical faults. Based on this behaviour, the authors present a switch-level test generation algorithm for DCVSL circuits. Finally, they present a scan approach suitable for self-timed systems.<> View full abstract»

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  • Probabilistic measures of fault equivalence in mixed-signal systems

    Publication Year: 1991 , Page(s): 67 - 70
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (306 KB)  

    A study of fault equivalence in mixed analogue-digital circuits and systems is presented, emphasizing both the theoretical analysis of the equivalence concept as well as experimental results from three classes of circuits: sample-and-hold, digital-to-analog converter, and analog-to-digital converter. While fault equivalence is well understood in digital fault models, the concept is still quite new for analog fault models. The concept is also valid within the context of mixed-signal fault models, but the equivalence has to be defined in the frequency domain and in some cases, has to be approached from a probabilistic perspective. The experimental results include fault effects due to the classic digital stuck-at-fault models as well as analog faults such as out-of-specification performance, nonlinearity, etc. For each class of circuit, extensive simulation is conducted to study the fault behavior and experimental measurements are carried out to verify these behaviors as well as to confirm the validity of equivalence definition. The major application of this study is in test generation and fault diagnosis, similar to the application of digital equivalent faults in defining test vectors for equivalence classes.<> View full abstract»

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  • The advantages of boundary-scan testing

    Publication Year: 1991 , Page(s): 71 - 77
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (513 KB)  

    Boundary scan has been used extensively by IBM in custom logic, standard cell, and gate array logic chips. Actual implementations of boundary-scan methods used in testing these chips are discussed. The benefits of this approach are reviewed, and an economic analysis of the cost savings attributable to boundary scan are presented.<> View full abstract»

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  • Combining IEEE Standard 1149.1 with reduced-pin-count component test

    Publication Year: 1991 , Page(s): 78 - 84
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (440 KB)  

    This paper describes a boundary-scan structure that permits comprehensive testing of level-sensitive-scan design (LSSD) components with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic testing equipment (ATE). Furthermore, the structure conforms to IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture, which simplifies testing of assembled printed-circuit boards or other multi-component substrates.<> View full abstract»

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  • Interconnect verification of multichip modules using boundary scan

    Publication Year: 1991 , Page(s): 85 - 91
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    Certainly one of the key factors in the manufacture of multichip modules (MCM) is the verification and fault diagnosis of an MCM's structural interconnects. High performance MCM products, which are clearly an expensive technology, will incur additional costs unless appropriate diagnostic tools are made available for fast failure analysis during production test. Boundary scan implementation is key in making these tools feasible.<> View full abstract»

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  • Issues of integrating the IEEE Std 1149.1 into a gate array

    Publication Year: 1991 , Page(s): 92 - 97
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    Use of boundary-scan to test systems at the production and field levels has taken on a greater importance due to the development of surface mount technology. The IEEE Standard 1149.1 offers a documented approach to the implementation of boundary-scan. United Technologies Microelectronics Center (UTMC) integrated the standard into an ASIC gate array; this paper presents that implementation and addresses issues arising from the integration not covered specifically in the standard.<> View full abstract»

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  • Specifications for the development of an expert tool for the automatic optical understanding of electronic circuits: VLSI reverse engineering

    Publication Year: 1991 , Page(s): 98 - 103
    Cited by:  Papers (2)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    Deals with the specifications for the development of an expert tool for the automatic optical detection and recognition of the connectivity among devices in digital electronic circuits and the understanding of the circuits functionality. In particular, the proposed tool, called ANTISTROFEAS, uses expert knowledge recognizing and understanding electronic circuits without the use of their associated database. The ANTISTROFEAS tool will use classical picture processing methods in combination with heuristics and knowledge acquisition schemes. The expert tool proposed is used for understanding of 'unknown' electronic circuits, or where the complexity of the circuit is too great, so that any human searching effort requires long time for reliable results.<> View full abstract»

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  • Statistical sensitivity simulation for integrating design and testing of MOSFET integrated circuits

    Publication Year: 1991 , Page(s): 104 - 108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A computer-aided design tool for testing MOSFET integrated circuit performance as functions of MOSFET channel length and channel width variations is presented. The numerical model, which is developed based on the Tellegen's theorem and a database that contains the statistical information of MOSFET process parameters, is implemented in SPICE2 circuit simulator. Sensitivity simulation of a MOSFET operational amplifier is carried out to illustrate the usefulness of the present work.<> View full abstract»

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  • Aspects on integration of high-speed multiplexers and demultiplexers in VLSI test systems

    Publication Year: 1991 , Page(s): 128 - 133
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (467 KB)  

    The authors describe hardware and software solutions for the design of a high-speed tester channel. Using gallium-arsenide circuitry for the merging of tester pin waveforms, cycle periods of less than 1 ns have been achieved. Hardware design alternatives are discussed, and a scheme for the automatic generation of tester-readable pattern description files is introduced. The conversion algorithms that allow for this generation are described.<> View full abstract»

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  • VLSI procurement and qualification: NASA/GSFC experience, issues and concerns

    Publication Year: 1991 , Page(s): 109 - 113
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Describes the VLSI parts quality and reliability issued for NASA space flight use, particularly from a NASA/Goddard Space Flight Center (GSFC) perspective. A case history of four chip set gate arrays planned for use on a high speed flight data recorder, qualification effort based on MIL-M-38510 requirements, is discussed.<> View full abstract»

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  • High accelerated lifetime test methods and procedures for VLSI microcircuit interconnection line certification

    Publication Year: 1991 , Page(s): 114 - 117
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB)  

    As an outcome of the advances in integrated circuit fabrication technology, electromigration has become a major reliability concern in silicon VLSI circuits. This paper represents an innovative testing approach, that allows a substantial reduction in the electromigration test times of metal thin films, and can be implemented as an in-line process electromigration monitor.<> View full abstract»

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  • A multilayered ceramic (MLC) interface design for 125+MHz performance wafer probing (of SRAMs)

    Publication Year: 1991 , Page(s): 118 - 122
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (354 KB)  

    A design is presented using a multilayered ceramic (MLC) substrate as the basis for the wafer-tester interface. A 27*27 matrix of pads on 225 mu m centers is contacted; this design replaces a hand-wire interface between the wafer probe and tester performance board. Significant reductions in signal crosstalk and power supply noise are realized.<> View full abstract»

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  • An adaptive device impedance matching circuit

    Publication Year: 1991 , Page(s): 123 - 127
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB)  

    Test engineers have been frustrated in their efforts to perform accurate functional testing of high speed VLSI devices on commercial ATE because of the impedance mismatch between the device and the ATE pin electronics. This mismatch between the low device output impedance and high ATE test station impedance causes signal reflections ('ringing') that interfere with testing. This paper will describe a circuit that effectively eliminates the problem of signal reflections. In contrast to earlier proposed solutions, this circuit is simple to understand and use.<> View full abstract»

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  • A software system architecture for testing multiple part number wafers

    Publication Year: 1991 , Page(s): 134 - 136
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (205 KB)  

    Testing single part number wafers is the normal mode of testing semiconductor devices in the industry today. However, as wafers get larger it may become more economical to put different devices on the same wafer resulting in multiple part number wafers. The authors describe a system architecture that allows for the testing of such wafers.<> View full abstract»

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  • An analysis and testing of operation induced faults in MOS VLSI

    Publication Year: 1991 , Page(s): 137 - 142
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (430 KB)  

    The operation induced faults in CMOS circuits are discussed. The significance of these faults for high density, small geometry circuits is pointed out. For modeling purposes the effects of these faults are correlated with classical fault models. A conductance fault model is presented to incorporate these faults. A test scheme to detect these faults is suggested which is based on the measurement of supply current. A scheme to generate test patterns for these faults is also outlined.<> View full abstract»

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