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Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Date 16-18 April 1997

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  • Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

    Publication Year: 1997
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1997, Page(s):249 - 250
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    Freely Available from IEEE
  • The swappable logic unit: a paradigm for virtual hardware

    Publication Year: 1997, Page(s):77 - 86
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SL... View full abstract»

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  • Mapping a real-time video algorithm to a context-switched FPGA

    Publication Year: 1997, Page(s):236 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    This paper describes the implementation of a real-time video algorithm on a context-switched FPGA. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. The algorithm makes use of special features of this architecture to achieve high utilization of the silicon at run... View full abstract»

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  • Garp: a MIPS processor with a reconfigurable coprocessor

    Publication Year: 1997, Page(s):12 - 21
    Cited by:  Papers (229)  |  Patents (182)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an... View full abstract»

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  • An FPGA architecture for DRAM-based systolic computations

    Publication Year: 1997, Page(s):2 - 11
    Cited by:  Papers (6)  |  Patents (57)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (980 KB)

    We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serve. Wide data paths within the chip are time multiplexed at the edge of the chip into much faster and narrower data paths that run off-chip. This kind of arrangement makes it possible to interface a relatively slow FPGA co... View full abstract»

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  • A dynamic reconfiguration run-time system

    Publication Year: 1997, Page(s):66 - 75
    Cited by:  Papers (24)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1008 KB)

    The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case studies. However, these systems have typically involved an ad hoc combination of hardware and software. The software that manages the dynamic reconfiguration is typically specialised to one application and one hardware configuration. We present three different applications of dynamic reconfiguration... View full abstract»

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  • Datapath-oriented FPGA mapping and placement for configurable computing

    Publication Year: 1997, Page(s):234 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Widespread acceptance of FPGA-based reconfigurable coprocessors will be expedited if compilation time for FPGA configurations can be reduced to be comparable to software compilation. This research achieves this goal, generating complete datapath layouts in fractions of a second rather than hours. Our algorithm, adapted from instruction selection in compilers, packs multiple operations into single ... View full abstract»

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  • A time-multiplexed FPGA

    Publication Year: 1997, Page(s):22 - 28
    Cited by:  Papers (146)  |  Patents (97)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory ... View full abstract»

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  • Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware

    Publication Year: 1997, Page(s):219 - 225
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    Reed-Solomon (RS) error correction codes are being widely used in modern communication systems such as compact disk players or satellite communication links. RS codes rely on arithmetic in finite, or Galois fields. The specific field GF(28) is of central importance for many practical systems. The most costly, and thus most critical, elementary operations in RS decoders are multiplicatio... View full abstract»

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  • The RAW benchmark suite: computation structures for general purpose computing

    Publication Year: 1997, Page(s):134 - 143
    Cited by:  Papers (23)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to expr... View full abstract»

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  • Acceleration of an FPGA router

    Publication Year: 1997, Page(s):175 - 181
    Cited by:  Papers (7)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors describe their experience and progress in accelerating an FPGA router. Placement and routing is undoubtedly the most time-consuming process in automatic chip design or configuring programmable logic devices as reconfigurable computing elements. Their goal is to accelerate routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration. Coarse-grain parall... View full abstract»

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  • Laser defect correction applications to FPGA based custom computers

    Publication Year: 1997, Page(s):240 - 241
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The complexity and speed of monolithic FPGA based custom computers has been set by the presence of defective sections which limit chip area. Test FPGAs show that laser link defect avoidance routing around flawed blocks generates delays <50% of active switches, making the error cell distribution nearly invisible View full abstract»

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  • Fault simulation on reconfigurable hardware

    Publication Year: 1997, Page(s):182 - 190
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The authors introduce a new approach to fault simulation, using reconfigurable hardware to implement a critical path tracing algorithm. The performance estimate shows that the approach is at least on order of magnitude faster than serial fault emulation used in prior work View full abstract»

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  • Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing

    Publication Year: 1997, Page(s):211 - 217
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The need to partition computation across multiple programmable devices in array architecture CCMs leads to performance bottlenecks in data flow through the computer and wiring delays between adjacent devices. However, significant improvements in FPGA capacities have brought one to a threshold where direct inter-chip connections are not required because an entire algorithm can be implemented on a s... View full abstract»

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  • Systems performance measurement on PCI Pamette

    Publication Year: 1997, Page(s):125 - 133
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    We describe the use of a reconfigurable board to obtain information on the performance that can be expected on particular systems. Our goal is to use the reconfigurability, of the board's interface to test a system and discover not only the maximum bandwidth and best latency attainable, but also the way to reliably achieve these figures. The board we present uses the now widespread PCI bus. PCI is... View full abstract»

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  • Automated target recognition on SPLASH 2

    Publication Year: 1997, Page(s):192 - 200
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Automated target recognition is an application area that requires special-purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high level of performance for ATR systems if the implementation can be adapted to the limited FPGA and routing resources of these architectures. The paper discusses a mapping experiment where a linear-systolic implementation of an ATR algo... View full abstract»

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  • The Chimaera reconfigurable functional unit

    Publication Year: 1997, Page(s):87 - 96
    Cited by:  Papers (73)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-op... View full abstract»

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  • Compilation tools for run-time reconfigurable designs

    Publication Year: 1997, Page(s):56 - 65
    Cited by:  Papers (28)  |  Patents (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process, known as compile-time sequencing; an incremental configuration calculator, which takes the output of the p... View full abstract»

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  • A parallel hardware evolvable computer POLYP

    Publication Year: 1997, Page(s):238 - 239
    Cited by:  Papers (1)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    Previous work (J.S. McCaskill et al., 1996; 1997) has shown the power of massively parallel configurable hardware (NGEN) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom circuit simulation of fine grained physical processes via a massively parallel architecture, e.g. 144 hardware configurable field programm... View full abstract»

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  • Mapping applications to the RaPiD configurable architecture

    Publication Year: 1997, Page(s):106 - 115
    Cited by:  Papers (32)  |  Patents (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (944 KB)

    The goal of the RaPiD (Reconfigurable Pipelined Datapath) architecture is to provide high performance configurable computing for a range of computationally-intensive applications that demand special-purpose hardware. This is accomplished by mapping the computation into a deep pipeline using a configurable array of coarse-grained computational units. A key feature of RaPiD is the combination of sta... View full abstract»

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  • On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

    Publication Year: 1997, Page(s):246 - 247
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    We summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA based reconfigurable application specific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algo... View full abstract»

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  • Speech recognition HMM training on reconfigurable parallel processor

    Publication Year: 1997, Page(s):242 - 243
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    Armstrong III is a 20 node multi-computer that is currently operational. In addition to a RISC processor, each node contains reconfigurable resources implemented with FPGAs. The in-circuit reprogramability of static RAM based FPGAs allows the computational capabilities of a node to be dynamically matched to the computational requirements of an application. Most reconfigurable computers in existenc... View full abstract»

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  • Implementation of single precision floating point square root on FPGAs

    Publication Year: 1997, Page(s):226 - 232
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtracter. The operation latency is 25 clock cycle... View full abstract»

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  • High level compilation for fine grained FPGAs

    Publication Year: 1997, Page(s):165 - 173
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors present an integrated tool set to generate highly optimized hardware computation blocks from a C language subset. By starting with a C language description of the algorithm, they address the problem of making FPGA processors accessible to programmers as opposed to hardware designers. Their work is specifically targeted to fine grained FPGAs such as the National Semiconductor CLAyT... View full abstract»

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