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Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

16-18 April 1997

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  • Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)

    Publication Year: 1997
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    Freely Available from IEEE
  • Index of authors

    Publication Year: 1997, Page(s):249 - 250
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    Freely Available from IEEE
  • The Chimaera reconfigurable functional unit

    Publication Year: 1997, Page(s):87 - 96
    Cited by:  Papers (88)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (916 KB)

    By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we describe Chimaera, a system that overcomes this bottleneck by integrating reconfigurable logic into the host processor itself with direct access to the host processor's register file, the system enables the creation of multi-op... View full abstract»

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  • Real-time stereo vision on the PARTS reconfigurable computer

    Publication Year: 1997, Page(s):201 - 210
    Cited by:  Papers (63)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    The paper describes a powerful, scalable, reconfigurable computer called the PARTS engine. The PARTS engine consists of 16 Xilinx 4025 FPGAs, and 16 one-megabyte SRAMs. The FPGAs are connected in a partial torus-each associated with two adjacent SRAMs. The SRAMs are tightly coupled to the FPGAs so that all the SRAMs can be accessed concurrently. The PARTS engine fits on a standard PCI card in a pe... View full abstract»

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  • Systems performance measurement on PCI Pamette

    Publication Year: 1997, Page(s):125 - 133
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    We describe the use of a reconfigurable board to obtain information on the performance that can be expected on particular systems. Our goal is to use the reconfigurability, of the board's interface to test a system and discover not only the maximum bandwidth and best latency attainable, but also the way to reliably achieve these figures. The board we present uses the now widespread PCI bus. PCI is... View full abstract»

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  • Datapath-oriented FPGA mapping and placement for configurable computing

    Publication Year: 1997, Page(s):234 - 235
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    Widespread acceptance of FPGA-based reconfigurable coprocessors will be expedited if compilation time for FPGA configurations can be reduced to be comparable to software compilation. This research achieves this goal, generating complete datapath layouts in fractions of a second rather than hours. Our algorithm, adapted from instruction selection in compilers, packs multiple operations into single ... View full abstract»

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  • A time-multiplexed FPGA

    Publication Year: 1997, Page(s):22 - 28
    Cited by:  Papers (176)  |  Patents (99)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper describes the architecture of a time-multiplexed FPGA. Eight configurations of the FPGA are stored in on-chip memory. This inactive on-chip memory is distributed around the chip, and accessible so that the entire configuration of the FPGA can be changed in a single cycle of the memory. The entire configuration of the FPGA can be loaded from this on-chip memory in 30 ns. Inactive memory ... View full abstract»

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  • A wireless LAN demodulator in a Pamette: design and experience

    Publication Year: 1997, Page(s):40 - 45
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    We have implemented the digital section of a wireless local area network (WLAN) demodulator in a reconfigurable interface card called the PCI Pamette. The entire baseband section of the demodulator has been implemented using the Pamette and a simple analog to digital mezzanine board. This is the second version of the demodulator, the first being a card-based design using a mixture of discrete and ... View full abstract»

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  • Compilation tools for run-time reconfigurable designs

    Publication Year: 1997, Page(s):56 - 65
    Cited by:  Papers (30)  |  Patents (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (828 KB)

    This paper describes a framework and tools for automating the production of designs which can be partially reconfigured at run time. The tools include: a partial evaluator, which produces configuration files for a given design, where the number of configurations can be minimised by a process, known as compile-time sequencing; an incremental configuration calculator, which takes the output of the p... View full abstract»

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  • The swappable logic unit: a paradigm for virtual hardware

    Publication Year: 1997, Page(s):77 - 86
    Cited by:  Papers (35)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Swappable Logic Units (SLUs) were introduced by the author previously (1996) to play a role in virtual hardware subsystems that is analogous to the role of pages or segments in virtual memory subsystems. The intention is that a conventional operating system can be extended to manage SLU circuitry implemented using FPGA real estate. In order to minimise operating system overheads, two particular SL... View full abstract»

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  • Automated target recognition on SPLASH 2

    Publication Year: 1997, Page(s):192 - 200
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    Automated target recognition is an application area that requires special-purpose hardware to achieve reasonable performance. FPGA-based platforms can provide a high level of performance for ATR systems if the implementation can be adapted to the limited FPGA and routing resources of these architectures. The paper discusses a mapping experiment where a linear-systolic implementation of an ATR algo... View full abstract»

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  • Acceleration of an FPGA router

    Publication Year: 1997, Page(s):175 - 181
    Cited by:  Papers (8)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The authors describe their experience and progress in accelerating an FPGA router. Placement and routing is undoubtedly the most time-consuming process in automatic chip design or configuring programmable logic devices as reconfigurable computing elements. Their goal is to accelerate routing of FPGAs by 10 fold with a combination of processor clusters and hardware acceleration. Coarse-grain parall... View full abstract»

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  • On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor

    Publication Year: 1997, Page(s):246 - 247
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    We summarize our study on implementing tautology checking, a fundamental logic synthesis algorithm, using an FPGA based reconfigurable application specific coprocessor. The use of the tautology checking algorithm is first discussed followed by the specifics of hardware accelerator implementation and interface to application software. We compare our hardware accelerator for the tautology check algo... View full abstract»

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  • Defect tolerance on the Teramac custom computer

    Publication Year: 1997, Page(s):116 - 123
    Cited by:  Papers (52)  |  Patents (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    Teramac is a large custom computer which works correctly despite the fact that three quarters of its FPGAs contain defects. This is accomplished through unprecedented use of defect tolerance, which substantially reduces Teramac's cost and permits it to have an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires, that are introduced during the manu... View full abstract»

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  • Implementation of single precision floating point square root on FPGAs

    Publication Year: 1997, Page(s):226 - 232
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The square root operation is hard to implement on FPGAs because of the complexity of the algorithms. In this paper, we present a non-restoring square root algorithm and two very simple single precision floating point square root implementations based on the algorithm on FPGAs. One is low-cost iterative implementation that uses a traditional adder/subtracter. The operation latency is 25 clock cycle... View full abstract»

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  • FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)

    Publication Year: 1997, Page(s):155 - 164
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (724 KB)

    The implementation of a number of FIR filter structures in the Xilinx XC6200 technology is presented. The designs have been implemented using a combination of IRIS, an architectural synthesis tool and Trianus/Hades a set of integrated tools for implementing algorithms on Custom Computing Machines. The main attraction of this approach is that it allows algorithms to be compiled quickly allowing per... View full abstract»

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  • Speech recognition HMM training on reconfigurable parallel processor

    Publication Year: 1997, Page(s):242 - 243
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB)

    Armstrong III is a 20 node multi-computer that is currently operational. In addition to a RISC processor, each node contains reconfigurable resources implemented with FPGAs. The in-circuit reprogramability of static RAM based FPGAs allows the computational capabilities of a node to be dynamically matched to the computational requirements of an application. Most reconfigurable computers in existenc... View full abstract»

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  • Garp: a MIPS processor with a reconfigurable coprocessor

    Publication Year: 1997, Page(s):12 - 21
    Cited by:  Papers (267)  |  Patents (191)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an... View full abstract»

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  • Computing kernels implemented with a wormhole RTR CCM

    Publication Year: 1997, Page(s):98 - 105
    Cited by:  Papers (5)  |  Patents (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    The wormhole run-time reconfiguration (RTR) computing paradigm is a method for creating high performance computational pipelines. The scalability, distributed control and data flow features of the paradigm allow it to fit neatly into the configurable computing machine (CCM) domain. To date, the field has been dominated by large bit-oriented devices whose flexibility can lead to lowered silicon uti... View full abstract»

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  • Increased FPGA capacity enables scalable, flexible CCMs: an example from image processing

    Publication Year: 1997, Page(s):211 - 217
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    The need to partition computation across multiple programmable devices in array architecture CCMs leads to performance bottlenecks in data flow through the computer and wiring delays between adjacent devices. However, significant improvements in FPGA capacities have brought one to a threshold where direct inter-chip connections are not required because an entire algorithm can be implemented on a s... View full abstract»

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  • Mapping a real-time video algorithm to a context-switched FPGA

    Publication Year: 1997, Page(s):236 - 237
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    This paper describes the implementation of a real-time video algorithm on a context-switched FPGA. The FPGA is based on the Xilinx XC4000E FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. The algorithm makes use of special features of this architecture to achieve high utilization of the silicon at run... View full abstract»

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  • The RAW benchmark suite: computation structures for general purpose computing

    Publication Year: 1997, Page(s):134 - 143
    Cited by:  Papers (24)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    The RAW benchmark suite consists of twelve programs designed to facilitate comparing, validating, and improving reconfigurable computing systems. These benchmarks run the gamut of algorithms found in general purpose computing, including sorting, matrix operations, and graph algorithms. The suite includes an architecture-independent compilation framework, Raw Computation Structures (RawCS), to expr... View full abstract»

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  • A parallel hardware evolvable computer POLYP

    Publication Year: 1997, Page(s):238 - 239
    Cited by:  Papers (1)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    Previous work (J.S. McCaskill et al., 1996; 1997) has shown the power of massively parallel configurable hardware (NGEN) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom circuit simulation of fine grained physical processes via a massively parallel architecture, e.g. 144 hardware configurable field programm... View full abstract»

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  • An FPGA-based coprocessor for ATM firewalls

    Publication Year: 1997, Page(s):30 - 39
    Cited by:  Papers (10)  |  Patents (45)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1188 KB)

    This implementation of the firewall enables a high degree of traffic selectability yet avoids the usual performance penalty associated with IP level firewalls. This approach is applicable to high-speed broadband networks, and asynchronous transfer mode (ATM) networks are addressed in particular. Security management is achieved through a new technique of active connection management with authentica... View full abstract»

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  • Incremental reconfiguration for pipelined applications

    Publication Year: 1997, Page(s):47 - 55
    Cited by:  Papers (21)  |  Patents (195)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    This paper examines the implementation of pipelined applications using run-time reconfiguration. Throughput and latency of pipelined applications can be significantly improved when reconfiguration is performed at the level of individual pipeline stages, as opposed to configuration of the entire FPGA. If reconfiguration and execution can be performed simultaneously, the performance of a pipelined a... View full abstract»

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