VHDL International Users' Forum, 1997. Proceedings

19-22 Oct. 1997

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  • Proceedings VHDL International Users' Forum. Fall Conference

    Publication Year: 1997
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    Freely Available from IEEE
  • OOVHDL: object oriented VHDL

    Publication Year: 1997, Page(s):54 - 59
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (387 KB)

    In the last decade, VHDL has played an important role in the explosive growth of the electronic design automation industry and, currently, it is widely used by hardware systems designers in many projects. However to keep up with the steady increase in complexity of hardware systems, to allow reuse of design models, and to reduce development time and cost, new design methods must be found. Several ... View full abstract»

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  • Index of authors

    Publication Year: 1997, Page(s): 279
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    Freely Available from IEEE
  • RTL based scan BIST

    Publication Year: 1997, Page(s):117 - 121
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The synthesis of ASICs from register transfer level (RTL) sources is often a bottom-up iterative process where the synthesis process is carefully controlled to produce a gate-level design which meets the desired constraints. Test logic, such as built-in self-test (BIST), is typically inserted at the gate level. This may cause new violations of timing/area goals, thus causing an expensive cycle of ... View full abstract»

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  • Proposing graphic extensions to VHDL

    Publication Year: 1997, Page(s):109 - 115
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    VHDL is a text-based hardware description language but, traditionally, graphical representation was used for describing the structure and the architecture of hardware. Even today, the leading tools offer some graphical design entry and thus a graphical representation of its models. In general, these representations are not compatible to each other and, when transferring the VHDL model from one too... View full abstract»

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  • Semantics based co-specifications to design DSP systems

    Publication Year: 1997, Page(s):105 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Presents our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded digital signal processing (DSP) systems. Instead of assuming one semantics (for instance, synchronous semantics) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements... View full abstract»

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  • Hardware/software codesign of a scalable embedded radar signal processor

    Publication Year: 1997, Page(s):200 - 208
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2356 KB)

    The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using CosmosTM, simulated with QuickHDLTM , and analyzed with Cosmos. Results for a Mercur... View full abstract»

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  • A performance modeling framework applied to real time infrared search and track processing

    Publication Year: 1997, Page(s):33 - 42
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2352 KB)

    The purpose and goals of performance modeling for multiprocessor systems using a token-based methodology in VHDL are discussed. Following this motivation, a framework for performance modeling is described, which involves modeling hardware and software at different levels of abstraction; the scope of the paper primarily addresses the high profile performance model. A commercial tool supporting this... View full abstract»

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  • Extending VHDL to the systems level

    Publication Year: 1997, Page(s):96 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high-level design decisions. Although VHDL is an excellent digital system description language, it lacks the flexibility to address all systems-level issues. Digital system behavior and structure are effectively handled, bu... View full abstract»

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  • Improvements to ADEPT-a VHDL based integrated design environment for performance and dependability analysis

    Publication Year: 1997, Page(s):190 - 199
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have b... View full abstract»

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  • Mixed-level modeling in VHDL using the watch-and-react interface

    Publication Year: 1997, Page(s):25 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling... View full abstract»

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  • A new methodology and generic model library for the rapid prototyping of real-time image processing systems

    Publication Year: 1997, Page(s):268 - 277
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    The foremost objective of system designers is to develop hardware with the correct functionality in the shortest possible time. Therefore, they are keen to exploit any methodology that will help to reduce development times, increase reuse and make `right first time' design an achievable target. This paper proposes a method that permits rapid prototyping of custom hardware for the implementation of... View full abstract»

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  • Building a test environment component in VHDL for an infrared link access protocol (IrLAP) compliant ASIC interface

    Publication Year: 1997, Page(s):217 - 224
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every actio... View full abstract»

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  • Use of VHDL within a system level design flow

    Publication Year: 1997, Page(s):150 - 155
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal descri... View full abstract»

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  • Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library

    Publication Year: 1997, Page(s):88 - 94
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Describes our design experience on fast prototyping with the development of an ASIC for ATM applications from the specification to the final implementation. The main goal of fast and safe prototyping is reached by using the CSELT Intellectual Properties Library of parametric macro-modules. This is a synthesizable library composed of a set of modules, written in RT-level VHDL and implementing funct... View full abstract»

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  • VHDL models supporting a system-level design process: a RASSP approach

    Publication Year: 1997, Page(s):183 - 188
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4× improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a... View full abstract»

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  • SCUBA: an HDL data-path/memory module generator for FPGAs

    Publication Year: 1997, Page(s):135 - 142
    Cited by:  Papers (1)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    Lucent Technologies' ORCA (Optimized Reconfigurable Cell Array) FPGAs, with their nibble-oriented architecture, are especially suitable for data-path-intensive circuits. The current design flows do not fully utilize the data-path and memory capabilities in the ORCA architecture. To fully utilize the capability of ORCA's flexible data-path blocks and to provide the designer with the flexibility of ... View full abstract»

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  • Functional fault simulation of VHDL gate level models

    Publication Year: 1997, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be... View full abstract»

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  • Hardware/software co-design in the rapid prototyping of application-specific signal processors methodology

    Publication Year: 1997, Page(s):241 - 250
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1164 KB)

    The Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is focused on speeding up the design and reducing the cost of signal processing systems. However, a Hardware/Software Co-design approach has been developed that has application to a wide range of design domains. HW/SW Co-design refers to the simultaneous consideration of hardware and software within the system design p... View full abstract»

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  • Processes with `incomplete' sensitivity lists and their synthesis aspects

    Publication Year: 1997, Page(s):75 - 81
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an ... View full abstract»

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  • Reuse through genericity in SUAVE

    Publication Year: 1997, Page(s):170 - 177
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider v... View full abstract»

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  • On comparing different modeling styles [VHDL]

    Publication Year: 1997, Page(s):264 - 267
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    VHDL plays a dominating role in today's system designs. Its primary application domain is currently focussed on RTL descriptions. One approach in dealing with the still dramatically increasing complexity of digital systems is to use VHDL more and more for executable specifications and complex test-benches. In this paper, we present the comparison results of models describing the same design unit u... View full abstract»

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  • Redesign of a generic VHDL model template for SRAMs

    Publication Year: 1997, Page(s):122 - 125
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    To reduce the time spent in writing and testing SRAM models, a method to automatically construct and deliver efficient SRAM models to the modeling community was developed. A new template, based on older existing models, targeted improvements in parameterization of variables and modularization of functionality, as well as efficient use of VHDL. The new template was posted to the World Wide Web and ... View full abstract»

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  • VHDL-based performance modeling: an application of the PMW tool suite to an image classification system

    Publication Year: 1997, Page(s):209 - 215
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    In a simulation-based design process developed for the Rapid Prototyping of Application-Specific Signal Processors program (RASSP), an abstract VHDL performance model forms a virtual prototype of a full DSP system that is timing- and data-faithful. Full-system models provide early design verification by simulating application software and hardware in an integrated co-design development. This paper... View full abstract»

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  • Rapid-prototyping of high-performance RISC cores with VHDL

    Publication Year: 1997, Page(s):43 - 52
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of hig... View full abstract»

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