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VHDL International Users' Forum, 1997. Proceedings

19-22 Oct. 1997

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  • Proceedings VHDL International Users' Forum. Fall Conference

    Publication Year: 1997
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    Freely Available from IEEE
  • OOVHDL: object oriented VHDL

    Publication Year: 1997, Page(s):54 - 59
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (387 KB)

    In the last decade, VHDL has played an important role in the explosive growth of the electronic design automation industry and, currently, it is widely used by hardware systems designers in many projects. However to keep up with the steady increase in complexity of hardware systems, to allow reuse of design models, and to reduce development time and cost, new design methods must be found. Several ... View full abstract»

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  • Index of authors

    Publication Year: 1997, Page(s): 279
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    Freely Available from IEEE
  • Mixed-level modeling in VHDL using the watch-and-react interface

    Publication Year: 1997, Page(s):25 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling... View full abstract»

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  • Implementing a complete test tool set in VHDL

    Publication Year: 1997, Page(s):2 - 10
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented... View full abstract»

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  • Extending VHDL to the systems level

    Publication Year: 1997, Page(s):96 - 104
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high-level design decisions. Although VHDL is an excellent digital system description language, it lacks the flexibility to address all systems-level issues. Digital system behavior and structure are effectively handled, bu... View full abstract»

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  • Hardware/software codesign of a scalable embedded radar signal processor

    Publication Year: 1997, Page(s):200 - 208
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2356 KB)

    The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using CosmosTM, simulated with QuickHDLTM , and analyzed with Cosmos. Results for a Mercur... View full abstract»

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  • Extraction of token based VHDL models from old ASIC net lists

    Publication Year: 1997, Page(s):157 - 161
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually View full abstract»

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  • A hybrid event-simulation/cycle-simulation environment for VHDL-based designs

    Publication Year: 1997, Page(s):258 - 263
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of mo... View full abstract»

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  • A requirements analysis of proposed object oriented VHDL abstractions

    Publication Year: 1997, Page(s):68 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Ci... View full abstract»

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  • Rapid-prototyping of high-performance RISC cores with VHDL

    Publication Year: 1997, Page(s):43 - 52
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of hig... View full abstract»

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  • Functional fault simulation of VHDL gate level models

    Publication Year: 1997, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be... View full abstract»

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  • Reuse through genericity in SUAVE

    Publication Year: 1997, Page(s):170 - 177
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider v... View full abstract»

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  • Supporting hardware trade analysis and cost estimation using design complexity

    Publication Year: 1997, Page(s):126 - 133
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Defines and illustrates a hardware design complexity measure (HDCM) and describe its potential applications to trade-off analysis and cost estimation. Specifically, we define a VHDL complexity measure. We have derived the HDCM from an avionics software design complexity measure (ASDCM) that we have shown to be effective in estimation and optimization of overall software costs. Similar to the ASDCM... View full abstract»

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  • RTL based scan BIST

    Publication Year: 1997, Page(s):117 - 121
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The synthesis of ASICs from register transfer level (RTL) sources is often a bottom-up iterative process where the synthesis process is carefully controlled to produce a gate-level design which meets the desired constraints. Test logic, such as built-in self-test (BIST), is typically inserted at the gate level. This may cause new violations of timing/area goals, thus causing an expensive cycle of ... View full abstract»

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  • Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library

    Publication Year: 1997, Page(s):88 - 94
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Describes our design experience on fast prototyping with the development of an ASIC for ATM applications from the specification to the final implementation. The main goal of fast and safe prototyping is reached by using the CSELT Intellectual Properties Library of parametric macro-modules. This is a synthesizable library composed of a set of modules, written in RT-level VHDL and implementing funct... View full abstract»

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  • Improvements to ADEPT-a VHDL based integrated design environment for performance and dependability analysis

    Publication Year: 1997, Page(s):190 - 199
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have b... View full abstract»

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  • Use of VHDL within a system level design flow

    Publication Year: 1997, Page(s):150 - 155
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal descri... View full abstract»

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  • IEEE VHDL 1076.1: mixed-signal behavioral modeling and verification in view of automotive applications

    Publication Year: 1997, Page(s):252 - 257
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper provides both an overview of the VHDL 1076.1 effort to extend the standard hardware description language VHDL 1076 to support the description and simulation of analog and mixed analog/digital systems as well as a VHDL 1076-based mixed-signal design methodology for application-specific mixed-signal circuits in automotive applications View full abstract»

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  • SUAVE: painless extension for an object-oriented VHDL

    Publication Year: 1997, Page(s):60 - 67
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mec... View full abstract»

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  • A performance modeling framework applied to real time infrared search and track processing

    Publication Year: 1997, Page(s):33 - 42
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2352 KB)

    The purpose and goals of performance modeling for multiprocessor systems using a token-based methodology in VHDL are discussed. Following this motivation, a framework for performance modeling is described, which involves modeling hardware and software at different levels of abstraction; the scope of the paper primarily addresses the high profile performance model. A commercial tool supporting this... View full abstract»

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  • Using WAVES for verification of synthesized sub-components in a deeply hierarchical design

    Publication Year: 1997, Page(s):11 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics accelerator integrated circuit with approximately 700,000 transistors. The purpose of the methodology was to automate as much as possible the functional testing of all implementation levels. WAVES and its a... View full abstract»

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  • Semantics based co-specifications to design DSP systems

    Publication Year: 1997, Page(s):105 - 108
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    Presents our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded digital signal processing (DSP) systems. Instead of assuming one semantics (for instance, synchronous semantics) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements... View full abstract»

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  • VHDL-based performance modeling: an application of the PMW tool suite to an image classification system

    Publication Year: 1997, Page(s):209 - 215
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    In a simulation-based design process developed for the Rapid Prototyping of Application-Specific Signal Processors program (RASSP), an abstract VHDL performance model forms a virtual prototype of a full DSP system that is timing- and data-faithful. Full-system models provide early design verification by simulating application software and hardware in an integrated co-design development. This paper... View full abstract»

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  • VHDL design environment for legacy electronics (VDELE)

    Publication Year: 1997, Page(s):162 - 169
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (808 KB)

    The rapidly escalating DMS (Diminishing Manufacturing Sources) problem for digital electronic components is seriously impacting the ability of avionics equipment suppliers to provide affordable equipment to new aircraft. Sustainment of this equipment in the field is a major cost driver in the O&S (Operation & Support) cost equation due to the same problem. The development of F3I... View full abstract»

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