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VHDL International Users' Forum, 1997. Proceedings

Date 19-22 Oct. 1997

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Displaying Results 1 - 25 of 39
  • Proceedings VHDL International Users' Forum. Fall Conference

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    Freely Available from IEEE
  • Index of authors

    Page(s): 279
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    Freely Available from IEEE
  • VHDL design environment for legacy electronics (VDELE)

    Page(s): 162 - 169
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    The rapidly escalating DMS (Diminishing Manufacturing Sources) problem for digital electronic components is seriously impacting the ability of avionics equipment suppliers to provide affordable equipment to new aircraft. Sustainment of this equipment in the field is a major cost driver in the O&S (Operation & Support) cost equation due to the same problem. The development of F3I (Form-Fit-Function-Interface) printed circuit assembly (PCA) level replacements for obsolete digital electronics provides the opportunity to solve both of these problems at minimum cost. The Wright Laboratories sponsored VDELE (VHDL Design Environment for Legacy Electronics) project has developed innovative methodologies for the development of F3 I clones for PCAs that have become obsolete due to DMS problems. The VDELE process extracts VHDL model and test information from the customer digital database and then applies commercially available tools to refine and validate the model in a virtual development environment. The refined VHDL simulation model is then provided to a qualified supplier in the form of a technology independent executable specification for synthesis into a clone PCA replacement. We present a brief description of the VDELE process and the application of the VDELE methodologies to the development of an FPGA (field programmable gate array) based prototype for an F-16 PCA seriously impacted by the DMS problem View full abstract»

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  • Reuse through genericity in SUAVE

    Page(s): 170 - 177
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    VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider variety of contexts without modifying the original code. We show that the genericity added by SUAVE enhances reuse across the spectrum of modeling, from high-level to gate level. In particular, the genericity extensions interact with the SUAVE extensions for object-oriented data modeling to significantly improve support for high-level behavioral modeling and for developing test-benches. We show that the genericity extensions integrate seamlessly with the existing language. Furthermore, the implementation burden is not large, and since generic instantiation is performed at elaboration time, there is no performance penalty in simulation or synthesis View full abstract»

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  • Extending VHDL to the systems level

    Page(s): 96 - 104
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    Systems engineering is the process of looking at many facets of an emerging design. A systems engineer is required to examine and reconcile many information sources when making high-level design decisions. Although VHDL is an excellent digital system description language, it lacks the flexibility to address all systems-level issues. Digital system behavior and structure are effectively handled, but other facets are not. VSPEC represents one attempt to model other facets in the VHDL framework. It adds functional requirement and performance constraint modeling to the VHDL-based design process. This paper first describes VSPEC and its interaction with VHDL. It argues that VSPEC is an excellent first step towards a systems-level description language. However, other facets are needed to model complete systems. A language structure for representing these facets is proposed and a potential source for a semantic definition is identified View full abstract»

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  • IEEE VHDL 1076.1: mixed-signal behavioral modeling and verification in view of automotive applications

    Page(s): 252 - 257
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    This paper provides both an overview of the VHDL 1076.1 effort to extend the standard hardware description language VHDL 1076 to support the description and simulation of analog and mixed analog/digital systems as well as a VHDL 1076-based mixed-signal design methodology for application-specific mixed-signal circuits in automotive applications View full abstract»

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  • Semantics based co-specifications to design DSP systems

    Page(s): 105 - 108
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    Presents our approach to the definition of a multi-paradigm environment to specify, model and synthesize embedded digital signal processing (DSP) systems. Instead of assuming one semantics (for instance, synchronous semantics) to specify and model the whole system, we propose to use simultaneously several semantics to describe and validate key system properties. Traceability of system requirements is challenging with such an approach. We propose an architectural view of systems which defines components and connectors to support respectively functional and non-functional requirements with several levels of abstraction specifying systems. Using the object-oriented framework Ptolemy, which supports simulating and prototyping of heterogeneous systems, a global view of the system is ensured, allowing us to validate its behavior and properties View full abstract»

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  • OOVHDL: object oriented VHDL

    Page(s): 54 - 59
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    In the last decade, VHDL has played an important role in the explosive growth of the electronic design automation industry and, currently, it is widely used by hardware systems designers in many projects. However to keep up with the steady increase in complexity of hardware systems, to allow reuse of design models, and to reduce development time and cost, new design methods must be found. Several documents and publications have proposed to extend VHDL and add object oriented features both to manage the complexity increase and to augment the capabilities and expressiveness of VHDL. The authors describe OOVHDL, which extends VHDL by adding object oriented features such as inheritance, polymorphism mechanism, and communication via messages. The object oriented extensions and the different constructs described in the paper are illustrated through some examples View full abstract»

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  • A performance modeling framework applied to real time infrared search and track processing

    Page(s): 33 - 42
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    The purpose and goals of performance modeling for multiprocessor systems using a token-based methodology in VHDL are discussed. Following this motivation, a framework for performance modeling is described, which involves modeling hardware and software at different levels of abstraction; the scope of the paper primarily addresses the high profile performance model. A commercial tool supporting this modeling framework is then introduced. The discussion continues with an overview of the real time infrared search and track algorithm, and the system design problem. Preliminary results of the performance modeling efforts and validation via code profiling is summarized, and future plans are described View full abstract»

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  • VHDL models supporting a system-level design process: a RASSP approach

    Page(s): 183 - 188
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    The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4× improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a hardware-less VHDL co-simulation and co-verification environment for rapid prototyping. We demonstrate this VHDL-based approach by applying it to the design of a synthetic aperture radar (SAR) system. We present quantitative estimates of the improvements in prototyping time and cost View full abstract»

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  • SUAVE: painless extension for an object-oriented VHDL

    Page(s): 60 - 67
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    The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mechanism. In addition to supporting object-orientation, these extended mechanisms improve the expressiveness of VHDL across the modeling spectrum, from high-level to gate-level. By choosing an incremental and evolutionary approach to extensions, SUAVE avoids major additions to the language that would complicate choice of mechanisms for expressing a design. The paper outlines the SUAVE extensions and illustrates their use through some examples. The mechanisms and examples are readily understood as incremental extensions to current modeling practices, hence “painless extension” View full abstract»

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  • Use of VHDL within a system level design flow

    Page(s): 150 - 155
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    The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal description languages at system level in comparison to VHDL is discussed. Concepts in regard to reconfigurable logic are discussed. An approach for a top-down methodology for this kind of logic is proposed View full abstract»

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  • Mixed-level modeling in VHDL using the watch-and-react interface

    Page(s): 25 - 32
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    Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling domain (value based). Specifically this interface is useful for integrating behavioral models of complex sequential components into performance models. It operates by monitoring the “important” signals in a system and then reacting to changes in these signals by generating tokens or forcing signals to appropriate values given the particular situation. The two main elements in the interface are the trigger and the driver. Program files containing scripting instructions are interpreted by the these two elements as the VHDL model simulates View full abstract»

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  • A hybrid event-simulation/cycle-simulation environment for VHDL-based designs

    Page(s): 258 - 263
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    The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of models: the hardware being verified (concurrent VHDL), behavior models (sequential VHDL) and the simulation control manager (sequential VHDL). Initially, the entire environment was run on an event-simulation engine, but capacity limitations obviated the need to consider use of cycle simulation. However, the cycle-simulation engine in use at Rochester had no inherent support for sequential VHDL. The resulting solution required the development of a hybrid simulation environment which combined the best of both types of simulation engines. The architecture, implementation, benefits and limitations of this hybrid environment are the subject of this paper View full abstract»

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  • Processes with `incomplete' sensitivity lists and their synthesis aspects

    Page(s): 75 - 81
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    Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an `incomplete' sensitivity list. Most, if not all, synthesis tools require that the processes used to describe combinational logic should have a `complete' sensitivity list, while for synchronous logic only the reset, if any, and clock signals should be in the sensitivity list. Beside these two applications of processes with sensitivity lists, there is a vague support for other incomplete sensitivity lists, sometimes resulting in latches in the circuit and sometimes resulting in logic that does not have the proper behaviour. This paper focuses on the synthesis aspects of processes with an incomplete sensitivity list, and presents a method to synthesise a subset of these processes. Also, the problem of synthesising processes with an incomplete sensitivity list is discussed View full abstract»

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  • Rapid-prototyping of high-performance RISC cores with VHDL

    Page(s): 43 - 52
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    The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade's Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of high-performance embeddable cores View full abstract»

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  • Improvements to ADEPT-a VHDL based integrated design environment for performance and dependability analysis

    Page(s): 190 - 199
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    This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have been made to ADEPT in the areas of mixed-level modeling-the cosimulation of performance and behavioral models, dependability modeling and analysis, modeling libraries, and post simulation data visualization tools, are presented View full abstract»

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  • Proposing graphic extensions to VHDL

    Page(s): 109 - 115
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    VHDL is a text-based hardware description language but, traditionally, graphical representation was used for describing the structure and the architecture of hardware. Even today, the leading tools offer some graphical design entry and thus a graphical representation of its models. In general, these representations are not compatible to each other and, when transferring the VHDL model from one toolset to another, the graphical representation is lost. Also, when introducing an audience to a new hardware concept, the graphical representation helps for an easy understanding of the presented concepts. A solution to this situation would be to define a standard graphical representation for VHDL constructs. The graphical representation could be restricted to a standard representation of structural constructs. The graphical representation of behavioral constructs could be made open to the tool vendors. This definition does not require a change of VHDL in itself. A similar approach was taken to the formal description languages SDL and MSC, which have, besides their textual representation, a graphical representation. The author has had good experiences with SDL, which is a formal description technique. The language is powerful, has a growing acceptance and is well suited for hardware/software codesign. Based on this experience, the proposal for a graphical representation of VHDL is presented in this paper. The paper starts with a short introduction to SDL, followed by a demonstration of how graphic constructs could increase the acceptance of VHDL View full abstract»

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  • Supporting hardware trade analysis and cost estimation using design complexity

    Page(s): 126 - 133
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    Defines and illustrates a hardware design complexity measure (HDCM) and describe its potential applications to trade-off analysis and cost estimation. Specifically, we define a VHDL complexity measure. We have derived the HDCM from an avionics software design complexity measure (ASDCM) that we have shown to be effective in estimation and optimization of overall software costs. Similar to the ASDCM, we believe that the proposed HDCM could enable more optimal hardware design, implementation and maintenance View full abstract»

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  • Fast prototyping of an ASIC for ATM application using a synthesizable VHDL flexible library

    Page(s): 88 - 94
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    Describes our design experience on fast prototyping with the development of an ASIC for ATM applications from the specification to the final implementation. The main goal of fast and safe prototyping is reached by using the CSELT Intellectual Properties Library of parametric macro-modules. This is a synthesizable library composed of a set of modules, written in RT-level VHDL and implementing functions commonly used in telecom applications. The developed circuit performs the following main functions: UTOPIA/PB interface conversion for both the physical and ATM sides, and ATM cell header processing. The circuit is intended to be used in an ATM switching system and has been designed using a 0.5 μm CMOS sea-of-gates library (3.3 V). It has a complexity of 70 kgates and an operational frequency of 33 MHz. The maximum throughput is 155 Mbit/s. It has been developed in approximately three months View full abstract»

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  • Hardware/software co-design in the rapid prototyping of application-specific signal processors methodology

    Page(s): 241 - 250
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    The Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is focused on speeding up the design and reducing the cost of signal processing systems. However, a Hardware/Software Co-design approach has been developed that has application to a wide range of design domains. HW/SW Co-design refers to the simultaneous consideration of hardware and software within the system design process. It is the co-development and co-verification of the hardware and software through the use of simulation and/or verification. This paper describes the generic Hardware/Software Co-design process developed under RASSP and provides an application example to highlight its use in the signal processing domain View full abstract»

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  • A requirements analysis of proposed object oriented VHDL abstractions

    Page(s): 68 - 73
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    The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Cincinnati while under contract to Wright Laboratory. Conclusions are based on how well such object oriented extensions work with existing VHDL benefits to provide increased capabilities of the language and associated tools View full abstract»

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  • A new methodology and generic model library for the rapid prototyping of real-time image processing systems

    Page(s): 268 - 277
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    The foremost objective of system designers is to develop hardware with the correct functionality in the shortest possible time. Therefore, they are keen to exploit any methodology that will help to reduce development times, increase reuse and make `right first time' design an achievable target. This paper proposes a method that permits rapid prototyping of custom hardware for the implementation of real-time image processing systems. This methodology consists of partitioning the system into component blocks and then prototyping using a library of generic VHDL models. Each component model has a standard interface and has been simulated and synthesised to a technology-independent level. Systems can be quickly and easily constructed using this library and a model-oriented design flow. This technique permits the rapid prototyping of hardware whilst allowing the functionality and performance of the proposed system to be quickly assessed and verified throughout the design cycle View full abstract»

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  • Extraction of token based VHDL models from old ASIC net lists

    Page(s): 157 - 161
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    The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually View full abstract»

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  • Reducing FPGA design modification time

    Page(s): 143 - 149
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    An incremental approach to logic synthesis developed under the RASSP program is described. The approach reduces the time it takes to implement changes in an FPGA design. It also helps designers stay connected with the implementation issues and helps new synthesis users get over the learning curve. It involves resynthesizing only the blocks of the design that change, rather than the whole design. Existing blocks of unmodified logic are reused through the netlist merge capabilities of many foundry tools. Results show that the incremental approach helps speed up the total design cycle time View full abstract»

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