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VHDL International Users' Forum, 1997. Proceedings

Date 19-22 Oct. 1997

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  • Proceedings VHDL International Users' Forum. Fall Conference

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (195 KB)
    Freely Available from IEEE
  • Index of authors

    Publication Year: 1997, Page(s): 279
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    Freely Available from IEEE
  • Building a test environment component in VHDL for an infrared link access protocol (IrLAP) compliant ASIC interface

    Publication Year: 1997, Page(s):217 - 224
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (696 KB)

    This paper presents the experiences of the Texas Instruments Bus Solutions ASIC design team in its efforts to create and use a component written in VHDL which was embedded into the test environment for an ASIC. The VHDL component described had to be: dynamically controllable; able to accept and check a wide range of expected results from the ASIC design; able to stimulate the design in every actio... View full abstract»

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  • On comparing different modeling styles [VHDL]

    Publication Year: 1997, Page(s):264 - 267
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    VHDL plays a dominating role in today's system designs. Its primary application domain is currently focussed on RTL descriptions. One approach in dealing with the still dramatically increasing complexity of digital systems is to use VHDL more and more for executable specifications and complex test-benches. In this paper, we present the comparison results of models describing the same design unit u... View full abstract»

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  • VHDL models supporting a system-level design process: a RASSP approach

    Publication Year: 1997, Page(s):183 - 188
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    The successful Rapid Prototyping of Application-Specific Signal Processors (RASSP) program of the US Department of Defense (DARPA and Tri-Services) targets a 4× improvement in cost and cycle time for design, prototyping, manufacturing, and support processes (relative to current practice). We describe a RASSP-based virtual prototyping process which incorporates parametric cost modeling into a... View full abstract»

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  • Using WAVES for verification of synthesized sub-components in a deeply hierarchical design

    Publication Year: 1997, Page(s):11 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    The Waveform and Vector Exchange Standard (WAVES) and organically developed tools were used in a new testing and verification methodology for an in-house design of a massively parallel graphics accelerator integrated circuit with approximately 700,000 transistors. The purpose of the methodology was to automate as much as possible the functional testing of all implementation levels. WAVES and its a... View full abstract»

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  • VHDL-based performance modeling: an application of the PMW tool suite to an image classification system

    Publication Year: 1997, Page(s):209 - 215
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    In a simulation-based design process developed for the Rapid Prototyping of Application-Specific Signal Processors program (RASSP), an abstract VHDL performance model forms a virtual prototype of a full DSP system that is timing- and data-faithful. Full-system models provide early design verification by simulating application software and hardware in an integrated co-design development. This paper... View full abstract»

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  • A hybrid event-simulation/cycle-simulation environment for VHDL-based designs

    Publication Year: 1997, Page(s):258 - 263
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The need for flexible high-level simulation environments continues to persist due to increasingly high-density chip technologies coupled with ever-decreasing product cycle times. The simulation development team at IBM-Rochester has designed a durable simulation environment providing a highly abstract test-case language and an adaptable model interface. The environment consists of three types of mo... View full abstract»

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  • VHDL modeling and tutoring efforts by Mississippi State University

    Publication Year: 1997, Page(s):179 - 182
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Mississippi State University had a two-fold participation in the RASSP project. The first task for MSU was to provide VHDL models for commercially available parts. The second task was to provide a demonstration of the Internet-based Intelligent Tutoring for Tools (I2T2) architecture, which is under development by Web Services, Inc View full abstract»

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  • A requirements analysis of proposed object oriented VHDL abstractions

    Publication Year: 1997, Page(s):68 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The paper analyzes benefits gained from object oriented extensions to VHDL by providing and examining example VHDL test cases. Both existing VHDL language features and proposed extensions are examined based on what abstraction benefits are gained from a requirements point of view. The paper concentrates specifically on an analysis of some object oriented extensions proposed by the University of Ci... View full abstract»

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  • Implementing a complete test tool set in VHDL

    Publication Year: 1997, Page(s):2 - 10
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    As a concurrent programming environment, VHDL can be used for the implementation of most digital system test algorithms for test generation and fault simulation. The benefits are in easier implementations, due to the concurrent nature of VHDL, and a uniform hardware netlist format for all design and test applications. In this paper, the general methodologies for using VHDL in testing are presented... View full abstract»

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  • Hardware/software codesign of a scalable embedded radar signal processor

    Publication Year: 1997, Page(s):200 - 208
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2356 KB)

    The RASSP performance modeling methodology was used to rapidly model and compare alternative hardware/software architectures for a scalable embedded radar signal processor based on COTS DSP boards. VHDL performance models were generated from graphical hardware and software architectures using CosmosTM, simulated with QuickHDLTM , and analyzed with Cosmos. Results for a Mercur... View full abstract»

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  • IEEE VHDL 1076.1: mixed-signal behavioral modeling and verification in view of automotive applications

    Publication Year: 1997, Page(s):252 - 257
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    This paper provides both an overview of the VHDL 1076.1 effort to extend the standard hardware description language VHDL 1076 to support the description and simulation of analog and mixed analog/digital systems as well as a VHDL 1076-based mixed-signal design methodology for application-specific mixed-signal circuits in automotive applications View full abstract»

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  • Reuse through genericity in SUAVE

    Publication Year: 1997, Page(s):170 - 177
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider v... View full abstract»

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  • SUAVE: painless extension for an object-oriented VHDL

    Publication Year: 1997, Page(s):60 - 67
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The SUAVE project aims to introduce object-oriented extensions to data modeling into VHDL in a way that does not disturb the existing language or its use. Designers regularly define abstract data types by using aspects of VHDL's type system, subprograms, and packages. The SUAVE approach builds on these basic mechanisms by strengthening the facilities for encapsulation and adding an inheritance mec... View full abstract»

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  • Reducing FPGA design modification time

    Publication Year: 1997, Page(s):143 - 149
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    An incremental approach to logic synthesis developed under the RASSP program is described. The approach reduces the time it takes to implement changes in an FPGA design. It also helps designers stay connected with the implementation issues and helps new synthesis users get over the learning curve. It involves resynthesizing only the blocks of the design that change, rather than the whole design. E... View full abstract»

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  • Component modeling for reliability analysis by simulation

    Publication Year: 1997, Page(s):225 - 229
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov mo... View full abstract»

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  • A new methodology and generic model library for the rapid prototyping of real-time image processing systems

    Publication Year: 1997, Page(s):268 - 277
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1100 KB)

    The foremost objective of system designers is to develop hardware with the correct functionality in the shortest possible time. Therefore, they are keen to exploit any methodology that will help to reduce development times, increase reuse and make `right first time' design an achievable target. This paper proposes a method that permits rapid prototyping of custom hardware for the implementation of... View full abstract»

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  • Improvements to ADEPT-a VHDL based integrated design environment for performance and dependability analysis

    Publication Year: 1997, Page(s):190 - 199
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    This paper presents improvements to the Advanced Design Environment Prototype Tool (ADEPT) that have been developed under the RASSP (Rapid Prototyping of Application Specific Signal Processors) program. ADEPT is an integrated design environment based on IEEE 1076 VHDL that supports the design and analysis of digital systems from initial concept to the final implementation. Improvements that have b... View full abstract»

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  • Functional fault simulation of VHDL gate level models

    Publication Year: 1997, Page(s):18 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A method of fault injection and fault simulation is proposed. A gate level circuit is modified to include logic gates where faults are to be injected. Values assigned to the inputs of the new additions of the circuit have the effect of injecting stuck-at faults at various lines of the original circuit. A functional model is obtained to represent the new altered circuit. This faultable model can be... View full abstract»

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  • Processes with `incomplete' sensitivity lists and their synthesis aspects

    Publication Year: 1997, Page(s):75 - 81
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an ... View full abstract»

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  • Use of VHDL within a system level design flow

    Publication Year: 1997, Page(s):150 - 155
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    The Automation Systems group at IFAT is working at a HW/SW codesign methodology, which is based on the formal description technique SDL. The methodology uses SDL at system level and VHDL and C for implementation specification. In this document the hardware part of this HW/SW codesign methodology is discussed in detail. The experiences with this methodology are represented. The use of formal descri... View full abstract»

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  • A model-year architecture approach to hardware reuse in digital signal processor system design

    Publication Year: 1997, Page(s):231 - 240
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (936 KB)

    This paper describes our team's hardware model-year architecture (MYA) approach to develop cost-effective signal processors that can be applied to a wide range of military and commercial applications. We present an overview of the MYA approach and describe the framework. We introduce two key hardware architectural interfaces: the Standard Virtual Interface (SVI) and the Reconfigurable Network Inte... View full abstract»

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  • Mixed-level modeling in VHDL using the watch-and-react interface

    Publication Year: 1997, Page(s):25 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    Using VHDL, it is possible to model systems at many different levels of detail. The various modeling levels (performance, behavioral, etc.) can also be intermixed to create mixed-level models. The paper describes the watch-and-react interface which was created to resolve the differences in timing and data abstraction between the performance modeling domain (token based) and the behavioral modeling... View full abstract»

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  • A symbol based algorithm for hardware implementation of cyclic redundancy check (CRC)

    Publication Year: 1997, Page(s):82 - 87
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    Describes a symbolic simulation-based algorithm to derive optimized Boolean equations for a parameterizable data width CRC generator/checker. The equations are then used to implement a data flow representation of the CRC circuit in VHDL. The VHDL description is subsequently synthesized to gates. The area and timing results of the hardware implementation are presented and compared with a convention... View full abstract»

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