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Proceedings of the International Conference on Application Specific Array Processors

2-4 Sept. 1991

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Displaying Results 1 - 25 of 37
  • On the use of most significant bit first arithmetic on the design of high performance DSP chips

    Publication Year: 1991
    Cited by:  Papers (1)
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  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.91TH0382-2)

    Publication Year: 1991
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    Freely Available from IEEE
  • Introduction to system design: algorithms and parallel architectures

    Publication Year: 1991
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  • Parallel digital implementations of neural networks

    Publication Year: 1991, Page(s):162 - 176
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    The paper reviews implementations of neural networks on parallel digital machines. The connectionist neural networks models are discussed from the point of view of their computational characteristics. The levels of parallelism available in the models and the factors affecting their performance of the models on the parallel machines are presented. Several mapping methodologies applicable to neural ... View full abstract»

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  • A wave digital filter three-port adaptor with fine grained pipelining

    Publication Year: 1991, Page(s):116 - 128
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    A VLSI architecture for implementing wave digital filter three-port adaptors is described. The design presented general one and can be used to construct RLC ladder filters. High sampling rates are obtained through a combination of fine grained pipelining and most significant bit first arithmetic. The resulting circuit is highly regular and for the most part consists of simple carry save adders View full abstract»

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  • The case for application specific computing

    Publication Year: 1991, Page(s):2 - 9
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Application specific computing is the only way to solve many computationally intensive problems. In contrast to general purpose computing, application specific computing can achieve high throughput, small size, and (for CMOS realizations) low power. The improvement in the area time product is often in excess of two orders of magnitude. This paper reviews past endeavors in special purpose processin... View full abstract»

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  • Partitioning schemes for circuit simulation on a multiprocessor array

    Publication Year: 1991, Page(s):177 - 183
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    The factorization of sparse matrices is used in the inner loop of many engineering algorithms. including circuit simulation. This time consuming operation can be speeded up by utilizing multiprocessor architectures. Distributed memory architectures can overcome the memory bottleneck normally associated with shared memory machines but require a careful distribution of matrix data to the processors.... View full abstract»

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  • A design method for on-line reconfigurable array processors

    Publication Year: 1991, Page(s):387 - 401
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    A design methodology for reconfigurable array processors is described which extends a known design method for non-redundant array architectures. Using self-checking processing elements, the systematic design of on-line reconfigurable arrays is feasible, which perform reconfiguration concurrently with data processing. Reconfiguration schemes suitable for one- and two-dimensional array processors ar... View full abstract»

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  • Pipelining and transposing heterogeneous array circuits

    Publication Year: 1991, Page(s):263 - 277
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    This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimised by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on developing novel pipelined designs for parallel division. It is found that, for a field-programmable gate arr... View full abstract»

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  • The Arithmetic Cube: error analysis and simulation

    Publication Year: 1991, Page(s):129 - 143
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    This paper examines the error performance and presents simulation results of the Arithmetic Cube. The Arithmetic Cube is a special purpose architecture for computing high speed convolution and the DFT. An error analysis is performed for convolution and the DFT, as computed on the Cube. An upper bound on the number of bits lost is derived. The Cube looses at most an extra two bits (four bits), whil... View full abstract»

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  • Mapping FIR filtering on systolic rings

    Publication Year: 1991, Page(s):87 - 101
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    During the past decade, systolic arrays have been designed for a wide variety of scientific applications, which are based on highly parallel linear system manipulations. Partitioning and mapping of systolic algorithms has been a key issue for real implementations, in terms of both cost and manageability. The authors demonstrate the mapping of triangular systolic array algorithms onto a one-dimensi... View full abstract»

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  • Consistency in dataflow graphs

    Publication Year: 1991, Page(s):355 - 369
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    This paper describes an analytical model for the behavior of dataflow graphs with data-dependent control flow. The number of tokens produced or consumed by each actor is given as a symbolic function of the Booleans in the system. Long term averages can be analyzed to determine consistency of token flow rates, which in turn determines whether memory requirements are bounded. Short-term behavior can... View full abstract»

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  • Transformation of systolic algorithms for interleaving partitions

    Publication Year: 1991, Page(s):56 - 71
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    A systematic method to map systolic problems onto multicomputers is presented. A systolic problem is a problem for which it is possible to design a systolic algorithm. This method selects and transforms the systolic algorithm into a parallel algorithm with high granularity. The communications requirements are reduced and the performance can be increased. The proposed scheme requires a classificati... View full abstract»

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  • A defect tolerant systolic array implementation for real time image processing

    Publication Year: 1991, Page(s):25 - 39
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    An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of two hundred and fifty-six taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines... View full abstract»

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  • Parallel implementations of discrete relaxation technique on fixed size processor arrays

    Publication Year: 1991, Page(s):184 - 198
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    Discrete relaxation technique has been widely used in pattern recognition, artificial intelligence and computer vision. For the consistent labeling problem for labeling n objects with m labels, a parallel implementation based on a new sequential algorithm is shown. This non-partitioned parallel implementation runs in O(nm) time using nm PE's. ... View full abstract»

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  • Parallel array architectures for motion estimation

    Publication Year: 1991, Page(s):214 - 235
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (856 KB)

    Motion estimation is one of the most computationally intensive tasks required in digital video compression. The authors propose parallelizable motion estimation algorithms with low computational cost for both sub-optimal and optimal motion estimation. For efficient optimal motion estimation, they develop theoretical bounds based on convexity to reduce the required operations. All algorithms are te... View full abstract»

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  • Processor clustering for the design of optimal fixed-size systolic arrays

    Publication Year: 1991, Page(s):402 - 413
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    The authors have shown in their previous work that processor-clustering is a key operation in the design of problem-size independent systolic/wavefront arrays. Indeed, the processor clustering techniques (called passive-clustering and active-clustering) can not only be used to reduce the size of an array to a constant, but also to achieve the design objectives such as transforming inefficient arra... View full abstract»

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  • Fast generation of long sorted runs for sorting a large file

    Publication Year: 1991, Page(s):445 - 456
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    On sequential machines, most internal sorting algorithms can sort no more than m items using a memory of size m. However, sorting with a heap can produce sorted sequences, called runs, of length about twice the heap size. A second advantage of sorting with a heap is that data I/O and the heap restructuring can be performed concurrently to reduce the sorting time. The third advantage is that it can... View full abstract»

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  • A decoupled access/execute processor for matrix algorithms: architecture and programming

    Publication Year: 1991, Page(s):281 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    The authors describe a processor for the execution of a class of matrix algorithms according to the multimesh graph (MMG) mapping method, which is suitable as the processing cell in an application-specific array. The processor uses the decoupled access-execute model of computation, so that it consists of two programmable units: a processing unit (PU) and an access unit (AU). The two programs synch... View full abstract»

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  • Biological information signal processor

    Publication Year: 1991, Page(s):144 - 160
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    The computation requirements for mapping and sequencing the human genome might soon exceed the capability of any existing supercomputer. The systolic array processor presented in this paper, called biological information signal processor (BISP), has the capability to satisfy the current and anticipated future computational requirements for performing sequence comparisons based on the T.F. Smith an... View full abstract»

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  • The missing dimension in real-time signal processing architectures

    Publication Year: 1991, Page(s):104 - 115
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    This paper introduces work done at STAR Semiconductor over the last three years in simplifying the use of digital signal processing techniques. This work has been directed at creating a technology that can go from a block diagram description to the efficient coding of a generally programmable signal processor in a matter of minutes. To achieve this required the development of a new kind of DSP pro... View full abstract»

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  • Synthesizing systolic arrays: some recent developments

    Publication Year: 1991, Page(s):372 - 386
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Methods for synthesizing systolic arrays from uniform DAGs are well understood. The idea is to extract from the original sequential algorithm a dependence graph where all incoming arcs to a given node come from a fixed-size neighborhood, so that dependencies are local. Space-time transformations are then used for scheduling the DAG (timing function) and mapping nodes onto physical processors (allo... View full abstract»

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  • High speed implementation of 1-D and 2-D morphological operations

    Publication Year: 1991, Page(s):249 - 262
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    The design of a morphological processing system is presented, to be used in medical image enhancement and compression. The system consists of a gray scale dilation/erosion systolic array capable of video data rates. The architecture can be implemented with either one dimensional or two dimensional building blocks that accept raster scanned data and exhibits low latency and an optimal pipeline rate... View full abstract»

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  • Mapping different node types of dependence graphs into the same processing element

    Publication Year: 1991, Page(s):72 - 86
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    This paper presents a method for mapping different computation nodes into the same complex processing element. The processing elements which use the minimal number of building blocks are derived automatically from the computations of the different nodes. Known design procedures for mapping algorithms onto array processors can be extended by this method to allow the mapping of dependence graphs wit... View full abstract»

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  • Automatic formal verification of systolic array designs

    Publication Year: 1991, Page(s):338 - 354
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    The authors have previously (1990) developed a new formalism, called systolic temporal arithmetic (STA), for formal specification and verification of systolic arrays at the array level. The formalism exploits systolic array attributes to produce elegant specification and effective formal design verification and is suitable to be combined with interval temporal logic for multilevel reasoning for se... View full abstract»

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