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Application Specific Array Processors, 1991. Proceedings of the International Conference on

Date 2-4 Sept. 1991

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Displaying Results 1 - 25 of 37
  • On the use of most significant bit first arithmetic on the design of high performance DSP chips

    Publication Year: 1991
    Cited by:  Papers (1)
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  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.91TH0382-2)

    Publication Year: 1991
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    Freely Available from IEEE
  • Introduction to system design: algorithms and parallel architectures

    Publication Year: 1991
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  • Parallel array architectures for motion estimation

    Publication Year: 1991 , Page(s): 214 - 235
    Cited by:  Papers (4)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (856 KB)  

    Motion estimation is one of the most computationally intensive tasks required in digital video compression. The authors propose parallelizable motion estimation algorithms with low computational cost for both sub-optimal and optimal motion estimation. For efficient optimal motion estimation, they develop theoretical bounds based on convexity to reduce the required operations. All algorithms are te... View full abstract»

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  • Transformation of systolic algorithms for interleaving partitions

    Publication Year: 1991 , Page(s): 56 - 71
    Cited by:  Papers (3)
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    A systematic method to map systolic problems onto multicomputers is presented. A systolic problem is a problem for which it is possible to design a systolic algorithm. This method selects and transforms the systolic algorithm into a parallel algorithm with high granularity. The communications requirements are reduced and the performance can be increased. The proposed scheme requires a classificati... View full abstract»

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  • The missing dimension in real-time signal processing architectures

    Publication Year: 1991 , Page(s): 104 - 115
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    This paper introduces work done at STAR Semiconductor over the last three years in simplifying the use of digital signal processing techniques. This work has been directed at creating a technology that can go from a block diagram description to the efficient coding of a generally programmable signal processor in a matter of minutes. To achieve this required the development of a new kind of DSP pro... View full abstract»

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  • Pipelining and transposing heterogeneous array circuits

    Publication Year: 1991 , Page(s): 263 - 277
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    This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimised by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on developing novel pipelined designs for parallel division. It is found that, for a field-programmable gate arr... View full abstract»

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  • Systolic architecture for adaptive eigenstructure decomposition based on simultaneous iteration method

    Publication Year: 1991 , Page(s): 485 - 495
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    Eigenstructure decomposition of correlation matrices is an important pre-processing stage in many modern signal processing applications. In an unknown and possibly changing environment, adaptive algorithms that are efficient and numerically stable as well as readily implementable in hardware for eigen decomposition are highly desirable. Most modern real-time signal processing applications involve ... View full abstract»

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  • The systematic design of a motion estimation array architecture

    Publication Year: 1991 , Page(s): 40 - 54
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    There are already good systematic design methodologies for the design of regular architectures starting from some algorithm description of an application. However, since the solution space of these methods can be quite large, heuristics must be built in the CAD tool that supports these design methodologies. The authors present the manual design of a motion estimation application using a systematic... View full abstract»

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  • GFLOPS: a general flexible linearly organized parallel structure for images

    Publication Year: 1991 , Page(s): 431 - 444
    Cited by:  Papers (3)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    This paper describes a design of a linear array for use in MIMD, SIMD, pipeline and SPMD modes of programming for image processing applications. It gives some results for an evaluation. A great variety of algorithms, from low level algorithms used for pixel operations to high level algorithms used for performing region treatments or eventually for symbolic processing, may be implemented on this un... View full abstract»

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  • Biological information signal processor

    Publication Year: 1991 , Page(s): 144 - 160
    Cited by:  Papers (22)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (748 KB)  

    The computation requirements for mapping and sequencing the human genome might soon exceed the capability of any existing supercomputer. The systolic array processor presented in this paper, called biological information signal processor (BISP), has the capability to satisfy the current and anticipated future computational requirements for performing sequence comparisons based on the T.F. Smith an... View full abstract»

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  • High speed implementation of 1-D and 2-D morphological operations

    Publication Year: 1991 , Page(s): 249 - 262
    Request Permissions | Click to expandAbstract | PDF file iconPDF (376 KB)  

    The design of a morphological processing system is presented, to be used in medical image enhancement and compression. The system consists of a gray scale dilation/erosion systolic array capable of video data rates. The architecture can be implemented with either one dimensional or two dimensional building blocks that accept raster scanned data and exhibits low latency and an optimal pipeline rate... View full abstract»

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  • A systolic algorithm for the triangular Stein equation

    Publication Year: 1991 , Page(s): 473 - 484
    Cited by:  Papers (1)
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    The authors solve the Stein equation X+AXB=C, with A and B upper triangular matrices, by means of a bidimensional systolic array processor, independent of problem size. The problem is decomposed into two basic subproblems: the solution of an upper triangular system and a GAXPY operation. They obtain a size-dependent systolic algorithm by means of an appropriate chaining of the solutions of these s... View full abstract»

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  • Mapping different node types of dependence graphs into the same processing element

    Publication Year: 1991 , Page(s): 72 - 86
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    This paper presents a method for mapping different computation nodes into the same complex processing element. The processing elements which use the minimal number of building blocks are derived automatically from the computations of the different nodes. Known design procedures for mapping algorithms onto array processors can be extended by this method to allow the mapping of dependence graphs wit... View full abstract»

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  • A defect tolerant systolic array implementation for real time image processing

    Publication Year: 1991 , Page(s): 25 - 39
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    An advanced defect tolerant systolic array implementation of the 2D convolution algorithm for real-time image processing applications is presented. The chip contrasts with available convolution chips by the maximum kernel size of two hundred and fifty-six taps, the ability to convolve one video signal with up to four independent coefficient masks, support of adaptive filtering, on-chip delay lines... View full abstract»

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  • Parallel strong orientation on a mesh connected computer

    Publication Year: 1991 , Page(s): 199 - 211
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    The author presents a solution for the following problem: given an undirected bridgeless graph G=(V, E), find an orientation of each edge such that the resulting directed graph is strongly connected. He assumes the input graph to be given as an adjacency matrix stored in the processors of a mesh connected processor array such that each processor contains one entry. The a... View full abstract»

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  • Implementation of a VLSI polynomial evaluator for real-time applications

    Publication Year: 1991 , Page(s): 13 - 24
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB)  

    Fast evaluation of polynomials is a major goal of computer science, since any continuous function may be approximated as accurately as desired by a polynomial. For instance, most part of current computers evaluate elementary functions using polynomial or rational approximations. J. Duprat and J.M. Muller (1988) presented a new operator, a polynomier, suitable for VLSI implementation, and specifica... View full abstract»

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  • Consistency in dataflow graphs

    Publication Year: 1991 , Page(s): 355 - 369
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    This paper describes an analytical model for the behavior of dataflow graphs with data-dependent control flow. The number of tokens produced or consumed by each actor is given as a symbolic function of the Booleans in the system. Long term averages can be analyzed to determine consistency of token flow rates, which in turn determines whether memory requirements are bounded. Short-term behavior can... View full abstract»

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  • CAPMA: a content-addressable pattern match architecture for production systems

    Publication Year: 1991 , Page(s): 236 - 248
    Cited by:  Papers (1)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (468 KB)  

    CAPMA is an efficient partially parallel pattern match architecture used to speed up the execution time of match process of a production system. The algorithm fully exploits the advantages of content-addressable memories (CAMs) not only to buffer the working memory elements, but also to support the functions for evaluating interconditions among patterns in the left-hand sides (LHSs) of productions... View full abstract»

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  • A wave digital filter three-port adaptor with fine grained pipelining

    Publication Year: 1991 , Page(s): 116 - 128
    Cited by:  Papers (4)
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    A VLSI architecture for implementing wave digital filter three-port adaptors is described. The design presented general one and can be used to construct RLC ladder filters. High sampling rates are obtained through a combination of fine grained pipelining and most significant bit first arithmetic. The resulting circuit is highly regular and for the most part consists of simple carry save adders View full abstract»

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  • Mapping FIR filtering on systolic rings

    Publication Year: 1991 , Page(s): 87 - 101
    Cited by:  Papers (2)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    During the past decade, systolic arrays have been designed for a wide variety of scientific applications, which are based on highly parallel linear system manipulations. Partitioning and mapping of systolic algorithms has been a key issue for real implementations, in terms of both cost and manageability. The authors demonstrate the mapping of triangular systolic array algorithms onto a one-dimensi... View full abstract»

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  • Parallel digital implementations of neural networks

    Publication Year: 1991 , Page(s): 162 - 176
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (624 KB)  

    The paper reviews implementations of neural networks on parallel digital machines. The connectionist neural networks models are discussed from the point of view of their computational characteristics. The levels of parallelism available in the models and the factors affecting their performance of the models on the parallel machines are presented. Several mapping methodologies applicable to neural ... View full abstract»

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  • Synthesizing systolic arrays: some recent developments

    Publication Year: 1991 , Page(s): 372 - 386
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (676 KB)  

    Methods for synthesizing systolic arrays from uniform DAGs are well understood. The idea is to extract from the original sequential algorithm a dependence graph where all incoming arcs to a given node come from a fixed-size neighborhood, so that dependencies are local. Space-time transformations are then used for scheduling the DAG (timing function) and mapping nodes onto physical processors (allo... View full abstract»

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  • Processor clustering for the design of optimal fixed-size systolic arrays

    Publication Year: 1991 , Page(s): 402 - 413
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (492 KB)  

    The authors have shown in their previous work that processor-clustering is a key operation in the design of problem-size independent systolic/wavefront arrays. Indeed, the processor clustering techniques (called passive-clustering and active-clustering) can not only be used to reduce the size of an array to a constant, but also to achieve the design objectives such as transforming inefficient arra... View full abstract»

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  • A 40 megasample IIR filter chip

    Publication Year: 1991 , Page(s): 416 - 430
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (668 KB)  

    The design of a high performance bit parallel second order IIR filter chip is described. The chip in question is highly pipelined, uses most significant bit first arithmetic and consists mainly of arrays of simple carry save adders. It has been fabricated in 1.5 um double level metal CMOS technology, accepts 12 bit input data and coefficient values and can operate at up to 40 megasamples per secon... View full abstract»

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