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Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on

Date 8-10 Sept. 1997

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Displaying Results 1 - 25 of 89
  • SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest [Front Matter and Table of Contents]

    Publication Year: 1997
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    Freely Available from IEEE
  • Progress in predicting transient diffusion

    Publication Year: 1997 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB)  

    Transient diffusion accounts for the majority of profile displacement in many modern processes. The last few years have seen considerable progress in understanding this anomalous diffusion, and predictive models have already been deployed in process development. Nevertheless, the evolving reduction in junction depth continues to challenge modeling capability. This work critically re-examines the theoretical basis of the present models and explores their limitations. View full abstract»

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  • Historical perspective and recent developments of hot-carrier generation modeling for device analysis

    Publication Year: 1997 , Page(s): 5 - 8
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (430 KB)  

    The paper presents an historical perspective of the efforts devoted in the past years to achieve efficient but increasingly accurate modeling of hot carrier generation in MOS devices. In addition, new modeling problems raised by recent experiments, and related to the effects of power supply and geometry down-scaling will be discussed. View full abstract»

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  • Recent advances in Krylov-subspace solvers for linear systems and applications in device simulation

    Publication Year: 1997 , Page(s): 9 - 16
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB)  

    The computational cost of many simulations is dominated by the solution of large, sparse systems of linear equations. Krylov-subspace methods, especially when combined with suitable preconditioning, are powerful algorithms for the iterative solution of such linear systems. One of the features of Krylov-subspace methods is that the matrix of the linear system is only used in the form of matrix-vector products, and thus sparsity is naturally exploited. In recent years, there have been many advances in Krylov-subspace methods for the solution of large, sparse, nonsymmetric linear systems. In this paper, we survey some of these recent advances especially in the area of Lanczos-based methods. We also discuss the use of state-of-the-art Krylov-subspace methods in device simulation. View full abstract»

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  • Application of TCAD to designing advanced DRAM and logic devices

    Publication Year: 1997 , Page(s): 17 - 20
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (393 KB)  

    Typical aspects of applying TCAD to designing advanced DRAM and logic devices are presented focusing on transistors. For prediction at the start of developing new devices, global models which fit marginally to varieties of transistors are used. After preliminary experiments of the new devices, model parameters are best fit to the experimental results using local parameter extractions. These local models are used for process optimization of the devices under development. Response surface models are extensively used with additional information of weighted optimization and statistical analysis. Fast and compact contributions to circuit design are promised by response surfaces of SPICE parameters. A new concept of response surface chains (RSC) is introduced to make the best use of simulated results. Support of TCAD tools to this concept is a key technology for concurrent and real-time development of the advanced devices. View full abstract»

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  • Asymmetry in effective-channel length of n- and p-MOSFETs

    Publication Year: 1997 , Page(s): 21 - 24
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB)  

    We have shown that there is a fundamental asymmetry in the effective-channel lengths of n-FET and p-FET devices. Basic differences in electron and hole transport give rise to a larger effective channel length for n-FETs. This can also be observed through a comparison of the device sheet resistance where the relative difference in channel to source/drain mobility leads to distinct sheet rho patterns near the metallurgical junction. Recent investigations in current flow patterns in the source/drain regions (to be reported elsewhere) has further substantiated these findings. View full abstract»

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  • VLSI performance metric based on minimum TCAD simulations

    Publication Year: 1997 , Page(s): 25 - 28
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    A new approach to performance metrology and qualification of digital VLSI processes with TCAD simulations is proposed. The method yields performance data on the system level directly from raw electrical device data obtained with a minimum set of device simulations. The key performance and qualification parameters are identified, pointing out the differences between these and traditional device performance metrics, and the methods to determine these parameters from the device data are described. View full abstract»

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  • Layout optimization of ESD protection TFO-NMOS by two-dimensional device simulation

    Publication Year: 1997 , Page(s): 29 - 31
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (246 KB)  

    The first-pass design methodology of ESD protection TFO-NMOS device has been developed using 2D process and device simulation. The ranges of optimum layout parameters have been suggested by investigating the current-to-failure and time-to-failure profiles extracted from 2D electro-thermal mixed-mode device simulation results. View full abstract»

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  • Tilt angle effect on optimizing HALO PMOS performance

    Publication Year: 1997 , Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (454 KB)  

    Deep submicrometer MOS devices often need special structures to optimize their performance. The HALO structure, or pocket implant, is usually adopted for PMOS to reduce off-state leakage current and enhance on-state drive current. This paper studies the tilt angle effect of HALO implant on device performance. It is found that devices with higher tilt angle feature reduced body effect and increased source resistance as compared to those with low tilt angle, and the effect of resistance and body effect compensates each other, resulting equivalent DC performance for different tilt angles. We suggest that based on this equivalence of DC performance, a high tilt angle should be adopted for HALO devices due to their lower junction capacitance. View full abstract»

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  • Analysis of channel-width effects in 0.3 /spl mu/m ultra-thin SOI NMOSFETs

    Publication Year: 1997 , Page(s): 37 - 40
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    Experiment-based new phenomena, such as LIF energy and channel width effects in ultra-thin (T/sub Si/=700 /spl Aring/) 0.3 /spl mu/m SOI NMOSFETs, are analysed using TCAD tools. The relatively higher doping profile along with the width direction silicon edge can improve the breakdown characteristics (i.e., BV/spl cong/9 V at W/L=0.4 um/0.3 um). This effect, which does not coincide with typical BV characteristics in very-small SOIs, is caused by the reduction of the impact ionization rate due to the doping and geometric effects of the silicon edge as the channel-width becomes narrower. It implies that very small SOI NMOSFETs can be well adopted for the ultra-high density DRAM cells when an optimised doping profile is provided. View full abstract»

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  • A characterization tool for current degradation effects of abnormally structured MOS transistors

    Publication Year: 1997 , Page(s): 41 - 43
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB)  

    A new modeling methodology and an environment for abnormally structured MOS transistors we presented. This methodology uses a three-dimensional device simulator and a curve fitting method to characterize the current degradation effects by extracting the parasitic diffusion resistance from abnormal transistors. We have applied this methodology to 0.5 /spl mu/m process. Within 5% error, an overall I-V curve fit for various device shapes and bias conditions is achieved. This methodology improves the accuracy of circuit-level simulation. View full abstract»

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  • An experimental methodology for the estimation of spatially correlated parametric yield in thin film devices

    Publication Year: 1997 , Page(s): 45 - 48
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (478 KB)  

    In this paper we present an experimental methodology for parametric yield estimation that accounts for spatial correlations between features of the same device at specific wafer locations. Each device feature is representative of a device parameter that must fit with a specific tolerance box and may be influenced by several steps of the manufacturing process. If the process how is known and each of its steps is characterized in a spatially correlated manner, the feature pointwise probability density functions (PDFs) can be accurately reconstructed from the processing step pointwise PDFs. This method thus permits the estimation of pointwise device yield more accurately than the common multilevel (run, wafer, die) averaging approach. Because spatially correlated phenomena is subject to both random and systematic nonuniformities, the pointwise step (PDFs) are determined by a decomposition process that separates the systematic and random error components. The systematic PDFs are determined from interpolation functions representing the spatial variations across the entire wafer lot, and the random PDFs are approximated using a combination of principle component analysis and factor analysis with a few uncorrelated random variables valid for the entire lot. View full abstract»

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  • Modeling stress effects on thin oxide growth kinetics

    Publication Year: 1997 , Page(s): 49 - 52
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (327 KB)  

    This paper describes the development of a thin oxide growth model, which includes stress dependencies and, hence, allows the modeling of non-planar structures with thin oxides. View full abstract»

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  • Mechanical stress modeling for silicon fabrication processes

    Publication Year: 1997 , Page(s): 53 - 55
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    Two finite element methods are implemented to investigate localized mechanical stress fields generated during multiple stages of silicon IC fabrication. The boundary loading method (BL) uses the oxide interface stresses as a boundary condition for the substrate solution. In the fully integrated method (FI), the strains in substrate are calculated along with the oxide stress computation. Both of the methods can be used to couple stresses generated by oxidation volume expansion to strains present from other sources such as thermal expansion, dopants, and intrinsic film stresses. They are then evaluated on computational intensiveness and in stress solution variation. It is found that the BL method computes nearly the same oxide solution as the FI method and the oxide solution corresponds very well in the oxide and surface films for a LOCOS process. View full abstract»

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  • Photoresist process optimization for defects using a rigorous lithography simulator

    Publication Year: 1997 , Page(s): 57 - 60
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB)  

    Particulate contamination in photoresist is a major source of yield loss for CMOS processes. Yield loss due to such contamination is controllable by improved filtering. This paper explores the relation between particle size and line spacing for an i-line lithography process using a calibrated defect simulator. View full abstract»

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  • Three-dimensional profile evolution under low sticking coefficient

    Publication Year: 1997 , Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (395 KB)  

    This paper describes a careful numerical study of the effects of low sticking coefficient for two and three dimensional structures. The model for reflection is a cosine re-emission distribution with no dependence on the distribution of incoming particles. We calculate the limiting case for several different initial topologies. We conclude that the limiting profile can not in general be replaced by an isotropic deposition term, and demonstrate the effects of low sticking coefficient on complex structures. View full abstract»

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  • A method for die-scale simulation of CMP planarization

    Publication Year: 1997 , Page(s): 65 - 68
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB)  

    Chemical-Mechanical Polishing (CMP) is well known for its planarization capability. However, it suffers from long-range non-uniformity due to its sensitivity to pattern density. This paper shows that, by using basic building blocks and formulation techniques, CMP simulation can be done on a large dimension, namely the whole die. View full abstract»

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  • CMP profile simulation using an elastic model based on nonlinear contact analysis

    Publication Year: 1997 , Page(s): 69 - 72
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    Recently, simulation of Chemical Mechanical Polishing (CMP) is becoming more important because planarity and uniformity which are dependent on many dynamic factors are difficult to control. In this paper, a profile simulation environment based on the linear elastic material and nonlinear contact analysis that considers equipment parameters, such as pad hardness, thickness and down pressure is presented. In transient CMP simulation using the elastic model, the contact stress on the wafer surface is the dominant factor in polishing rate during the CMP process. The profiles of CMP simulation agree well with the measured data. This simulation can be used to optimize the CMP process and to generate design rules for filling dummy patterns which are used to improve planarity. View full abstract»

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  • A model of {311} defect evolution based on nucleation theory

    Publication Year: 1997 , Page(s): 73 - 76
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (407 KB)  

    A new model of {311} defect evolution is proposed. The defects are characterized by their mean size and their concentration. The flux between free interstitials and {311} defects is described by an expression obtained by extending the classical theory of nucleation. The model is shown to agree well with the experimental data on {311} defect evolution of Eaglesham et al. and with the boron TED data of Chao et al. View full abstract»

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  • Physical modeling of transient enhanced diffusion and dopant deactivation via extended defect evolution

    Publication Year: 1997 , Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (377 KB)  

    Simulation of ion implant annealing requires adequate models for a range of processes, including deactivation of dopants and transient enhanced diffusion. It is now well understood that extended defects ({311} defects, dislocation loops, BICs, arsenic precipitates, etc.) play a central role in all these processes. We have developed a fundamental model which can account for the behavior of a broad range of extended defects, as well as their interactions with each other. We have successfully applied and parameterized our model to a range of systems and conditions, some of which are presented in this paper. We also present how these processes couple with each other, as well as standard coupled dopant diffusion, by terms of a simple MOSFET structure. View full abstract»

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  • A new diffusion algorithm during oxidation which can handle both phosphorus pile-up and boron segregation at Si-SiO/sub 2/ interface

    Publication Year: 1997 , Page(s): 81 - 84
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (338 KB)  

    A new simulation algorithm during oxidation which can handle both the phosphorus (P) pile-up and the boron (B) segregation has been proposed. In this algorithm, an interlayer (IL) is placed at Si-SiO/sub 2/ interface in order to have P pile-up. The interface is moved according to the Si consumption during a time step and a new interface is generated at the end of the consumed Si region. A region between an old and a new IL is defined as a transition layer (TL). A diffusion equation is solved inside the TL using local effective diffusion constants in order to fully redistribute the impurities. By using this "diffusion in the TL", the P piled up in the old IL may move through the TL and re-piles up into the new IL, and B segregation can be simulated accurately. The V/sub th/-V/sub sub/ characteristics of an actual buried channel pMOSFET which is simulated using the proposed algorithm agrees well with the experiment. View full abstract»

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  • Modeling the effect of phosphorus dose loss at the SiO/sub 2/ interface on CMOS device characteristics

    Publication Year: 1997 , Page(s): 85 - 88
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    A model for the phosphorus dose loss effect is developed and incorporated into the process simulator PROPHET. The dose loss model is applied consistently with the Transient Enhanced Diffusion and the segregation models in PROPHET to provide doping profiles used by the device simulator PADRE in simulations of NMOS, PMOS, and isolation structures for actual VLSI technologies. Comparison of the simulated and measured device characteristics and their dependence on substrate bias and structure geometry shows good agreement, and furthermore highlights the importance of the dose loss phenomenon in these structures. View full abstract»

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  • Simulation of transient enhanced diffusion of boron induced by silicon self-implantation

    Publication Year: 1997 , Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB)  

    The time, dose, and energy dependence of boron transient enhanced diffusion (TED) induced by silicon self-implantation has been simulated taking into account the time evolution of self-interstitial clusters. The kinetics of cluster dissolution and growth are combined with the kick-out mechanism for boron diffusion, and the decrease in the cluster evolution rate with time is taken into account. Using a unified set of parameters, the simulation explains some complex characteristics of TED; that is, the enhancement is independent of the implant dose at short annealing times, while it increases with increasing implant dose after longer annealing times. In addition, the implant energy dependence of TED can be explained by the proximity of the damage to the surface. View full abstract»

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  • Solution of 1-D Schrodinger and Poisson equations double gate SOI MOS

    Publication Year: 1997 , Page(s): 93 - 96
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB)  

    In this paper the self-consistent solution of Schrodinger and Poisson equations is applied to single- and double-gate SOI MOS structures. The reasons for possible advantages related to the presence of the two symmetric gates in the latter case are investigated. View full abstract»

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  • Density-gradient simulations of quantum effects in ultra-thin-oxide MOS structures

    Publication Year: 1997 , Page(s): 97 - 100
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    The density-gradient approach to quantum transport theory is used to model the C-V characteristics of MOS devices with ultra-thin gate oxides. The method is shown to provide a physics-based approach the works well in all bias regimes and is simple enough for engineering applications. View full abstract»

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