1991 Proceedings, International Conference on Wafer Scale Integration

29-31 Jan. 1991

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  • 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9)

    Publication Year: 1991
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    Freely Available from IEEE
  • A variable domain approach to reconfiguration of WSI processor arrays

    Publication Year: 1991, Page(s):134 - 140
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    A novel reconfiguration algorithm for WSI (wafer scale integration) processor arrays using the concept of a variable domain is discussed. Variable domain is decided based on a fault distribution. The algorithm utilizes fault distribution information in the global assignment phase as well as in the local assignment phase. The concept of variable domain used in the algorithm overcomes the weakness o... View full abstract»

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  • A rapid prototype wafer scale system design for signal and data processing

    Publication Year: 1991, Page(s):68 - 74
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (456 KB)

    The authors describe a WSI (wafer scale integration) rapid prototype system design project. Applications which can be implemented as WSI systems are being developed at three universities (alpha sites). A single WSI design is being developed which can be rapidly restructured to meet the system requirements of each university. A system design verification approach that involves a common CAD (compute... View full abstract»

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  • Large area defect-tolerant tree architectures

    Publication Year: 1991, Page(s):127 - 133
    Cited by:  Papers (2)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (268 KB)

    The authors study the problem of designing large-area defect-tolerant tree architectures under the fault model that each processor, switch, and wire may be defective with independent constant probability. Using expander graphs, it is shown that, for any given constant 0<h<1, there is a design of n processors with layout area O(n) such that the harvest rate... View full abstract»

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  • Limitations to the size of single-chip electronic neural networks

    Publication Year: 1991, Page(s):61 - 67
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    The authors analyze and quantify the design tradeoffs which will limit the size of single-chip analog neural networks implemented using standard CMOS technology. Issues investigated include the limits imposed by the neural network architectures themselves, and the related effects of processing variations and defects on the ultimate size of manufacturable neural systems. It is shown that neural net... View full abstract»

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  • Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

    Publication Year: 1991, Page(s):120 - 126
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. ... View full abstract»

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  • Defect tolerance and yield for a wafer scale FFT processor system

    Publication Year: 1991, Page(s):54 - 60
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    A wafer scale system for frame-by-frame computation of the fast Fourier-transform (FFT) is described. It is based on an eight-point FFT wafer design, which uses two types of cells, a multiply-subtract-add (MSA) cell and a coefficient ROM cell. Systematic repetition of these cells and the interconnect forms the physical wafer. The cells are designed for high performance and testability. For success... View full abstract»

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  • Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets

    Publication Year: 1991, Page(s):113 - 119
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (372 KB)

    A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in... View full abstract»

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  • Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation

    Publication Year: 1991, Page(s):47 - 53
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    Presents a novel approach for concurrent error detection and location in homogeneous VLSI/WSI (wafer scale integration) architectures for the computation of the complex N-point fast Fourier transform. The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analyzed with respect to functional and physical faults. ... View full abstract»

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  • WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

    Publication Year: 1991, Page(s):270 - 276
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (368 KB)

    The evolution of silicon to 0.25-μm technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realization of future distributed systems. Multichip sy... View full abstract»

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  • Self-reconfigurable algorithm of WSI sorting network

    Publication Year: 1991, Page(s):249 - 255
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (308 KB)

    The authors present a self-reconfigurable algorithm for a hierarchically redundant WSI (wafer scale integration) sorting network. This WSI sorting network consists of a mesh interconnection and a modified bitonic sorter with spare cells. The fault tolerance performance of the WSI sorting network using the self-reconfigurable algorithm is discussed. It is confirmed that the hierarchical redundancy ... View full abstract»

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  • Structures for a configuration and self-configuration of WSI systems with a low degree of regularity

    Publication Year: 1991, Page(s):104 - 111
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    For WSI (wafer scale integration) systems with a low degree of regularity, a design strategy is investigated which features a self-configuration. Redundant arrangements of modules as well as implementations of subsidiary circuitry are presented. They provide a multiple defect tolerance even for central circuitry such as system control, test, and configuration circuitry. The components are implemen... View full abstract»

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  • A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization

    Publication Year: 1991, Page(s):40 - 46
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    A novel MIMD (multiple instruction multiple data) based multiprocessor architecture consisting of multiple processing elements (PE) has been developed for real-time image processing. Each PE contains an arithmetic processing unit adapted to convolution-like low-level operations and a high-level and control processor. A high-speed random access to local image data is provided by two local input mem... View full abstract»

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  • Practical considerations for WSI based systems

    Publication Year: 1991, Page(s):321 - 327
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (380 KB)

    The author examines some aspects of the Westinghouse WSI (wafer scale integration) development effort. The status of device production efforts is summarized, important packaging-oriented practical issues are discussed, and a particular approach to WSI packaging is presented. Some critical issues associated with overall circuit density, power distribution, signal connections, and heat removal are i... View full abstract»

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  • A generalized Poisson based model for defect spatial distribution in WSI

    Publication Year: 1991, Page(s):149 - 155
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (296 KB)

    Discusses the use of the modified generalized Poisson binomial limit in modeling defect spatial distribution in WSI (wafer scale integration) and large-area VLSI chips. This model demonstrates the usefulness of generalized Poisson distributions for effectively taking into account the issues of the distribution of clusters and cluster sizes. The strength of the proposed model lies in its simplicity... View full abstract»

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  • Physical design of the MUSE wafer-scale circuit

    Publication Year: 1991, Page(s):5 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (272 KB)

    MUSE is a wafer-scale adaptive nulling processor which is being implemented using the restructurable VLSI techniques and design tools. The authors describe the physical design of the wafer with emphasis on interconnect redundancy and design for testability during the restructuring process. Power distribution and the wafer floorplan and packaging are also discussed View full abstract»

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  • Design and parallel testing of wafer scale linear arrays with high harvest rates

    Publication Year: 1991, Page(s):285 - 291
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (304 KB)

    Design for high harvest rates and parallel on-wafer diagnosis of linear arrays are described. A generalized loop-based approach to defect-tolerant wafer scale linear arrays is presented. In terms of harvest rate, the loop-based approach is significantly better than the traditional spiral approaches. Similar to the spiral approaches, the loop-based approach guarantees a fixed propagation delay betw... View full abstract»

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  • WSI interconnect issues: practical experience gained on the WASP project

    Publication Year: 1991, Page(s):263 - 269
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (356 KB)

    The problems of external interfacing and internal interconnection for WSI (wafer scale integration) devices are considered. In particular, the WASP (WSI associative string processor) 2A device is examined in detail, and practical results are presented. Analysis of the experimental on-wafer interconnection included on WASP 2A has shown that, given simple layout precautions, a high yield can be obta... View full abstract»

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  • VHDL-based design and analysis of defect tolerant VLSI/WSI array architectures

    Publication Year: 1991, Page(s):163 - 169
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (320 KB)

    Presents an integrated computer-aided design environment, the VAR (VHDL-based array reconfiguration) system, for the design, diagnosis, reconfiguration, simulation, and evaluation of an array architecture described in VHDL. VAR allows one to study fault diagnosis and reconfiguration algorithms by inserting user-defined faults into the array and then locating the faulty processing elements as well ... View full abstract»

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  • The evolution of DRAM technology towards WSI

    Publication Year: 1991, Page(s):243 - 247
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (180 KB)

    Issues connected with the evolution of dynamic random-access memory (DRAM) technology towards wafer scale integration (WSI) are examined. It is pointed out that as one moves towards submicron technologies, fundamental physical, electrical, and processing limits are being encountered, and it is becoming clear that this trend cannot continue. This phenomenon is most clearly demonstrated by the devel... View full abstract»

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  • An overview and analysis of 3D WSI

    Publication Year: 1991, Page(s):223 - 235
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (692 KB)

    The author reviews the early trends in 3-D WSI (wafer scale integration) and examines recent breakthroughs in technology to assess the viability of 3-D. It is concluded that this option is rich with possibility for the designer. However, not every architecture can benefit equally from this packaging approach. An attempt is made to quantify this impact by computing an average wire-shortening effect... View full abstract»

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  • Silicon substrate test structures for hybrid wafer scale technology

    Publication Year: 1991, Page(s):185 - 191
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    The authors explore the variety of test structures that may be used in the fabrication and assembly of silicon substrate multichip modules (MCMs) that aim at wafer scale complexity levels, with particular reference to their technological role. It is pointed out that a comprehensive set of test structures has been devised that provides yield, performance, and reliability information for silicon sub... View full abstract»

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  • Excimer laser formed vertical links of standard CMOS double-level metallizations

    Publication Year: 1991, Page(s):207 - 213
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (292 KB)

    Excimer-laser-formed vertical links between two metallization levels are demonstrated on special test chips, fabricated by ES2 in a standard CMOS process. Yield is 100% using link structures of 20 μm×20 μm and 14 μm×14 μm linear dimension and two identical laser pulses. Mean contact resistance is less than 200 Ω. A new test chip is built using sandwich layers for meta... View full abstract»

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  • Combining switch and site yields for soft-configurable WSI

    Publication Year: 1991, Page(s):97 - 103
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (284 KB)

    The configuration requirements of a soft-configurable pipelined memory are described. Monte Carlo simulations show that wafer yield dependence on high switch yields can be reduced substantially using switch path bypasses and/or spare columns. These simulations combine the effects of switch and site failures in ways that cannot easily be captured using simpler analytic models, due to interdependenc... View full abstract»

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  • A reconfigurable cube-connected cycles architecture for wafer scale integration

    Publication Year: 1991, Page(s):33 - 39
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (384 KB)

    Proposes a novel reconfigurable architecture for the cube-connected cycles (CCC) implemented by wafer scale integration (WSI) technology. This design is aimed at maintaining the full rigid structure of the CCC in the presence of manufacturing defects. The spare PEs (processing elements), which are added to every building block of the system, can be shared by the PEs in immediate nearby blocks or b... View full abstract»

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