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Wafer Scale Integration, 1991. Proceedings., [3rd] International Conference on

Date 29-31 Jan. 1991

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  • 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9)

    Publication Year: 1991
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    Freely Available from IEEE
  • Wafer scale integration-a technology whose time has come

    Publication Year: 1991, Page(s):328 - 330
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The criteria which every new technological advance needs to satisfy before it can become accepted into the mainstream of product development are identified. it is then suggested that one company's wafer scale integration (WSI) now satisfies these criteria; it meets the needs of the intermediate storage market, and it is cost effective to manufacture because it provides a way for semiconductor manu... View full abstract»

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  • Reconfiguring processor arrays using multiple-track models

    Publication Year: 1991, Page(s):307 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors study a 3-track-1-spare model that has three tracks along each channel and one spare row or column along each boundary. It is shown that the model uses the spare processors very efficiently; specifically, it is proved that a 3-track-1-spare model can support any set of nonintersecting compensation paths. This provides theoretical justification of the observations made in the literature... View full abstract»

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  • Multiple voting systolic array

    Publication Year: 1991, Page(s):26 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant archi... View full abstract»

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  • A generalized Poisson based model for defect spatial distribution in WSI

    Publication Year: 1991, Page(s):149 - 155
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Discusses the use of the modified generalized Poisson binomial limit in modeling defect spatial distribution in WSI (wafer scale integration) and large-area VLSI chips. This model demonstrates the usefulness of generalized Poisson distributions for effectively taking into account the issues of the distribution of clusters and cluster sizes. The strength of the proposed model lies in its simplicity... View full abstract»

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  • Yield enhancement of wafer scale integrated arrays

    Publication Year: 1991, Page(s):178 - 184
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    In an approach proposed by V.P. Kumar et al. (see Proc. IEEE Int. Conf. on Computer-Aided Design, p.226-9, Nov. 1989) for the yield enhancement of programmable gate arrays (PGAs), an initial placement of a circuit is first obtained using a standard technique such as simulated annealing on a defect-free PGA. In the next step this placement is reconfigured so that the circuit is mapped onto the defe... View full abstract»

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  • A rapid prototype wafer scale system design for signal and data processing

    Publication Year: 1991, Page(s):68 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors describe a WSI (wafer scale integration) rapid prototype system design project. Applications which can be implemented as WSI systems are being developed at three universities (alpha sites). A single WSI design is being developed which can be rapidly restructured to meet the system requirements of each university. A system design verification approach that involves a common CAD (compute... View full abstract»

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  • A self-testing and self-diagnostic systolic array cell for signal processing

    Publication Year: 1991, Page(s):75 - 81
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A built-in self test (BIST) method for a systolic array controller chip/multiplier-accumulator chip (SAC/MAC) was used to generate the signatures for all combinational blocks of each cell in parallel. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a pre... View full abstract»

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  • Interconnect and cell redundancy tradeoffs for WSI: an FFT case study

    Publication Year: 1991, Page(s):314 - 320
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The authors describe the results of an investigation into the relationship between cell redundancy, yield, and interconnect area for WSI (wafer scale integration) designs. A general analysis framework is presented which allows algorithmic computation of the optimum amount of redundancy from an area efficiency standpoint. The results of this theoretical study were applied to the case study of an 8-... View full abstract»

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  • Large area defect-tolerant tree architectures

    Publication Year: 1991, Page(s):127 - 133
    Cited by:  Papers (2)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The authors study the problem of designing large-area defect-tolerant tree architectures under the fault model that each processor, switch, and wire may be defective with independent constant probability. Using expander graphs, it is shown that, for any given constant 0<h<1, there is a design of n processors with layout area O(n) such that the harvest rate... View full abstract»

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  • The evolution of DRAM technology towards WSI

    Publication Year: 1991, Page(s):243 - 247
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Issues connected with the evolution of dynamic random-access memory (DRAM) technology towards wafer scale integration (WSI) are examined. It is pointed out that as one moves towards submicron technologies, fundamental physical, electrical, and processing limits are being encountered, and it is becoming clear that this trend cannot continue. This phenomenon is most clearly demonstrated by the devel... View full abstract»

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  • Fault tolerant characteristics of the linear array architecture for WSI implementation of neural nets

    Publication Year: 1991, Page(s):113 - 119
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A novel digital architecture supporting implementation of feedforward, multilayered artificial neural networks is presented. Based on a switched bus array philosophy, particular care is taken to minimize area requirements while maximizing throughput and parallelism. The architecture is well suited to support, with minimal additional changes, fault/defect tolerance with respect to faults located in... View full abstract»

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  • An 80 MHz digital signal processing multichip module made with the General Electric high density interconnect technology

    Publication Year: 1991, Page(s):192 - 198
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    A unique packaging and interconnect technology was used to build a multichip, four CPU element, pipeline parallel processing computer module using Texas Instruments TMS320C25 digital signal processors and companion circuits. The technology allowed a greater than fifteen-fold reduction in area over conventional chip packages mounted with printed-circuit-board methods. Reduced interconnect capacitan... View full abstract»

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  • Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation

    Publication Year: 1991, Page(s):47 - 53
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Presents a novel approach for concurrent error detection and location in homogeneous VLSI/WSI (wafer scale integration) architectures for the computation of the complex N-point fast Fourier transform. The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analyzed with respect to functional and physical faults. ... View full abstract»

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  • WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

    Publication Year: 1991, Page(s):270 - 276
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The evolution of silicon to 0.25-μm technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realization of future distributed systems. Multichip sy... View full abstract»

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  • A reconfigurable cube-connected cycles architecture for wafer scale integration

    Publication Year: 1991, Page(s):33 - 39
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Proposes a novel reconfigurable architecture for the cube-connected cycles (CCC) implemented by wafer scale integration (WSI) technology. This design is aimed at maintaining the full rigid structure of the CCC in the presence of manufacturing defects. The spare PEs (processing elements), which are added to every building block of the system, can be shared by the PEs in immediate nearby blocks or b... View full abstract»

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  • Yield evaluation of WSI parallel systems

    Publication Year: 1991, Page(s):156 - 162
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The authors propose a methodology for estimating the yield of WSI (wafer scale integration) parallel systems efficiently and accurately by taking advantage of the fact that most of the parallel systems have recursive structures by nature. This methodology evaluates yield by means of a recursive approach without enumerating all fixable states. It is often possible to derive the yield of WSI paralle... View full abstract»

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  • A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization

    Publication Year: 1991, Page(s):40 - 46
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A novel MIMD (multiple instruction multiple data) based multiprocessor architecture consisting of multiple processing elements (PE) has been developed for real-time image processing. Each PE contains an arithmetic processing unit adapted to convolution-like low-level operations and a high-level and control processor. A high-speed random access to local image data is provided by two local input mem... View full abstract»

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  • Rotary spare replacement redundancy for tree architecture WSIs

    Publication Year: 1991, Page(s):83 - 89
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    The author proposes rotary spare replacement redundancy (RSRR) for defect tolerance in tree architecture WSIs. The main feature of the RSRR is that it can be applied in element groups of a subroot element and its leaf elements on every neighboring two stages, using a simple switching scheme based on k-out-of-n redundancy. Especially, it can be applied to hierarchical redundancy, ... View full abstract»

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  • Excimer laser formed vertical links of standard CMOS double-level metallizations

    Publication Year: 1991, Page(s):207 - 213
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Excimer-laser-formed vertical links between two metallization levels are demonstrated on special test chips, fabricated by ES2 in a standard CMOS process. Yield is 100% using link structures of 20 μm×20 μm and 14 μm×14 μm linear dimension and two identical laser pulses. Mean contact resistance is less than 200 Ω. A new test chip is built using sandwich layers for meta... View full abstract»

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  • Practical considerations for WSI based systems

    Publication Year: 1991, Page(s):321 - 327
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The author examines some aspects of the Westinghouse WSI (wafer scale integration) development effort. The status of device production efforts is summarized, important packaging-oriented practical issues are discussed, and a particular approach to WSI packaging is presented. Some critical issues associated with overall circuit density, power distribution, signal connections, and heat removal are i... View full abstract»

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  • A variable domain approach to reconfiguration of WSI processor arrays

    Publication Year: 1991, Page(s):134 - 140
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A novel reconfiguration algorithm for WSI (wafer scale integration) processor arrays using the concept of a variable domain is discussed. Variable domain is decided based on a fault distribution. The algorithm utilizes fault distribution information in the global assignment phase as well as in the local assignment phase. The concept of variable domain used in the algorithm overcomes the weakness o... View full abstract»

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  • Self-reconfigurable algorithm of WSI sorting network

    Publication Year: 1991, Page(s):249 - 255
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors present a self-reconfigurable algorithm for a hierarchically redundant WSI (wafer scale integration) sorting network. This WSI sorting network consists of a mesh interconnection and a modified bitonic sorter with spare cells. The fault tolerance performance of the WSI sorting network using the self-reconfigurable algorithm is discussed. It is confirmed that the hierarchical redundancy ... View full abstract»

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  • Limitations to the size of single-chip electronic neural networks

    Publication Year: 1991, Page(s):61 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors analyze and quantify the design tradeoffs which will limit the size of single-chip analog neural networks implemented using standard CMOS technology. Issues investigated include the limits imposed by the neural network architectures themselves, and the related effects of processing variations and defects on the ultimate size of manufacturable neural systems. It is shown that neural net... View full abstract»

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  • Efficient reconfiguration algorithms for degradable VLSI/WSI arrays

    Publication Year: 1991, Page(s):120 - 126
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    A systematic method for reconfiguration in VLSI/WSI (wafer scale integration) arrays using the degradation approach for yield enhancement is presented. Based on the bipartite graph representation of faulty cells in a reconfigurable host array, the problem of finding a maximum fault-free target array is shown to be equivalent to finding a restricted independent set of vertices in the graph models. ... View full abstract»

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