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1991 Proceedings, International Conference on Wafer Scale Integration

29-31 Jan. 1991

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Displaying Results 1 - 25 of 47
  • 1991 Proceedings. International Conference on Wafer Scale Integration (Cat. No.91CH2943-9)

    Publication Year: 1991
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    Freely Available from IEEE
  • Limitations to the size of single-chip electronic neural networks

    Publication Year: 1991, Page(s):61 - 67
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors analyze and quantify the design tradeoffs which will limit the size of single-chip analog neural networks implemented using standard CMOS technology. Issues investigated include the limits imposed by the neural network architectures themselves, and the related effects of processing variations and defects on the ultimate size of manufacturable neural systems. It is shown that neural net... View full abstract»

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  • A reconfigurable cube-connected cycles architecture for wafer scale integration

    Publication Year: 1991, Page(s):33 - 39
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Proposes a novel reconfigurable architecture for the cube-connected cycles (CCC) implemented by wafer scale integration (WSI) technology. This design is aimed at maintaining the full rigid structure of the CCC in the presence of manufacturing defects. The spare PEs (processing elements), which are added to every building block of the system, can be shared by the PEs in immediate nearby blocks or b... View full abstract»

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  • Structures for a configuration and self-configuration of WSI systems with a low degree of regularity

    Publication Year: 1991, Page(s):104 - 111
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB)

    For WSI (wafer scale integration) systems with a low degree of regularity, a design strategy is investigated which features a self-configuration. Redundant arrangements of modules as well as implementations of subsidiary circuitry are presented. They provide a multiple defect tolerance even for central circuitry such as system control, test, and configuration circuitry. The components are implemen... View full abstract»

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  • Interconnect and cell redundancy tradeoffs for WSI: an FFT case study

    Publication Year: 1991, Page(s):314 - 320
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The authors describe the results of an investigation into the relationship between cell redundancy, yield, and interconnect area for WSI (wafer scale integration) designs. A general analysis framework is presented which allows algorithmic computation of the optimum amount of redundancy from an area efficiency standpoint. The results of this theoretical study were applied to the case study of an 8-... View full abstract»

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  • Defect tolerance and yield for a wafer scale FFT processor system

    Publication Year: 1991, Page(s):54 - 60
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A wafer scale system for frame-by-frame computation of the fast Fourier-transform (FFT) is described. It is based on an eight-point FFT wafer design, which uses two types of cells, a multiply-subtract-add (MSA) cell and a coefficient ROM cell. Systematic repetition of these cells and the interconnect forms the physical wafer. The cells are designed for high performance and testability. For success... View full abstract»

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  • Multiple voting systolic array

    Publication Year: 1991, Page(s):26 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A model of the multiple voting systolic array is proposed. The proposed fault tolerant technique uses majority decision by voting, without reconfiguration. As an example, a DFT (discrete Fourier transform) implementation of a triple voting systolic array is presented. It is shown that area redundancy is small and dynamic fault recovery is possible. It is believed that proposed fault-tolerant archi... View full abstract»

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  • Combining switch and site yields for soft-configurable WSI

    Publication Year: 1991, Page(s):97 - 103
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    The configuration requirements of a soft-configurable pipelined memory are described. Monte Carlo simulations show that wafer yield dependence on high switch yields can be reduced substantially using switch path bypasses and/or spare columns. These simulations combine the effects of switch and site failures in ways that cannot easily be captured using simpler analytic models, due to interdependenc... View full abstract»

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  • A new approach to implement a defect tolerant power distribution network in WSI circuits

    Publication Year: 1991, Page(s):215 - 222
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    An efficient approach for implementing a defect-tolerant power distribution network suitable for WSI (wafer scale integration) circuits is proposed. The network is not segmented but relies on a thermal imaging technique for defect localization and laser cutting for defect isolation. Power bus designs for this approach are described. Preliminary, experimental results have verified the design concep... View full abstract»

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  • Reconfiguring processor arrays using multiple-track models

    Publication Year: 1991, Page(s):307 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors study a 3-track-1-spare model that has three tracks along each channel and one spare row or column along each boundary. It is shown that the model uses the spare processors very efficiently; specifically, it is proved that a 3-track-1-spare model can support any set of nonintersecting compensation paths. This provides theoretical justification of the observations made in the literature... View full abstract»

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  • Clock distribution strategies for WSI: a critical survey

    Publication Year: 1991, Page(s):277 - 283
    Cited by:  Papers (9)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors review the available methods for clock distribution design which have been used at the VLSI level and discuss the adjustments necessary for WSI (wafer scale integration) design. It is pointed out that much work has been reported regarding methods for clock distribution design for VLSI, and it is noted that these techniques can be applied to WSI with appropriate adjustments made for lon... View full abstract»

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  • Physical design of the MUSE wafer-scale circuit

    Publication Year: 1991, Page(s):5 - 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    MUSE is a wafer-scale adaptive nulling processor which is being implemented using the restructurable VLSI techniques and design tools. The authors describe the physical design of the wafer with emphasis on interconnect redundancy and design for testability during the restructuring process. Power distribution and the wafer floorplan and packaging are also discussed View full abstract»

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  • A self-testing and self-diagnostic systolic array cell for signal processing

    Publication Year: 1991, Page(s):75 - 81
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A built-in self test (BIST) method for a systolic array controller chip/multiplier-accumulator chip (SAC/MAC) was used to generate the signatures for all combinational blocks of each cell in parallel. The BIST is combined with a scan path design; therefore, all registers in the array cells are connected as a scan chain and all signatures are shifted out by this scan chain to be compared with a pre... View full abstract»

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  • Concurrent error detection and fault location in reconfigurable WSI structures for FFT computation

    Publication Year: 1991, Page(s):47 - 53
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Presents a novel approach for concurrent error detection and location in homogeneous VLSI/WSI (wafer scale integration) architectures for the computation of the complex N-point fast Fourier transform. The proposed approach is based on the relationship between the computations of cells at a given point distance. This relationship is analyzed with respect to functional and physical faults. ... View full abstract»

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  • Wafer scale integration-a technology whose time has come

    Publication Year: 1991, Page(s):328 - 330
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The criteria which every new technological advance needs to satisfy before it can become accepted into the mainstream of product development are identified. it is then suggested that one company's wafer scale integration (WSI) now satisfies these criteria; it meets the needs of the intermediate storage market, and it is cost effective to manufacture because it provides a way for semiconductor manu... View full abstract»

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  • Defect-tolerant implementation of a systolic array for two-dimensional convolution

    Publication Year: 1991, Page(s):19 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    A defect-tolerant, advanced VLSI-implementation of the two-dimensional convolution algorithm for real-time processing is presented. The chip contrasts with previously published convolution chips by its maximum mask size of 256 tabs (dividable into up to four independent masks which were applied to the same video-signal) support of adaptive filtering, on-chip delay-lines, and implemented special pr... View full abstract»

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  • A WSI macrocell fault circumvention strategy

    Publication Year: 1991, Page(s):90 - 96
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    The use of a design paradigm that consists of a hierarchy of structures from cells to macrocells to functional elements to wafers greatly simplifies the design and development of wafer scale integration (WSI) systems. The authors examine the use of pooled spares, for fault circumvention at the macrocell level of the hierarchy. A method is provided that maximizes the yield of the pools of macrocell... View full abstract»

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  • The evolution of DRAM technology towards WSI

    Publication Year: 1991, Page(s):243 - 247
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    Issues connected with the evolution of dynamic random-access memory (DRAM) technology towards wafer scale integration (WSI) are examined. It is pointed out that as one moves towards submicron technologies, fundamental physical, electrical, and processing limits are being encountered, and it is becoming clear that this trend cannot continue. This phenomenon is most clearly demonstrated by the devel... View full abstract»

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  • Excimer laser formed vertical links of standard CMOS double-level metallizations

    Publication Year: 1991, Page(s):207 - 213
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Excimer-laser-formed vertical links between two metallization levels are demonstrated on special test chips, fabricated by ES2 in a standard CMOS process. Yield is 100% using link structures of 20 μm×20 μm and 14 μm×14 μm linear dimension and two identical laser pulses. Mean contact resistance is less than 200 Ω. A new test chip is built using sandwich layers for meta... View full abstract»

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  • A variable domain approach to reconfiguration of WSI processor arrays

    Publication Year: 1991, Page(s):134 - 140
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A novel reconfiguration algorithm for WSI (wafer scale integration) processor arrays using the concept of a variable domain is discussed. Variable domain is decided based on a fault distribution. The algorithm utilizes fault distribution information in the global assignment phase as well as in the local assignment phase. The concept of variable domain used in the algorithm overcomes the weakness o... View full abstract»

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  • Guidelines for testing WSI sequential arrays

    Publication Year: 1991, Page(s):300 - 306
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    New results on generating a functional test procedure for linear arrays composed of sequential cells are presented. The sequential cell is modeled as a finite state machine and the testing process is characterized by the definition of a test sequence for each transition of the finite state machine, by means of the unique input/output sequence technique. The two sets of conditions that are defined ... View full abstract»

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  • WSI systolic networks: an active silicon circuit board function for ULSI-based parallel computing

    Publication Year: 1991, Page(s):270 - 276
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The evolution of silicon to 0.25-μm technologies will yield very powerful, single-chip ULSI arrays of high-performance processors and high-capacity wafer-scale memories. The very compact, distributed computing systems which result will require very-high-performance communication networks, scaled to the much smaller size and more monolithic realization of future distributed systems. Multichip sy... View full abstract»

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  • Silicon substrate test structures for hybrid wafer scale technology

    Publication Year: 1991, Page(s):185 - 191
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    The authors explore the variety of test structures that may be used in the fabrication and assembly of silicon substrate multichip modules (MCMs) that aim at wafer scale complexity levels, with particular reference to their technological role. It is pointed out that a comprehensive set of test structures has been devised that provides yield, performance, and reliability information for silicon sub... View full abstract»

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  • A rapid prototype wafer scale system design for signal and data processing

    Publication Year: 1991, Page(s):68 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors describe a WSI (wafer scale integration) rapid prototype system design project. Applications which can be implemented as WSI systems are being developed at three universities (alpha sites). A single WSI design is being developed which can be rapidly restructured to meet the system requirements of each university. A system design verification approach that involves a common CAD (compute... View full abstract»

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  • A MIMD based multiprocessor architecture for real-time image processing suitable for a monolithic redundant realization

    Publication Year: 1991, Page(s):40 - 46
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    A novel MIMD (multiple instruction multiple data) based multiprocessor architecture consisting of multiple processing elements (PE) has been developed for real-time image processing. Each PE contains an arithmetic processing unit adapted to convolution-like low-level operations and a high-level and control processor. A high-speed random access to local image data is provided by two local input mem... View full abstract»

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