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Application Specific Array Processors, 1990. Proceedings of the International Conference on

Date 5-7 Sept. 1990

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Displaying Results 1 - 25 of 69
  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7)

    Publication Year: 1990
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  • A feedback concentrator for the Image Understanding Architecture

    Publication Year: 1990, Page(s):579 - 590
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    The Image Understanding Architecture (IUA) is a massively parallel, multilevel system. The hardware implementation of two important summary feedback mechanisms-some/none response and count responders-for the lower two processing levels of the first generation IUA are described. Both mechanisms are implemented using multiple copies of a single custom VLSI chip. A brief overview of the custom chip i... View full abstract»

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  • The design of a high-performance scalable architecture for image processing applications

    Publication Year: 1990, Page(s):722 - 733
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture ... View full abstract»

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  • Mapping high-dimension wavefront computations to silicon

    Publication Year: 1990, Page(s):78 - 89
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    The authors present a new template-matching algorithm with good recognition performance. However, this new algorithm exhibits a complex, four-dimensional, wavefront architecture. Thus, for VLSI implementation, reduced architectures with fewer connections and processors need to be derived. For this purpose, the authors develop a systematic reduction methodology to manually map wavefront computation... View full abstract»

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  • The bit-serial systolic back-projection engine (BSSBPE)

    Publication Year: 1990, Page(s):43 - 54
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The author presents a machine designed with a two-phase approach. First, the selection of an efficient algorithm, based on the quality of the final image and on the computational efficiency, is undertaken. Second, the algorithm is realized in hardware which incorporates efficient array processing structures, with the aim of creating regular repeated structures. The design is based on the S.Y. Kung... View full abstract»

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  • Calculus of space-optimal mappings of systolic algorithms on processor arrays

    Publication Year: 1990, Page(s):4 - 18
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    The authors present a method for the mapping of systolic algorithms that use the minimal number of processors. This method is based on geometrical interpretations on convex polyhedra in Z n. The authors present a recurrence equation model defining the target problems for systolic program derivation. Some geometrical tools on convex polyhedra in Zn are given.... View full abstract»

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  • Programming environment for a line processor-SYMPATI-2

    Publication Year: 1990, Page(s):567 - 578
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    The authors present the programming environment developed for the line processor SYMPATI-2. The main objective is to take advantage of the facilities provided by the parallel structure and make them easy to be used. The authors give the general characteristics of the SYMPATI-2 architecture and then present the programming environment and the 4 LP language. Some examples for illustrating the easy w... View full abstract»

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  • Array processing on finite polynomial rings

    Publication Year: 1990, Page(s):284 - 295
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The disadvantage of computations using finite rings is the need to compute over many different rings in order to produce useful dynamic ranges of computation. By mapping integers into polynomial rings, one can replace the different rings by the replication of the same ring with considerable computational advantages. The authors present the methodology of such a mapping strategy, and discuss the ap... View full abstract»

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  • Massively parallel architecture: application to neural net emulation and image reconstruction

    Publication Year: 1990, Page(s):214 - 225
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    The authors present two applications of a specific cellular architecture: emulation of the recall and learning for feedforward neural networks and parallel image reconstruction. This architecture is based on a bidimensional array of asynchronous processing elements, the cells, which can communicate between themselves by message transfers. Each cell includes a rotating routing part ensuring the mes... View full abstract»

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  • Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing

    Publication Year: 1990, Page(s):712 - 721
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The authors present a fast parallel simulated annealing algorithm for solving the traveling salesman problem (TSP) on single-instruction multiple-data (SIMD) machines with linear interconnections among processing elements. In the algorithm for TSP, it is shown that with the proper data distribution and movement schemes, the generation of a new configuration and the calculation of energy difference... View full abstract»

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  • Digit-serial VLSI microarchitecture

    Publication Year: 1990, Page(s):457 - 468
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    The authors illustrate the techniques by which a simple function library may be widely parameterized to meet the diverse function, throughput and accuracy requirements in high-performance integer arithmetic applications. In a design automation environment the user's view of these structures is, in the case of multipliers and adders, a simple functional icon carrying synthetic parameters which are ... View full abstract»

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  • Systolic architectures for decoding Reed-Solomon codes

    Publication Year: 1990, Page(s):67 - 77
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A systolic implementation of a Reed-Solomon decoder is presented which with minor modification is suitable for BCH and Goppa codes. The various operations involved in decoding such codes were analyzed and the results are described. Systolic array architectures are derived for the various steps including the syndrome calculation, key equation solution and error evaluation. Since the throughput of t... View full abstract»

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  • Systolic array implementation of nested loop programs

    Publication Year: 1990, Page(s):31 - 42
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors consider a formal and systematic method to convert a class of nested loop programs to single assignment codes and, when possible, to regular algorithms (RAs) for systolic array implementation. The authors concentrate on the analysis of certain imperative nested loop programs in view of the ultimate objective, which is the (semi)-automatic design of systolic arrays from such initial beh... View full abstract»

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  • Linear arrays for residue mappers

    Publication Year: 1990, Page(s):309 - 316
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    Pipelined structures based on the residue number system (RNS) have been found suitable for high-speed arithmetic. The polynomial RNS (PRNS) can speed up digital signal processing (DSP)-related tasks like correlations and convolutions. The authors introduce pipelined arrays able to serve as mapping modules for PRNS-based functional units. Such mappings, involve polynomial evaluation coupled with mo... View full abstract»

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  • Mapping algorithms onto the TUT cellular array processor

    Publication Year: 1990, Page(s):235 - 246
    Cited by:  Papers (3)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    The Tampere University of Technology Cellular Array (TUTCA) processor array is based on a dynamically configurable logic cell array. It is intended for efficient implementation of the direct mapping dataflow principle with a self-timed, distributed control structure. The architecture of the processor, principles of mapping algorithms on it, and the compiler of the dataflow language are described. ... View full abstract»

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  • Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

    Publication Year: 1990, Page(s):329 - 340
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned log... View full abstract»

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  • Design of run-time fault-tolerant arrays of self-checking processing elements

    Publication Year: 1990, Page(s):168 - 179
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A design method for array architectures from regular dependence graphs (DGs) is extended for the design of reconfigurable arrays. The original design method is combined to a single step mapping of the DG with arbitrary dimension n onto the final signal flow graph (SFG) with dimension k. This eliminates the need for recursive application of a mapping which reduces the dimension of... View full abstract»

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  • Systolic VLSI compiler (SVC) for high performance vector quantisation chips

    Publication Year: 1990, Page(s):145 - 155
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    An overview is given of a systolic VLSI compiler (SVC) tool currently under development for the automated design of high performance digital signal processing (DSP) chips. Attention is focused on the design of systolic vector quantization chips for use in both speech and image coding systems. The software in question consists of a cell library, silicon assemblers, simulators, test pattern generato... View full abstract»

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  • Embedding pyramids in array processors with pipelined busses

    Publication Year: 1990, Page(s):665 - 676
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    The concept of pipelined buses for parallel architectures diverges from the conventional exclusive access buses and offers both possibilities and challenges for significantly improving the efficiency of interprocessor communications in parallel computers. The authors present an efficient embedding of pyramids in array processors with pipelined buses. The embedding has the property that all the nei... View full abstract»

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  • Towards the automated design of application specific array processors (ASAPs)

    Publication Year: 1990, Page(s):414 - 425
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    The authors describe the architecture and VLSI design of GLiTCH, an associative processor array chip designed for computer vision applications. The design is built from a library of cells, which can be used in conjunction with high level functional specifications to rapidly design new application specific array processors. The objective is to design a system which will allow application specific a... View full abstract»

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  • Fine-grain system architectures for systolic emulation of neural algorithms

    Publication Year: 1990, Page(s):554 - 566
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A systolic approach is described that is well suited to solve the neural net interconnection problem and cope with neural application areas like vision or speech. The proposed neuro-emulator concept is sizeable to the application domain in terms of processing power, memory and flexibility, and it is designed for throughput rates that enable the user to access real-world applications in reasonable ... View full abstract»

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  • Implementation of systolic algorithms using pipelined functional units

    Publication Year: 1990, Page(s):272 - 283
    Cited by:  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of initiating a new operation before the previous one has been completed. The method permits transformation of a SA so that it can be efficiently executed using PFUs. The method is based ... View full abstract»

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  • Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor

    Publication Year: 1990, Page(s):202 - 213
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    The authors present the concept of vector register windows (VRWs) geared towards large scale matrix computation and image processing applications. The VRWs consist of multiple windows for vector registers providing parallel access and manipulation of large matrix data in the orthogonal multiprocessor (OMP). The number of windows and the number of registers in a window are dynamically reconfigurabl... View full abstract»

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  • A systolic array for nonlinear adaptive filtering and pattern recognition

    Publication Year: 1990, Page(s):700 - 711
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A systolic array for multidimensional fitting and interpolation using (nonlinear) radial basis functions (RBFs) is proposed. The fit may be constrained very simply to ensure that the resulting surface takes a pre-determined value at one or more specific points. The RBF processor is capable of performing a wide range of complex pattern recognition tasks. The processor, which constitutes a form of n... View full abstract»

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  • An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation

    Publication Year: 1990, Page(s):448 - 456
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The extended Euclidean algorithm (XEA) is the basis of one of the methods used for solving the key equation which arises in decoding Reed-Solomon error correcting codes. The algorithm is implemented using an Advanced Micro Devices electrically programmable gate array (EPGA) development system. This PC based software uses ORCAD schematic entry and simulation in conjunction with an AMD interface. EP... View full abstract»

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