[1990] Proceedings of the International Conference on Application Specific Array Processors

5-7 Sept. 1990

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  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.90CH2920-7)

    Publication Year: 1990
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    Freely Available from IEEE
  • ASP modules: building-blocks for application-specific massively parallel processors

    Publication Year: 1990, Page(s):493 - 504
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (476 KB)

    ASP (associative string processor) modules comprise highly-versatile parallel processing building-blocks for the simple construction of application-specific second-generation massively parallel processors (MPPs). The author discusses ASP module philosophy, demonstrates how ASP modules can satisfy the market, algorithmic, architectural, and engineering requirements of application-specific MPPs, and... View full abstract»

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  • A systolic array programming language

    Publication Year: 1990, Page(s):794 - 803
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (276 KB)

    The author gives an overview of the Warp systolic array and describes the AL language and its implementation for the Warp machine. AL is a sequential programming language extended with the DARRAY data structure and DO looping construct to guide the compiler to generate efficient parallel code. The author has implemented an AL compiler for the Warp machine and has been using AL to program matrix co... View full abstract»

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  • Extensions to linear mapping for regular arrays with complex processing elements

    Publication Year: 1990, Page(s):156 - 167
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (488 KB)

    The optimal architectural design of the processing elements (PEs) for an application specific regular array (RA) is nontrivial if the application has a complex operation set. The authors present an approach that extends the conventional, linear time-space transformation for such cases. In application-specific-integrated-circuit (ASIC) architectures, one has the freedom to fine-tune all aspects of ... View full abstract»

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  • Dynamic systolic associative memory chip

    Publication Year: 1990, Page(s):481 - 492
    Cited by:  Papers (2)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (772 KB)

    A dynamic random access memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (256×4096) associative memory chip based on a 1-Mb DRAM, the ~10 transistors per sense amplifier in a DRAM are expanded to ~24 transistors per sense amplifier in the modified chip... View full abstract»

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  • Channel complexity analysis for reconfigurable VLSI/WSI processor arrays

    Publication Year: 1990, Page(s):329 - 340
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (608 KB)

    The authors propose a general method to analyze channel complexity for a 2D array with a given domain constraint. A domain-based reconfiguration scheme can be divided into two phases: assignment and interconnection. In the assignment phase a logical cell is assigned to a fault-free cell under a domain constraint by assignment rules. In the interconnection phase connections between the assigned log... View full abstract»

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  • A practical runtime test method for parallel lattice-gas automata

    Publication Year: 1990, Page(s):782 - 793
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (504 KB)

    The authors describe a test method for lattice-gas automata of the type introduced by U. Frisch et al. (1986). The test method consists of inserting test patterns into the initial state of the automaton and using a graphics display to detect errors. The test patterns are carefully constructed limit cycles that are disrupted by errors occurring at any level of the simulator system. The patterns can... View full abstract»

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  • Systolic VLSI compiler (SVC) for high performance vector quantisation chips

    Publication Year: 1990, Page(s):145 - 155
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    An overview is given of a systolic VLSI compiler (SVC) tool currently under development for the automated design of high performance digital signal processing (DSP) chips. Attention is focused on the design of systolic vector quantization chips for use in both speech and image coding systems. The software in question consists of a cell library, silicon assemblers, simulators, test pattern generato... View full abstract»

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  • An analog VLSI array processor for classical and connectionist AI

    Publication Year: 1990, Page(s):367 - 378
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (492 KB)

    The authors describe the architecture of an operational 31-cell CMOS VLSI Lukasiewicz logic array (LLA) which is regular, simple, area-efficient, and implemented with analog rather than digital processing elements. The prototype LLAs are programmed with input vectors derived from normal forms of sentences in the Lukasiewicz logic. This requires data inputs on the order of O(2n)... View full abstract»

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  • The design of a high-performance scalable architecture for image processing applications

    Publication Year: 1990, Page(s):722 - 733
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (408 KB)

    The authors present the organization of an interleaved wrap-around memory system for a partitionable parallel/pipeline architecture with P pipes of L processors each. The architecture is designed to efficiently support real-time image processing and computer vision algorithms, especially those requiring global data operations. The interleaved memory system makes the architecture ... View full abstract»

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  • CMOS VLSI Lukasiewicz logic arrays

    Publication Year: 1990, Page(s):469 - 480
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (432 KB)

    Lukasiewicz logic arrays (LLAs) are massively parallel analog computers organized as binary trees of identical processing elements. The authors have designed and performed preliminary tests on a series of CMOS VLSI LLAs whose cells perform Lukasiewicz implication (→). The authors describe the LLA architecture and its relationship to cellular automata, describe the CMOS VLSI implementation of ... View full abstract»

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  • A fault-tolerant two-dimensional sorting network

    Publication Year: 1990, Page(s):317 - 328
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (480 KB)

    The authors evaluate a class of sorting algorithms which can be adapted to a faulty network with nearest neighbor interconnections by determining a suitable indexing scheme. A worst case sorting time of O(N) is proved for these sorters. Simulation results show that the average sorting time of the fault-tolerant sorters is only slightly higher than O(√N), a... View full abstract»

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  • A design methodology for fixed-size systolic arrays

    Publication Year: 1990, Page(s):591 - 602
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (588 KB)

    The authors present a methodology to design fixed-size systolic arrays. It allows a systematic and hierarchical mapping of full-size arrays to fixed-size arrays. Two processor-clustering techniques are described. They can be used to achieve the following design objectives: (1) transforming inefficient arrays into efficient arrays, (2) reducing the size of an array, (3) reducing the dimension of an... View full abstract»

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  • Bit-level systolic algorithm for the symmetric eigenvalue problem

    Publication Year: 1990, Page(s):770 - 781
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (624 KB)

    An arithmetic algorithm is presented which speeds up the parallel Jacobi method for the eigen-decomposition of real symmetric matrices. After analyzing the elementary mathematical operations in the Jacobi method (i.e. the evaluation and application of Jacobi rotations), the author devises arithmetic algorithms that effect these mathematical operations with few primitive operations (i.e. few shifts... View full abstract»

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  • A graph-based approach to map matrix algorithms onto local-access processor arrays

    Publication Year: 1990, Page(s):641 - 652
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (464 KB)

    The authors describe the application of the multi-mesh graph (MMG) method to the mapping of large matrix algorithms onto class-specific local-access processor arrays. These arrays consist of cells with large local memory (i.e., memory size proportional to the size of the problems) and low cell bandwidth (much smaller than the cell computation rate). The results given indicate that the MMG method a... View full abstract»

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  • Systolic-based computing machinery for radar signal processing studies

    Publication Year: 1990, Page(s):689 - 699
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (448 KB)

    The authors describe a high-speed systolic-based computer system designed to process real-life radar data in near real time. At the heart of the system is a ten-cell Warp (systolic) machine. A digital recorder is used to input data to the system, and a color monitor displays the output of the processing algorithms. The system permits the processing of large volumes of radar data in real time, disp... View full abstract»

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  • Analysing parametrised designs by non-standard interpretation

    Publication Year: 1990, Page(s):133 - 144
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (444 KB)

    The authors consider the use of a nonstandard interpretation to analyze parametrized circuit descriptions, in particular for array based architectures. Various metrics are employed to characterize the performance tradeoffs for generic designs. The objective is to facilitate the comparison of feasible design alternatives at an early stage of development. The research centers on techniques for extra... View full abstract»

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  • A prototype for a fault tolerant parallel signal processor

    Publication Year: 1990, Page(s):518 - 529
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (340 KB)

    The authors describe a hardware prototype of a fault-tolerant parallel digital signal processor (DSP) that uses the single fault correction scheme of B.E. Musicus and W. S. Song (1987, 1990). Ten of the sixteen DSP-32 C processors perform identical linear operations on ten different data streams (a complex fast Fourier transform (FFT) for a sonar beamforming application), three do arithmetic check... View full abstract»

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  • PASIC. A sensor/processor array for computer vision

    Publication Year: 1990, Page(s):352 - 366
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (472 KB)

    The PASIC prototype chip contains 256×256 photosensors, a linear array of 256 A/D converters, two 256 8-bit shift registers, 256 bit-serial processors, and a 256×256 bit dynamic RAM. It appears to be a viable architecture for low-level vision processing. The processors operate in SIMD model at 20 MHz. To avoid high speed transfer of analog data, an A/D converter in the form of a linear... View full abstract»

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  • A processor-time minimal systolic array for transitive closure

    Publication Year: 1990, Page(s):19 - 30
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (436 KB)

    A directed acyclic graph (DAG) model of algorithms is used. For a given DAG the authors focus on processor-time minimal multiprocessor schedules: time minimal multiprocessor schedules that use as few processors as possible. The Kung, Lo and Lewis (KLL) algorithm (S.-Y. Kung et al., 1987) for computing the transitive closure of a relation over a set of n elements requires at least 5n View full abstract»

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  • An improved multilayer neural model and array processor implementation

    Publication Year: 1990, Page(s):389 - 400
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (448 KB)

    The authors present a method for obtaining faster learning in a multilayer neural network. The key ingredient is the concept of floating positive/negative thresholds used in the output neurons to interpret the output states. In a traditional multilayer perceptron, the output state is 1 or 0, depending on whether the activation value exceeds the fixed target threshold or not. The proposed approach ... View full abstract»

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  • Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing

    Publication Year: 1990, Page(s):712 - 721
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (360 KB)

    The authors present a fast parallel simulated annealing algorithm for solving the traveling salesman problem (TSP) on single-instruction multiple-data (SIMD) machines with linear interconnections among processing elements. In the algorithm for TSP, it is shown that with the proper data distribution and movement schemes, the generation of a new configuration and the calculation of energy difference... View full abstract»

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  • Towards the automated design of application specific array processors (ASAPs)

    Publication Year: 1990, Page(s):414 - 425
    Cited by:  Papers (2)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (412 KB)

    The authors describe the architecture and VLSI design of GLiTCH, an associative processor array chip designed for computer vision applications. The design is built from a library of cells, which can be used in conjunction with high level functional specifications to rapidly design new application specific array processors. The objective is to design a system which will allow application specific a... View full abstract»

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  • Domain flow and streaming architectures

    Publication Year: 1990, Page(s):438 - 447
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (476 KB)

    The author introduces the main ideas of a system compiler for affine dependence algorithm. The first idea is a streaming architecture, which is a machine model for the compiler that reduces control overhead in comparison with an ensemble of von Neumann architectures. Such a streaming architecture is a dedicated architecture programmed with an incremental array instruction to be able to run any ins... View full abstract»

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  • Digit-serial VLSI microarchitecture

    Publication Year: 1990, Page(s):457 - 468
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    The authors illustrate the techniques by which a simple function library may be widely parameterized to meet the diverse function, throughput and accuracy requirements in high-performance integer arithmetic applications. In a design automation environment the user's view of these structures is, in the case of multipliers and adders, a simple functional icon carrying synthetic parameters which are ... View full abstract»

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