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Real-Time and Embedded Technology and Applications Symposium, 2009. RTAS 2009. 15th IEEE

Date 13-16 April 2009

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  • [Front cover]

    Publication Year: 2009 , Page(s): C1
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  • [Title page i]

    Publication Year: 2009 , Page(s): i
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  • [Title page iii]

    Publication Year: 2009 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2009 , Page(s): iv
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  • Table of contents

    Publication Year: 2009 , Page(s): v - viii
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  • Message from Program Chair

    Publication Year: 2009 , Page(s): ix
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  • Organizing Committee

    Publication Year: 2009 , Page(s): x
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  • Technical Program Committee

    Publication Year: 2009 , Page(s): xi
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  • list-reviewer

    Publication Year: 2009 , Page(s): xii
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  • Notional Processors: An Approach for Multiprocessor Scheduling

    Publication Year: 2009 , Page(s): 3 - 12
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    Consider the problem of designing an algorithm with a high utilization bound for scheduling sporadic tasks with implicit deadlines on identical processors. A task is characterized by its minimum interarrival time and its execution time. Task preemption and migration is permitted. Still, low preemption and migration counts are desirable.We formulate an algorithm with a utilization bound no less than 66.6%characterized by worst-case preemption counts comparing favorably against the state-of-the-art. View full abstract»

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  • An Evaluation of the Dynamic and Static Multiprocessor Priority Ceiling Protocol and the Multiprocessor Stack Resource Policy in an SMP System

    Publication Year: 2009 , Page(s): 13 - 22
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (355 KB) |  | HTML iconHTML  

    There has been significant study of implementations of a variety of priority inversion control algorithms in uniprocessor systems, but there has been far less work done on the multiprocessor implementations of these algorithms. Herein, we will present such an evaluation of the Multiprocessor Priority Ceiling Protocol (MPCP) and the Multiprocessor Stack Resource Policy (MSRP). To our knowledge, no such empirical evaluation of these two policies has been conducted prior to this. We will show that the results differ from the previous simulation-based studies and that both policies are more or less equally effective. The main difference is the MSRPpsilas expense. We discuss the efficacy of Ada-2005 and C/POSIX. We also discuss the methods through which we have attempted to overcome Adapsilas weakness in mapping tasks to processors. View full abstract»

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  • Semi-partitioned Fixed-Priority Scheduling on Multiprocessors

    Publication Year: 2009 , Page(s): 23 - 32
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (487 KB) |  | HTML iconHTML  

    This paper presents a new algorithm for fixed-priority scheduling of sporadic task systems on multiprocessors.The algorithm is categorized to such a scheduling class that qualifies a few tasks to migrate across processors, while most tasks are fixed to particular processors. We design the algorithm so that a task is qualified to migrate, only if it cannot be assigned to any individual processors, in such a way that it is never returned to the same processor within the same period, once it is migrated from one processor to another processor. The scheduling policy is then conformed to deadline monotonic. According to the simulation results, the new algorithm significantly outperforms the traditional fixed-priority algorithms in terms of schedulability. View full abstract»

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  • Minimizing WCET for Real-Time Embedded Systems via Static Instruction Cache Locking

    Publication Year: 2009 , Page(s): 35 - 44
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB) |  | HTML iconHTML  

    Cache is effective in bridging the gap between processor and memory speed. It is also a source of unpredictability because of its dynamic and adaptive behavior. Worst-case execution time (WCET) of an application is one of the most important criteria for real-time embedded system design. The unpredictability of instruction miss/hit behavior in the instruction cache (I-Cache) leads to an unnecessary over-estimation of the real-time application's WCET. A lot of modern processors provide cache locking capability. Static I-Cache locking locks function/instruction blocks of a program into the I-Cache before program execution. In this way, a more precise estimation of WCET can be achieved. The selection of functions/instructions to be locked in the I-Cache has dramatic influence on the performance of the real-time application. This paper focuses on the static I-Cache locking problem to minimize WCET for real-time embedded systems. We formulate the problem using an Execution Flow Tree (EFT) and a linear programming model. For a subset of the problems with certain properties, corresponding polynomial time optimal algorithms are proposed. We prove that the general problem is an NP-Hard problem. We also show that for a subset of the general problem with certain patterns, optimal solutions can be achieved in polynomial time. Experimental results show that our algorithms can reduce the WCET of applications further compared to current best known techniques. View full abstract»

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  • Static Prediction of Worst-Case Data Cache Performance in the Absence of Base Address Information

    Publication Year: 2009 , Page(s): 45 - 54
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (483 KB) |  | HTML iconHTML  

    While caches are essential to reduce execution time and power consumption, they complicate the estimation of the worst-case execution time (WCET), crucial for many real-time systems (RTS). Most research on static worst-case cache behavior prediction has focused on hard RTS, which need complete information on the access patterns and addresses of the data to guarantee the predicted WCET is a safe upper bound of any execution time. Access patterns are available in those codes that have a steady state of access patterns after the first iteration of a loop (in the following regular codes), however, the addresses of the data are not always known at compile time for many reasons: stack variables, dynamically allocated memory, modules compiled separately, etc. Even when available, their usefulness to predict cache behavior in systems with virtual memory decreases in the presence of physically-indexed caches. In this paper we present a model that predicts a reasonable bound of the worst-case behavior of data caches during the execution of regular codes without information on the base address of the data structures. In 99.7% of our tests the number of misses performed below the boundary predicted by the model. This turns the model into a valuable tool, particularly for non-RTS and soft RTS, which tolerate a percentage of the runs exceeding their deadlines. View full abstract»

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  • Model Identification for WCET Analysis

    Publication Year: 2009 , Page(s): 55 - 64
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (254 KB) |  | HTML iconHTML  

    Worst-Case Execution Time (WCET) analysis derives upper bounds for the execution times of programs. Such bounds are crucial when designing and verifying real-time systems. Static WCET analysis derives safe upper bounds. For complex hardware architectures the hardware modelling is still a challenge, leading to long analysis times and a risk of large WCET overestimation. Therefore, hybrid WCET analysis methods have appeared, where measurements are used to augment or replace the detailed low-level static WCET analysis. These methods do not in general yield a safe WCET estimate, but can still be appropriate in soft real-time systems where such WCET estimates are not crucial. In this paper we make two contributions. First, we develop a hybrid WCET analysis method, which uses regression to identify parameters in the common linear Implicit Path Enumeration Technique (IPET) model for WCET calculation. The method can use timing measurements of different granularity, including end-to-end measurements, which reduces the need for fine-grained timing measurement instrumentation. It uses a novel kind of regression, which guarantees that the identified model does not underestimate any observed execution times. Second, we initiate the development of an IPET-based theory for hybrid WCET analysis test coverage, and we formulate and prove a coverage criterion for the tests needed to identify a safe model. View full abstract»

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  • CSL: A Language to Specify and Re-specify Mobile Sensor Network Behaviors

    Publication Year: 2009 , Page(s): 67 - 76
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1125 KB) |  | HTML iconHTML  

    The Collaborative Sensing Language (CSL) is a high-level feedback control language for mobile sensor networks (MSN). It specifies MSN controllers to accomplish network objectives with a dynamically changing ad-hoc resource pool. Furthermore, CSL is designed to allow the updating of controllers during execution (patching). This enables hierarchical control with simpler controllers at lower levels. The CSL Execution Engine contains the intelligence to allocate resources to tasks dynamically and adjust in real time to resource motion, this enables CSL controllers to be simple, intuitive and scalable. Experimental results show that the CSL Execution Engine performs these services with the addition of very little overhead. View full abstract»

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  • Execution Strategies for PTIDES, a Programming Model for Distributed Embedded Systems

    Publication Year: 2009 , Page(s): 77 - 86
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (953 KB) |  | HTML iconHTML  

    We define a family of execution policies for a programming model called PTIDES (programming temporally integrated distributed embedded systems). A PTIDES application (factory automation, for example) is given as a discrete-event (DE) model of a distributed real-time system that includes sensors and actuators. The time stamps of DE events are bound to physical time at the sensors and actuators, turning the DE model into an executable specification of the system with explicit real-time constraints. This paper first defines a general execution strategy that conforms to the DE semantics, and then specializes this strategy to give practical, implementable and distributed policies. Our policies leverage network time synchronization to eliminate the need for null messages, allow independent events to be processed out of time stamp order, thus increasing concurrency and making more models feasible (w.r.t. real-time constraints), and improve fault isolation in distributed systems. The policies are given in terms of a safe to process predicate on events that depends on the time stamp of the events and the local notion of physical time. In a simple case we show how to statically check whether program execution satisfies timing constraints. View full abstract»

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  • On Dynamic Reconfiguration of a Large-Scale Battery System

    Publication Year: 2009 , Page(s): 87 - 96
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB) |  | HTML iconHTML  

    Electric vehicles powered with large-scale battery packs are gaining popularity as gasoline price soars. Large-scale battery packs usually consist of an estimated 12,000 battery cells connected in series and parallel, which are susceptible to battery-cell failures. Unfortunately, current battery-management systems are unable to handle the inevitable battery-cell failures very well. To address this problem, we propose a dynamic reconfiguration framework that monitors, reconfigures, and controls large-scale battery packs online. The framework is built upon a syntactic bypassing mechanism that provides a set of rules for changing the battery-pack configuration, and a semantic bypassing mechanism by which the battery-cell connectivity is reconfigured to recover from a battery-cell failure. In particular, the semantic bypassing mechanism is dictated by constant-voltage-keeping and dynamic-voltage-allowing policies. The former policy is effective in preventing unavoidable voltage drops during the battery discharge, while the latter policy is effective in supplying different amounts of power to meet a wide-range of application requirements. Our experimental evaluation has shown the proposed framework to enable the battery packs to be 9 times as fault-tolerant as a legacy scheme. View full abstract»

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  • The System-Level Simplex Architecture for Improved Real-Time Embedded System Safety

    Publication Year: 2009 , Page(s): 99 - 107
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing application-level fault-tolerance methods, even if formally verified, leave the system vulnerable to errors in the real-time operating system (RTOS), middleware, and microprocessor. We introduce the system-level simplex architecture, which uses hardware/software co-design to provide fail-operational guarantees for both logical application-level faults, as well as faults in previously dependent layers including the RTOS and microprocessor. We also provide an end-to-end design process for the system-level simplex architecture where the AADL architecture description is automatically constructed and checked and the VHDL hardware code is generated. To show the efficacy of System-Level Simplex design, we apply the approach to both a classic inverted pendulum and a cardiac pacemaker. We perform fault-injection tests on the inverted pendulum design which demonstrate robustness in spite of software controller and operating system faults. For the pacemaker, we contrast the provided safety guarantees with those of a previous-generation pacemaker. View full abstract»

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  • QeDB: A Quality-Aware Embedded Real-Time Database

    Publication Year: 2009 , Page(s): 108 - 117
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    QeDB is a database for data-intensive real-time applications running on flash memory-based embedded systems.Currently, databases for embedded systems are best effort,providing no guarantees on its timeliness and data freshness. Moreover, the existing real-time database (RTDB) technology can not be applied to these embedded databases since they hypothesize that the main memory of a system is large enough to hold all database, which can not be true in data-intensive real-time applications. QeDB uses a novel feedback control scheme to support QoS in such embedded systems without requiring all data to reside in main memory.In particular, our approach is based on simultaneous control of both I/O and CPU resource to guarantee the desired timeliness. Unlike existing work on feedback control of RTDB performance, we actually implement and evaluate the proposed scheme in a modern embedded system.The experimental results show that our approach supports the desired timeliness of transactions while still maintaining high data freshness compared to baseline approaches. View full abstract»

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  • Adaptive Failover for Real-Time Middleware with Passive Replication

    Publication Year: 2009 , Page(s): 118 - 127
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (342 KB) |  | HTML iconHTML  

    Supporting uninterrupted services for distributed soft real-time applications is hard in resource-constrained and dynamic environments, where processor or process failures and system workload changes are common. Fault-tolerant middleware for these applications must achieve high service availability and satisfactory response times for client applications. Although passive replication is a promising fault tolerance strategy for resource-constrained systems, conventional client failover approaches are non-adaptive and load-agnostic, which can cause system overloads and significantly increase response times after failure recovery.This paper presents four contributions to the study of passive replication for distributed soft real-time applications. First, it describes how our fault-tolerant load-aware and adaptive middleware (FLARe) dynamically adjusts failover targets at runtime in response to system load fluctuations and resource availability. Second, it describes how FLARe's overload management strategy proactively enforces desired CPU utilization bounds by redirecting clients from overloaded processors. Third, it presents the design and implementation of FLARe's lightweight middleware architecture that manages failures and overloads transparently to clients. Finally, it presents experimental results on a distributed Linux testbed that demonstrate how FLARe adaptively maintains soft real-time performance for clients operating in the presence of failures and overloads with negligible runtime overhead. View full abstract»

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  • Thermal-Aware Global Real-Time Scheduling on Multicore Systems

    Publication Year: 2009 , Page(s): 131 - 140
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (318 KB) |  | HTML iconHTML  

    As the power density of modern electronic circuits increases dramatically, systems are prone to overheating. Thermal management has become a prominent issue in system design. This paper explores thermal-aware scheduling for sporadic real-time tasks to minimize the peak temperature in a homogeneous multicore system, in which heat might transfer among some cores. By deriving an ideally preferred speed for each core, we propose global scheduling algorithms which can exploit the flexibility of multicore platforms at low temperature. Compared with load-balancing strategies, the proposed algorithms can significantly reduce the peak temperature by up to 30degC to 70degC for simulated platforms. View full abstract»

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  • Proactive Speed Scheduling for Real-Time Tasks under Thermal Constraints

    Publication Year: 2009 , Page(s): 141 - 150
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    Thermal management becomes a prominent issue in system design for both server systems and embedded systems. A system could fail if the peak temperature exceeds its thermal constraint. This research studies thermal-constrained scheduling for frame-based real-time tasks on a dynamic voltage/speed scaling system. Our objective is to design speed schedulers for real-time tasks by utilizing dynamic voltage/speed scaling to meet both timing and thermal constraints. Two approaches are proposed: One is based on the minimization of the response time under the thermal constraint, and the other is based on the minimization of the temperature under the timing constraint. We present detailed schedulability analysis for both proposed approaches. Our data show that our proposed proactive approaches outperform existing reactive ones. View full abstract»

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  • Power-Aware Mapping of Probabilistic Applications onto Heterogeneous MPSoC Platforms

    Publication Year: 2009 , Page(s): 151 - 160
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    Multiprocessor SoC platforms have been adopted for a wide range of high performance applications. Task assignment and processing unit allocation are key steps in the design of predictable and efficient embedded systems. Provided that the probability distributions and mutual exclusion conditions for executing applications are known a priori, this paper explores the mapping of tasks onto processing units while minimizing the expected average power consumption. The underlying model considers static (leakage) and dynamic power. This study shows that deriving approximative solutions with a constant worst-case approximation factor in polynomial time is not achievable unless P=NP, even if a feasible task mapping is provided as an input. A polynomial-time heuristic algorithm is proposed that applies a multiple-step heuristic. Experimental results reveal the effectiveness of the proposed algorithm by comparing the derived solutions to the optimal ones, obtained via an integer linear program (ILP) specification. View full abstract»

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  • A Metric for Judicious Relaxation of Timing Constraints in Soft Real-Time Systems

    Publication Year: 2009 , Page(s): 163 - 172
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (602 KB) |  | HTML iconHTML  

    For soft real-time systems, timing constraints are not as stringent as those in hard real-time systems: some constraint violations are permitted as long as the amount of violation is within a given limit. The allowed flexibility for soft real-time systems can be utilized to improve system's other quality-of-service (QoS) properties, such as energy consumption. One way to enforce constraint violation limit is to allow an expansion of timing constraint feasible region, but restrict the expansion in such a way that the relaxed constraint feasible region sufficiently resembles the original one. In this paper, we first introduce a new metric, constraint set similarity, to quantify the resemblance between two different timing constraint sets. Because directly calculating the exact value of the metric involves calculating the size of a polytope which is a #P-hard problem, we instead introduce an efficient method for estimating its bound. We further discuss how this metric can be exploited for evaluating trade-offs between timing constraint compromises and system's other QoS property gains. We use energy consumption reduction as an example to show the application of the proposed metric. View full abstract»

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