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Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

14-16 July 1997

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  • Proceedings IEEE International Conference on Application-Specific Systems, Architectures and Processors

    Publication Year: 1997
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    Freely Available from IEEE
  • An approach for quantitative analysis of application-specific dataflow architectures

    Publication Year: 1997, Page(s):338 - 349
    Cited by:  Papers (87)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a quantitative way and therefore supports him in the design process to find better performing architectures. The context of our work is video signal processing algorithms which are mapped onto weakly-programmable, coarse-grai... View full abstract»

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  • Index of authors

    Publication Year: 1997, Page(s):539 - 540
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    Freely Available from IEEE
  • Low power CORDIC implementation using redundant number representation

    Publication Year: 1997, Page(s):154 - 161
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    In this paper a methodology for reducing the power consumption of shift-and-add operations in general and especially of CORDIC stages is presented. The proposed method uses the fact of simultaneous carry generation in redundant carry-save and signed digit structures to predict the minimum necessary hardware effort for shift-and-add operations. As a carry once generated in a certain bit position ca... View full abstract»

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  • Accurate function approximations by symmetric table lookup and addition

    Publication Year: 1997, Page(s):144 - 153
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper presents a high-speed method for accurate function approximations. This method employs parallel table lookups followed by multi-operand addition. It takes advantage of leading zeros and symmetry in the table entries to reduce the table sizes. By increasing the number of tables and the number of operands in the multi-operand addition, the amount of memory is significantly reduced. This m... View full abstract»

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  • Determination of the processor functionality in the design of processor arrays

    Publication Year: 1997, Page(s):199 - 208
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper the inclusion of hardware constraints into the design of massively parallel processor arrays is considered. We propose an algorithm which determines an optimal scheduling function as well as the selection of components which have to be implemented in one processor of a processor array. The arising optimization problem is formulated as an integer linear program which also takes the ne... View full abstract»

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  • CORDIC-based computation of ArcCos and ArcSin

    Publication Year: 1997, Page(s):132 - 143
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    CORDIC-based algorithms to compute cos-1(t), sin-1 (t) and √(1-t2) are proposed. The implementation requires a standard CORDIC module plus a module to compute the direction of rotation, this being the same hardware required for the extended CORDIC vectoring, recently proposed by the authors. Although these functions can be obtained as a special case of this e... View full abstract»

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  • A flexible data-interlacing architecture for full-search block-matching algorithm

    Publication Year: 1997, Page(s):96 - 104
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate.... View full abstract»

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  • ADPCM codec: from system level description to versatile HDL model

    Publication Year: 1997, Page(s):458 - 467
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (672 KB)

    Due to the rapid increase in the system complexity of modern telecommunication products, two main challenges exist for a system design flow meeting the arising demands: 1) provide a platform for fast algorithmic and architectural design exploration and optimization from system to gate level, which guarantees high quality of results (QoR) and enables full and seamless design verification; 2) provid... View full abstract»

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  • A logical framework to prove properties of ALPHA programs

    Publication Year: 1997, Page(s):187 - 198
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    We present an assertional approach to prove properties of ALPHA programs. ALPHA is a functional language based on affine recurrence equations. We first present two kinds of operational semantics for ALPHA together with some equivalence and confluence properties of these semantics. We then present an attempt to provide ALPHA with an external logical framework. We therefore define a proof method bas... View full abstract»

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  • Low latency word serial CORDIC

    Publication Year: 1997, Page(s):124 - 131
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    In this paper we present a modification of the CORDIC algorithm which reduces the number of iterations almost to half by merging two successive iterations of the basic algorithm. The two coefficients per iteration are obtained with only a small increase in the cycle time by estimating one of the coefficients. A correcting iteration method is used to correct the possible errors produced by the esti... View full abstract»

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  • A VLSI architecture for image geometrical transformations using an embedded core based processor

    Publication Year: 1997, Page(s):86 - 95
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    This paper presents a circuit dedicated to real time geometrical transforms of pictures. The supported transforms are third degree polynomials of two variables. The post-processing is performed by a bilinear filter. An embedded DSP core is in charge of high level, low rate, control tasks while a set of hard wired units is in charge of computing intensive low level tasks View full abstract»

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  • On core and more: a design perspective for systems-on-a-chip

    Publication Year: 1997, Page(s):448 - 457
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    In this survey, key drivers in design methodology are provided that enable successful design of systems-on-a-chip for the highly competitive telecommunications market. Main components of a design environment are described that fulfill the requirements of today's system design: efficient verification by means of fast simulation, integration of intellectual property, support of HW/SW co-design by me... View full abstract»

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  • An efficient video decoder design for MPEG-2 MP@ML

    Publication Year: 1997, Page(s):509 - 518
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    In this paper, we present an efficient MPEG-2 video decoder architecture design to meet MP@ML real-time decoding requirement. The overall architecture, as well as the design of the major function-specific processing blocks, such as the variable-length decoder, the inverse 2-D discrete cosine transform unit, and the motion compensation unit, are discussed. A hierarchical and distributed controller ... View full abstract»

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  • Architectural approaches for video compression

    Publication Year: 1997, Page(s):176 - 185
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (584 KB)

    An overview on architectures for implementations of current video compression schemes is given. Dedicated as well as programmable approaches are discussed. Examples for dedicated function-specific implementations include architectures for DCT and block matching. For programmable video signal processors, a number of architectural measures to increase video compression performance are reviewed. Actu... View full abstract»

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  • Scheduling in co-partitioned array architectures

    Publication Year: 1997, Page(s):219 - 228
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    We consider a balanced combined application of the known LPGS- and LSGP-partitioning which we call co-partitioning. This approach allows a structural adjustment of the array design as well as a balancing of the size of the local memory and the IO-demand between the processing elements of the co-partitioned array. We determine the size of the LSGP-partitions such that there exists a sequential sche... View full abstract»

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  • Processor elements for the standard cell implementation of residue number systems

    Publication Year: 1997, Page(s):116 - 123
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    In this article processor elements for the effective implementation of standard cell circuits based on residue number systems (RNS) are presented. Two new processors are proposed helping to reduce the hardware requirements of the implementations. Following a new strategy for implementation a comparison between other circuits discussed in past prove the new method and cells to lead to faster and sm... View full abstract»

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  • Libraries of schedule-free operators in Alpha

    Publication Year: 1997, Page(s):239 - 248
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    This paper presents a method, based on the formalism of affine recurrence equations, for the synthesis of digital circuits exploiting parallelism at the bit-level. In the initial specification of a numerical algorithm, the arithmetic operators are replaced with their yet unscheduled (schedule-free) binary implementation as recurrence equations. This allows a bit-level dependency analysis yielding ... View full abstract»

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  • Buffer size optimization for full-search block matching algorithms

    Publication Year: 1997, Page(s):76 - 85
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint. As a result, a systematic design procedure for buffer optimization is derived to reduce realization cost View full abstract»

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  • A datapath generator for full-custom macros of iterative logic arrays

    Publication Year: 1997, Page(s):438 - 447
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    A new flexible datapath generator which allows the automated design of full-custom macros covering dedicated filter structures as well as programmable DSP cores is presented. The underlying concept combines the advantages of full-custom designs concerning power dissipation, silicon area, and throughput rate with a moderate design effort. In addition, the datapath generator can be easily included i... View full abstract»

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  • On computing with locally-interconnected architectures in atomic/nanoelectronic systems

    Publication Year: 1997, Page(s):14 - 23
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    The past decade has seen tremendous experimental and theoretical progress in the field of mesoscopic devices and molecular self assembly techniques, leading to laboratory demonstration of many new device concepts. While these studies have been important from a fundamental physics perspective, it has been recognized by many that they may offer new insights into building a future generation of compu... View full abstract»

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  • Automatic data mapping of signal processing applications

    Publication Year: 1997, Page(s):350 - 362
    Cited by:  Papers (4)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    This paper presents a technique to map automatically a complete digital signal processing (DSP) application onto a parallel machine with distributed memory. Unlike other applications where coarse or medium grain scheduling techniques can be used, DSP applications integrate several thousand of tasks and hence necessitate fine grain considerations. Moreover finding an effective mapping imperatively ... View full abstract»

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  • An efficient architecture for the in place fast cosine transform

    Publication Year: 1997, Page(s):499 - 508
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    The cosine transform (DCT) is in the core of image encoding and compression applications. We present a new architecture to efficiently compute the fast direct and inverse cosine transform which is based on reordering the butterflies after their computation. The designed architecture exploits locality, allowing pipelining between stages and saving memory (in place). The result is an efficient archi... View full abstract»

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  • A strategy for determining a Jacobi specific dataflow processor

    Publication Year: 1997, Page(s):53 - 64
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    In this paper we present a strategy for determining a dataflow processor which is intended for the execution of Jacobi algorithms which are found in the application domain of array processing and other real-lime adaptive signal processing applications. Our strategy to determine a processor for their execution is to exploit the quasi regularity property in their dependence graph representations in ... View full abstract»

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  • Performance model of the Argonne Voyager multimedia server

    Publication Year: 1997, Page(s):316 - 327
    Cited by:  Papers (2)  |  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    The Argonne Voyager Multimedia Server is being developed in the Futures Lab of the Mathematics and Computer Science Division at Argonne National Laboratory. As a network based service for recording and playing multimedia streams, it is important that the Voyager system be capable of sustaining certain minimal levels of performance in order for it to be a viable system. In this article, we examine ... View full abstract»

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