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2009 IEEE Workshop on Microelectronics and Electron Devices

Date 3-3 April 2009

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Displaying Results 1 - 25 of 34
  • [Title page]

    Publication Year: 2009, Page(s): i
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  • [Copyright notice]

    Publication Year: 2009, Page(s): ii
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  • Table of contents

    Publication Year: 2009, Page(s):iii - iv
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  • General Chairs message

    Publication Year: 2009, Page(s):v - vi
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  • management Committee

    Publication Year: 2009, Page(s): vii
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  • Technical program

    Publication Year: 2009, Page(s):viii - ix
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  • Kapur Keynote Speaker

    Publication Year: 2009, Page(s):x - xi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (170 KB) | HTML iconHTML

    ISET has developed and patented a unique process for manufacturing Copper Indium Gallium Diselenide (CIGS) solar cells using an 'Ink Based' process in which semiconductor precursors are printed both on rigid and flexible substrates. This process has the potential to achieve grid parity for PV generated electricity in the near future. This presentation will describe ISET's 'Ink Based' process for f... View full abstract»

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  • Welser Keynote Speaker

    Publication Year: 2009, Page(s):xii - xiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    In this talk, the scaling challenges facing the current CMOS technology roadmap will be discussed, along with the ultimate limits for charge-switching based devices. From this motivation, the current status of the NRI program will be discussed, with an overview of the current research topics being investigated at the NRI centers. View full abstract»

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  • Edelstein - Invited Speaker

    Publication Year: 2009, Page(s): xiv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (154 KB) | HTML iconHTML

    Summary form only given: This talk will present a broad and detailed discussion of technical issues facing advanced Cu/low-k and /ULK BEOL technologies, and potential solutions being worked on to address them. Of particular focus will be the relationship between integration and reliability for the issues. Some key metallization, dielectric, and packaging elements will be addressed. Today, work has... View full abstract»

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  • Misra - Invited Speaker

    Publication Year: 2009, Page(s): xv
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB) | HTML iconHTML

    In recent years, high-k dielectrics have been successfully implemented in CMOS logic devices wherein their use has led to lower leakages, better gate control and in turn continued downscaling. While high-k dielectrics materials and process flows are continuously being fine tuned for logic devices, their applications in other non-CMOS insertion are also rapidly emerging. In this talk, we discussed ... View full abstract»

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  • Lundstrom Tutorial

    Publication Year: 2009, Page(s): xvi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (154 KB)

    MOSFET scaling continues to push transistors to smaller and smaller dimensions while advances in nanoscience provide fascinating new opportunities for developing novel electronic device technologies. The central theme of 21st Century electronics will be nanotechnology - nanoscale devices and nanostructured materials that produce gigascale systems. Research today is setting the stage for this revol... View full abstract»

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  • Vogel Tutorial

    Publication Year: 2009, Page(s): xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (157 KB)

    Summary form only given. The traditional planar MOSFET consisting of a silicon substrate, a highly doped polysilicon gate electrode, a gate dielectric of SiO2, and doped source and drain had been the basis of integrated circuits for over 30 years. As these traditional materials have been pushed to their limits, entirely new materials (e.g. high-k gate dielectrics, metal gate electrodes,... View full abstract»

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  • Posters and Abstracts

    Publication Year: 2009, Page(s):xviii - xx
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB)

    Provides an abstract for each of the poster presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Technical reviewers

    Publication Year: 2009, Page(s): xxi
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  • List of Speakers

    Publication Year: 2009, Page(s): xxii
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  • Call for Papers

    Publication Year: 2009, Page(s): xxiii
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  • EOT, Workfunction, and Vfb Roll-Off in HfO2/Metal Gate Stacks

    Publication Year: 2009, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1804 KB) | HTML iconHTML

    At a given thickness of HfO2, atomic layer deposited (ALD) TaN metal-gates showed higher equivalent oxide thickness (EOT) and flat-band-voltage (Vfb) shift compared to physical vapor deposited (PVD) TaSiN after annealing at 750degC for 30 min in N2. TEM data revealed the growth of a thicker interfacial oxide of 1.7 nm for TaN compared to 0.9 nm for TaSiN. In additi... View full abstract»

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  • Low Pressure Chemical Vapor Deposition of Ultra-Thin, Pinhole-Free Amorphous Silicon Films

    Publication Year: 2009, Page(s):1 - 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4780 KB) | HTML iconHTML

    A method to deposit and characterize ultra-thin (<100 Aring) amorphous silicon on silicon dioxide substrates is described. Two Si precursors, silane and disilane were compared for film continuity, measured in terms of pinhole density. Disilane was found to result in pinhole free films as thin as 45 Aring. The differences in sub-monolayer or island-stage film morphology were used to describe the... View full abstract»

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  • Analysis and Optimization of Packaging Structures to Maximize the Thermal Performance of Multi-Finger GaInP/GaAs Collector-Up HBTs

    Publication Year: 2009, Page(s):1 - 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    We develop an elaborate finite-element model to analyze packaging structures of multi-finger GalnP/GaAs collector-up HBTs. Novel packaging structures have been designed and evaluated in detail. With careful optimization, the thermal performance can be maximized and the conventional heat-dissipation configuration can be further reduced by 40%. The results demonstrate that thinning the packaging des... View full abstract»

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  • Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing: Example Using a Phase-Change Memory Test Chip

    Publication Year: 2009, Page(s):1 - 4
    Cited by:  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    We have demonstrated that back-end-of-line (BEOL) processing can successfully be performed in a university environment on die that have been fabricated at a foundry. This processing option enables universities to integrate state-of-the-art feature sizes with low resolution photolithography capabilities, such as achieved with a contact aligner, typically available at universities. With this capabil... View full abstract»

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  • Intrinsic Mechanism of Drain-Lag and Current Collapse in GaN-Based HEMTs

    Publication Year: 2009, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB) | HTML iconHTML

    The intrinsic mechanism of drain-lag and current collapse in GaN-based high-electron-mobility-transistors are studied by using two-dimensional transient simulations. The simulated drain-lag characteristics are in good agreement with the reported experimental data. Dynamic pictures of trapping of hot electron under drain-pulse voltages are discussed in detail. The trapped charges may accumulate at ... View full abstract»

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  • 3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory

    Publication Year: 2009, Page(s):1 - 3
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    A new Technology CAD (TCAD) methodology has been applied to accurately extract cell-cell interference. The new method uses a "DeltaVt ratio" model instead of the conventional "capacitance ratio" model. The new method will be introduced and validated by recent experimental data. The predictions of the cell-cell interference on sub-40 nm floating gate (FG) cells and charge trapped flash (CTF) cells ... View full abstract»

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  • Design of a Novel Capacitorless DRAM Cell with Enhanced Retention Performance

    Publication Year: 2009, Page(s):1 - 4
    Cited by:  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (726 KB) | HTML iconHTML

    A novel capacitorless DRAM cell with enhanced retention performance is investigated. The write / read mechanisms, speed, retention performance are studied with numerical simulations. Further, the manufacturing method of this device is briefly discussed. View full abstract»

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  • Surface and Orientation Dependence on Performance of Trigated Silicon Nanowire pMOSFETs

    Publication Year: 2009, Page(s):1 - 4
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (697 KB) | HTML iconHTML

    Impact of surface and transport, orientation on hole transport in p-type silicon nanowire MOSFET has been studied using atomistic 10-band sp3s*-SO tight-binding valence band model along with semi classical ballistic top-of-the-barrier approach for tri-gated devices. (100) and (110) surface orientations for <100> and <110> transport orientations were studied. Study of channel current an... View full abstract»

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  • Multi-Layer High-K Tunnel Barrier for a Voltage Scaled NAND-Type Flash Cell

    Publication Year: 2009, Page(s):1 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    Low-voltage program/erase (P/E) operations of a NAND-type flash cell have been demonstrated using a multi-layer tunnel barrier. The concept is to achieve low voltage P/E operations similar to a scaled tunnel barrier without compromising retention by exploiting a multi-layer tunnel oxide consisting of a low-k, high-k and low k material. In this study, barrier engineered tunnel oxides of SiO... View full abstract»

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