By Topic

Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on

Date 23-25 Jan. 1990

Filter Results

Displaying Results 1 - 25 of 43
  • 1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (159 KB)
    Freely Available from IEEE
  • Some new algorithms for reconfiguring VLSI/WSI arrays

    Publication Year: 1990, Page(s):229 - 235
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distributio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A methodology for wafer scale integration of linear pipelined arrays

    Publication Year: 1990, Page(s):220 - 228
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A methodology for designing large one-dimensional pipelined array processing architectures where a large number of defects can be expected is presented. Central to the methodology is a functional separation at each processing element between the processing core and the inter-cell communication path. Using an `interconnection harness' which provides the inter-cell communication medium and straps or... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A defect and fault tolerant design of WSI static RAM modules

    Publication Year: 1990, Page(s):213 - 219
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits

    Publication Year: 1990, Page(s):288 - 297
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient cur... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implementation of configurable hardware using wafer scale integration

    Publication Year: 1990, Page(s):68 - 73
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units

    Publication Year: 1990, Page(s):203 - 211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • MUSE: a wafer-scale systolic DSP

    Publication Year: 1990, Page(s):27 - 35
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Defect tolerance scheme for gigaFLOP WSI architectures

    Publication Year: 1990, Page(s):109 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Performance is the one area in which a monolithic technology has potential unmatched by other approaches. Integrating an entire high performance system on a single piece of silicon eliminates the off-chip signal delays encountered in multichip implementations, which can become the performance bottleneck in highly pipelined array architectures. The major problem with achieving full wafer integratio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield modeling and optimization of large redundant RAMs

    Publication Year: 1990, Page(s):273 - 287
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global re... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A high performance single chip FFT array processor for wafer scale integration

    Publication Year: 1990, Page(s):60 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An exper... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 200-Mb wafer scale memory

    Publication Year: 1990, Page(s):5 - 12
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    A wafer scale memory has now been developed that has achieved a high enough yield to make it practical to manufacture. This CMOS wafer scale memory was developed with high density and low cost as higher priorities than high speed. The device fills a gap in the hierarchy of computer memory between high speed, high priced main memory and low speed, low priced off-line or hard disk memory. To achieve... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault tolerance performance of WSI systolic sorter

    Publication Year: 1990, Page(s):196 - 202
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Presents a novel redundancy sorting array for WSI implementation. The redundancy sorting array consists of a mesh connected odd-even transposition sort and a modified bitonic sort with spare cells. The fault tolerance performance of the redundancy sorting array is discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Yield enhancement for WSI array processors using two-and-half-track switches

    Publication Year: 1990, Page(s):243 - 250
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Addresses the enhancement of fabrication yield for arrays of large number of processors. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, the authors are able to develop a reconfiguration a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hybrid wafer scale interconnection inventing a new technology

    Publication Year: 1990, Page(s):308 - 316
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    Describes a monolithic multilayer thin film technology featuring discretionary wiring and a cellular design methodology which borrows heavily from VLSI design/fabrication technology. Referred to herein as Hybrid Wafer Scale Interconnect (HWSI), it preserves in many ways the advantages of monolithic Wafer Scale Integration (WSI), while simultaneously offering higher yield and superior performance t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A linear-array WSI architecture for improved yield and performance

    Publication Year: 1990, Page(s):85 - 91
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Lincoln programmable image-processing wafer

    Publication Year: 1990, Page(s):20 - 26
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabri... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A study of high density multilayer LSI

    Publication Year: 1990, Page(s):322 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Describes a new type of high density multilayer LSI chip which is made up of several piled chips. Prescribed interconnections on the conventional wafer, are fabricated first. Thin chips with through-holes (about the size of pad) are fixed to the available parts of the under-layer chip. Each chip is interconnected through the holes. As a result, the chips will be equivalent to a hybrid IC which has... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • WSI architecture for L-U decomposition: a radar array processor

    Publication Year: 1990, Page(s):102 - 108
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    Presents a wafer scale architecture for a radar array processor. The computation intensive block in this processor is the L-U decomposition block, which is amenable to reconfigurable wafer implementation. The authors' design employs only two types of cells thus facilitating restructuring through laser linking and cutting. Details of these cells are presented as is the mapping of the algorithm to a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Divide-and-conquer in wafer scale array testing

    Publication Year: 1990, Page(s):265 - 271
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Testing of wafer scale arrays is very time consuming if classical loopback testing is used. In this paper, a divide-and-conquer technique for testing wafer scale arrays is presented. The technique is general in the sense that it can be applied to any regular topologies. Although the proposed scheme also suffers from long testing time in the worst case, it is shown to be very efficient for most of ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 64 Mb MROM with good pair selection architecture

    Publication Year: 1990, Page(s):57 - 59
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    The needs for high density mask programmable ROM (MROM) have increased rapidly due to the demand for storing the Kanji character fonts and dictionaries used in Japanese word processors. For example, desktop publishing uses MROMs for 80 M bits fixed data. The authors describe a 64 Mb MROM which employs a `good pair selection' as a type of redundancy technique. Employing the technology a flat cell s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Data manipulator network for WSI designs

    Publication Year: 1990, Page(s):138 - 144
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    Multiprocessor system architectures require the use of INterconnection NETworks (INNETs) to provide for movement of data or instructions between memory and the processing elements. When an INNET is an integral part of the system, a WSI implementation will generally require a large fraction of the wafer area. This paper presents an area-reducing algorithm for the data manipulator network in silicon... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Distributed diagnosis for wafer scale systems

    Publication Year: 1990, Page(s):189 - 195
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. C... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Soft-programmable bypass switch design for defect-tolerant arrays

    Publication Year: 1990, Page(s):236 - 242
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Most wafer-scale processing arrays include bypass switches and wiring to permit signals to be routed around faulty modules. In some cases, the bypass circuitry contains registers to maintain data synchronization. The ideal switch design maximizes routing flexibility and switch yield while minimizing switch area and signal delay. Unfortunately these design goals work at cross-purposes. The goals al... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations

    Publication Year: 1990, Page(s):298 - 307
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.