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1990 Proceedings. International Conference on Wafer Scale Integration

23-25 Jan. 1990

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  • 1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2)

    Publication Year: 1990
    Request permission for commercial reuse | PDF file iconPDF (159 KB)
    Freely Available from IEEE
  • Fault tolerance performance of WSI systolic sorter

    Publication Year: 1990, Page(s):196 - 202
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    Presents a novel redundancy sorting array for WSI implementation. The redundancy sorting array consists of a mesh connected odd-even transposition sort and a modified bitonic sort with spare cells. The fault tolerance performance of the redundancy sorting array is discussed View full abstract»

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  • Distributed diagnosis for wafer scale systems

    Publication Year: 1990, Page(s):189 - 195
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. C... View full abstract»

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  • Effects of switch failure on soft-configurable WSI yield

    Publication Year: 1990, Page(s):152 - 159
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yie... View full abstract»

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  • WSI architecture of a neurocomputer module

    Publication Year: 1990, Page(s):124 - 130
    Cited by:  Papers (7)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm2 soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized m... View full abstract»

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  • Implementation of configurable hardware using wafer scale integration

    Publication Year: 1990, Page(s):68 - 73
    Cited by:  Papers (1)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    In recent years a new class of integrated circuits has emerged which can be configured dynamically to implement gate level logic designs. This class of device is termed configurable hardware. These structures can be used to implement important algorithms with much higher performance than conventional computers and board designs using configurable hardware as a computation engine have been proposed... View full abstract»

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  • A methodology for wafer scale integration of linear pipelined arrays

    Publication Year: 1990, Page(s):220 - 228
    Cited by:  Papers (2)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A methodology for designing large one-dimensional pipelined array processing architectures where a large number of defects can be expected is presented. Central to the methodology is a functional separation at each processing element between the processing core and the inter-cell communication path. Using an `interconnection harness' which provides the inter-cell communication medium and straps or... View full abstract»

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  • Hierarchical fault tolerance for 3D microelectronics

    Publication Year: 1990, Page(s):174 - 188
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    Describes recent progress in the area of in-use fault tolerance for a massively parallel array processor. Specifically, the authors have taken the existing architecture of the Hughes 3D Computer and added fault tolerance capability to it. This has been possible to accomplish in modular, uniform way because of the unique circuit partitioning and implementation of the 3D Computer. The single instruc... View full abstract»

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  • Multiple fault detection and location in WSI baseline interconnection networks

    Publication Year: 1990, Page(s):145 - 151
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Presents an approach for the full diagnosis (detection and location) of baseline interconnection networks implemented in WSI. A multiple fault model as applicable to production of these devices, is assumed. This implies that a totally exhaustive combinatorial fault model is used in the analysis. It is proved that the maximum number of tests for detecting multiple faults (i.e. 2(1+log2... View full abstract»

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  • Introduction of a new architecture for wafer integration through configuration hierarchies: resulting in practical monolithic self configuring wafer scale integration

    Publication Year: 1990, Page(s):92 - 101
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    Currently a monolithic self configuring test structure has been fabricated which achieves wafer scale integration levels through General Dynamics patented architecture, new technology and methodologies. The test structure uses a new double metal 3.0-micron GD/P:WSI CMOS technology. The device was not developed as a functional product, but rather as a test of the configuration manager, configuratio... View full abstract»

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  • A general configurable architecture for WSI implementation for neural nets

    Publication Year: 1990, Page(s):116 - 123
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    Presents a solution that allows flexible mapping of neural nets (such as multi-layered ones) onto uncommitted processing arrays in which a large number of processing elements are interconnected by a switched-bus network. The basic algorithms leading to such mapping are outlined, providing a balance between structure simplicity and parallelism of operation speed. A protocol by which the array can b... View full abstract»

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  • A high performance single chip FFT array processor for wafer scale integration

    Publication Year: 1990, Page(s):60 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    An architecture with p multiplier-adder's per butterfly stage has been developed to implement a radix p FFT. It is based on the p-fold symmetry in radix p constant geometry FFT algorithm. A methodology to realize a high radix processing element with lower radix hardware is presented. It is suitable for wafer scale integration. The latency and throughput of this architecture are evaluated. An exper... View full abstract»

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  • Divide-and-conquer in wafer scale array testing

    Publication Year: 1990, Page(s):265 - 271
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (384 KB)

    Testing of wafer scale arrays is very time consuming if classical loopback testing is used. In this paper, a divide-and-conquer technique for testing wafer scale arrays is presented. The technique is general in the sense that it can be applied to any regular topologies. Although the proposed scheme also suffers from long testing time in the worst case, it is shown to be very efficient for most of ... View full abstract»

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  • MUSE: a wafer-scale systolic DSP

    Publication Year: 1990, Page(s):27 - 35
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-t... View full abstract»

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  • A defect and fault tolerant design of WSI static RAM modules

    Publication Year: 1990, Page(s):213 - 219
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic ... View full abstract»

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  • A visually oriented architectural fault simulation environment for WSI

    Publication Year: 1990, Page(s):167 - 173
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A visually oriented fault simulation environment for WSI architectures based on behavioral simulation of parallel message passing processors and switch-level fault simulation of selected processors is described. The environment was implemented by interfacing the CHAMP switch-level simulator with the OODRA behavioral simulator. The simulation environment was used to measure the fault coverage for a... View full abstract»

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  • Data manipulator network for WSI designs

    Publication Year: 1990, Page(s):138 - 144
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    Multiprocessor system architectures require the use of INterconnection NETworks (INNETs) to provide for movement of data or instructions between memory and the processing elements. When an INNET is an integral part of the system, a WSI implementation will generally require a large fraction of the wafer area. This paper presents an area-reducing algorithm for the data manipulator network in silicon... View full abstract»

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  • A linear-array WSI architecture for improved yield and performance

    Publication Year: 1990, Page(s):85 - 91
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when... View full abstract»

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  • Defect tolerance scheme for gigaFLOP WSI architectures

    Publication Year: 1990, Page(s):109 - 115
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Performance is the one area in which a monolithic technology has potential unmatched by other approaches. Integrating an entire high performance system on a single piece of silicon eliminates the off-chip signal delays encountered in multichip implementations, which can become the performance bottleneck in highly pipelined array architectures. The major problem with achieving full wafer integratio... View full abstract»

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  • Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits

    Publication Year: 1990, Page(s):288 - 297
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    Investigations have shown that the layout of power lines and isolation circuits as well as the modules' circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient cur... View full abstract»

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  • The WASP demonstrator programme: the engineering of a wafer-scale system

    Publication Year: 1990, Page(s):43 - 49
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of t... View full abstract»

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  • A 64 Mb MROM with good pair selection architecture

    Publication Year: 1990, Page(s):57 - 59
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    The needs for high density mask programmable ROM (MROM) have increased rapidly due to the demand for storing the Kanji character fonts and dictionaries used in Japanese word processors. For example, desktop publishing uses MROMs for 80 M bits fixed data. The authors describe a 64 Mb MROM which employs a `good pair selection' as a type of redundancy technique. Employing the technology a flat cell s... View full abstract»

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  • A self-test methodology for restructurable WSI

    Publication Year: 1990, Page(s):258 - 264
    Cited by:  Papers (5)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Progress in Wafer Scale Integration (WSI) has brought the problems of system level testing into the semiconductor manufacturing arena. Full wafer testing is complicated by the reduced controllability and observability implicit at this level of integration. Under a DARPA sponsored microelectronics research project at the University of South Florida, several monolithic WSI designs are being develope... View full abstract»

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  • Wafer scale integration (WSI) of programmable gate arrays (PGA's)

    Publication Year: 1990, Page(s):329 - 338
    Cited by:  Papers (1)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is ... View full abstract»

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  • Yield enhancement for WSI array processors using two-and-half-track switches

    Publication Year: 1990, Page(s):243 - 250
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Addresses the enhancement of fabrication yield for arrays of large number of processors. An array grid model based on two-and-half-track switches is adopted. It is shown that two-and-half-track switches, possessing much better reconfigurability capability than that of one-and-half-track switches, are more suitable for yield enhancement. Moreover, the authors are able to develop a reconfiguration a... View full abstract»

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