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Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on

Date 23-25 Jan. 1990

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  • 1990 Proceedings. International Conference on Wafer Scale Integration (Cat. No.90CH2814-2)

    Publication Year: 1990
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    Freely Available from IEEE
  • Effects of switch failure on soft-configurable WSI yield

    Publication Year: 1990 , Page(s): 152 - 159
    Cited by:  Papers (5)
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    A fault tolerant switch network is evaluated, using a pipelined memory system as an example application. Monte Carlo simulation predicts the yield of each circuit piece directly from the layout. Circuit yields are combined with a system model to predict wafer yield. Previous work described system models based on site yield. System models requiring low latency are shown to also depend on switch yield View full abstract»

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  • Defect tolerant implementations of feed-forward and recurrent neural networks

    Publication Year: 1990 , Page(s): 160 - 166
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    Many of the defect tolerant techniques employed to achieve wafer-scale integration can also be used to construct flexible and scalable architectures. These techniques are applied to two artificial neural networks: a feed-forward analog network with backpropagation and an efficient digital recurrent network View full abstract»

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  • Defect tolerant sorting networks for WSI implementation

    Publication Year: 1990 , Page(s): 131 - 137
    Cited by:  Papers (3)
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    To overcome the yield problem in WSI, it is necessary to include redundancy and use more regular architectures for implementation. The authors present a novel hierarchical fault tolerant sorting network which satisfies both application requirements and area-time complexity constraints. It is very regular in structure and hence more easily reconfigurable than any existing sorting network with the same time complexity. Redundancy is provided at each level of the hierarchy. Hierarchical reconfiguration is implemented by replacing the faulty cells with spare cells at the lowest level first, and go to the next higher level to perform reconfiguration if there is not enough redundancy at the current level. In addition to defect tolerance after fabrication, these redundant cells can also be used for single error correction at run time View full abstract»

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  • Hybrid wafer scale interconnection inventing a new technology

    Publication Year: 1990 , Page(s): 308 - 316
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    Describes a monolithic multilayer thin film technology featuring discretionary wiring and a cellular design methodology which borrows heavily from VLSI design/fabrication technology. Referred to herein as Hybrid Wafer Scale Interconnect (HWSI), it preserves in many ways the advantages of monolithic Wafer Scale Integration (WSI), while simultaneously offering higher yield and superior performance typically associated with optimized subassemblies. It is noteworthy that many `monolithic' WSI systems currently under development utilize the same, or even more discrete subassemblies, than the proposed HWSI technology View full abstract»

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  • A visually oriented architectural fault simulation environment for WSI

    Publication Year: 1990 , Page(s): 167 - 173
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    A visually oriented fault simulation environment for WSI architectures based on behavioral simulation of parallel message passing processors and switch-level fault simulation of selected processors is described. The environment was implemented by interfacing the CHAMP switch-level simulator with the OODRA behavioral simulator. The simulation environment was used to measure the fault coverage for a digital adaptive beamforming architecture with a synthetic workload. Fault coverage variation with input set size and array location was investigated. The rate at which faults produce errors in the architecture was also measured View full abstract»

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  • Some new algorithms for reconfiguring VLSI/WSI arrays

    Publication Year: 1990 , Page(s): 229 - 235
    Cited by:  Papers (1)
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    Deals with the issue of reconfiguring processor arrays in the presence of faulty processors and fixed hardware resources. The models discussed consist of a set of identical Processing Elements (PEs) embedded in a flexible interconnection structure that is configured in the form of a rectangular grid. Furthermore in order to incorporate fault tolerance a given array has a pre-determined distribution of spare PEs. The general issue in reconfiguration is to replace faulty non-spare PEs by healthy spare ones, subject to given hardware constraints. The authors present some new algorithms for reconfiguring N×( N+1) arrays (where the spare PEs are configured in the form of a spare row) into N×N arrays when N of the PEs are faulty. The algorithms developed are simple and perform better than other reconfiguration algorithms presented in the literature View full abstract»

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  • 200-Mb wafer scale memory

    Publication Year: 1990 , Page(s): 5 - 12
    Cited by:  Papers (11)
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    A wafer scale memory has now been developed that has achieved a high enough yield to make it practical to manufacture. This CMOS wafer scale memory was developed with high density and low cost as higher priorities than high speed. The device fills a gap in the hierarchy of computer memory between high speed, high priced main memory and low speed, low priced off-line or hard disk memory. To achieve high density, standard 1-Mb DRAMs with a small amount of control logic were arranged as an array on the wafer. Partially good DRAMs are used as the basis for these devices, and several redundancy techniques requiring no additional process steps are used to increase yield. Since the number of wire bonds and solder joints was reduced by 90% compared to the same device manufactured using discrete DRAM chips, the reliability factor of these devices was greatly increased View full abstract»

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  • The Lincoln programmable image-processing wafer

    Publication Year: 1990 , Page(s): 20 - 26
    Cited by:  Papers (6)
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    The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication View full abstract»

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  • Wafer scale integration (WSI) of programmable gate arrays (PGA's)

    Publication Year: 1990 , Page(s): 329 - 338
    Cited by:  Papers (1)  |  Patents (7)
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    Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM's. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as Programmable Gate Array (PGA), which is also known as a Logic Component Array (LCA) View full abstract»

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  • A general configurable architecture for WSI implementation for neural nets

    Publication Year: 1990 , Page(s): 116 - 123
    Cited by:  Papers (4)
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    Presents a solution that allows flexible mapping of neural nets (such as multi-layered ones) onto uncommitted processing arrays in which a large number of processing elements are interconnected by a switched-bus network. The basic algorithms leading to such mapping are outlined, providing a balance between structure simplicity and parallelism of operation speed. A protocol by which the array can be configured (and, therefore, initialized) is presented: nominal operation is then described, and it is seen that the same solution providing for initialization supports also subsequent algorithms. The structure of the basic elements of the architecture (switches and processing elements) is detailed, so as to allow an evaluation of complexity as regards silicon requirements in CMOS View full abstract»

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  • Hierarchical fault tolerance for 3D microelectronics

    Publication Year: 1990 , Page(s): 174 - 188
    Cited by:  Papers (3)
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    Describes recent progress in the area of in-use fault tolerance for a massively parallel array processor. Specifically, the authors have taken the existing architecture of the Hughes 3D Computer and added fault tolerance capability to it. This has been possible to accomplish in modular, uniform way because of the unique circuit partitioning and implementation of the 3D Computer. The single instruction multiple data stream (SIMD) design of the 3D Computer greatly simplifies the control and reconfiguration process, while the fine-grained parallelism permits a high degree of redundancy with very low overhead. They have adopted a hierarchical strategy that mirrors the structure of the 3D Computer itself. Static reconfiguration is supported by special purpose hardware, the Realignment Plane wafer type, which allows them to treat failures uniformly at the row/column, processing element, and functional element levels View full abstract»

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  • MUSE: a wafer-scale systolic DSP

    Publication Year: 1990 , Page(s): 27 - 35
    Cited by:  Papers (4)
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    MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 μm CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4" by 4" silicon substrate View full abstract»

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  • The WASP demonstrator programme: the engineering of a wafer-scale system

    Publication Year: 1990 , Page(s): 43 - 49
    Cited by:  Papers (11)
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    The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2) View full abstract»

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  • WSI architecture for L-U decomposition: a radar array processor

    Publication Year: 1990 , Page(s): 102 - 108
    Cited by:  Papers (3)  |  Patents (2)
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    Presents a wafer scale architecture for a radar array processor. The computation intensive block in this processor is the L-U decomposition block, which is amenable to reconfigurable wafer implementation. The authors' design employs only two types of cells thus facilitating restructuring through laser linking and cutting. Details of these cells are presented as is the mapping of the algorithm to a systolic array architecture. In particular, the authors discuss the internal switches and multiplexers of the multiply-accumulate cell, and the external switches. Also described is the fast reciprocal cell which is expressly developed for this radar processor. Finally, the reconfiguration strategy is discussed View full abstract»

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  • WSI architecture of a neurocomputer module

    Publication Year: 1990 , Page(s): 124 - 130
    Cited by:  Papers (5)  |  Patents (4)
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    Discusses application and technology related constraints on the implementation of neurocomputing systems on a wafer. The resulting neurocomputer architecture builds on the experience obtained with a 42 cm2 soft-configured chip which carries a 2-dimensional array of multipliers in CMOS. The architecture is specially adapted to pattern recognition of video images by means of generalized multilayer-perceptrons View full abstract»

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  • Yield modeling and optimization of large redundant RAMs

    Publication Year: 1990 , Page(s): 273 - 287
    Cited by:  Patents (8)
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    Presents and analyzes redundant large area TRAM architectures (64 to 512 Mbit) for variations in redundancy level and determine the optimal redundancy organization for yield enhancement. A hierarchical redundancy scheme is used for defect tolerance and the yield of the redundant RAM is modelled using a compounded Poisson model. Results are presented that show the tradeoff in local versus global redundancy schemes for TRAM View full abstract»

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  • Distributed diagnosis for wafer scale systems

    Publication Year: 1990 , Page(s): 189 - 195
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    The increasing demand for high performance systems has led to the design of systems comprised of a large number of processing elements on a single wafer. This paper presents a distributed diagnosis algorithm for wafer scale systems. Unlike other approaches, the algorithm does not assume diagnostic circuits are fault-free. The algorithm is simple enough to be realized with small circuit overhead. Computer simulation has shown that even for low unit yields, extremely high performance (fault coverage) can be achieved by properly tuning the algorithm parameters View full abstract»

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  • A defect and fault tolerant design of WSI static RAM modules

    Publication Year: 1990 , Page(s): 213 - 219
    Cited by:  Papers (5)  |  Patents (3)
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    Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration View full abstract»

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  • WASP: a wafer-scale massively parallel processor

    Publication Year: 1990 , Page(s): 36 - 42
    Cited by:  Papers (8)
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    The new decade (1990-2000) heralds the age of very powerful compute-, graphics- and information-servers, based on Massively Parallel Processors (mppS), capable of TOPS (Tera Operations-Per-Second) performance in networked scientific, engineering, knowledge-base and artificial intelligence applications. This paper describes a WSI associative string processor (WASP) in CMOS fault-tolerant WSI MPP architecture which satisfies both the architectural and engineering requirements outlined and, thereby, offers a step-function improvement in cost-effectiveness compared with first-generation MPPs View full abstract»

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  • A linear-array WSI architecture for improved yield and performance

    Publication Year: 1990 , Page(s): 85 - 91
    Cited by:  Papers (6)  |  Patents (2)
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    A new architecture is proposed for constructing a linear array from cells on a partially defective wafer. Each cell connects to its four nearest neighbors in a way that guarantees a fixed delay between any pair of communicating cells. Phase-shifted synchronous clocking further improves performance. A simple configuration scheme is presented, and is shown to exceed 96% harvest of working cells when the configuration logic yield is above 75%. The architecture is shown to compare favorably to existing schemes in terms of performance, yield and overhead View full abstract»

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  • Re-wafer scale integration: a new approach to active phased arrays

    Publication Year: 1990 , Page(s): 50 - 56
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    Describes a new approach to active phased array technology. Here, several modules are fabricated at the same time and placed in a layered structure. The layers include the RF modules, cooling manifold, DC bias distribution, RF manifold, and radiating elements. In this configuration, 16 or more T/R modules are fabricated on a single 3-inch GaAs wafer. The realization of multiple modules on a wafer is made possible by redundancy of circuit elements and novel mechanical switches. Preliminary results on these efforts are presented View full abstract»

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  • Multiple fault detection and location in WSI baseline interconnection networks

    Publication Year: 1990 , Page(s): 145 - 151
    Cited by:  Papers (5)
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    Presents an approach for the full diagnosis (detection and location) of baseline interconnection networks implemented in WSI. A multiple fault model as applicable to production of these devices, is assumed. This implies that a totally exhaustive combinatorial fault model is used in the analysis. It is proved that the maximum number of tests for detecting multiple faults (i.e. 2(1+log2N), where N is the number of inputs/outputs), can be used to locate and identify multiple faulty switching elements provided that no intermittent and/or transient behaviour is present, i.e. using the definition of no logically undefined and no undetermined outputs are present. The proposed diagnostic technique is based on a process which reveals the switching state of each element on a stage by stage basis using the test set. No additional hardware is therefore required. The proposed technique can be efficiently used in the manufacturing of complex interconnection networks using advanced integration techniques such as WSI View full abstract»

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  • Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations

    Publication Year: 1990 , Page(s): 298 - 307
    Cited by:  Papers (6)  |  Patents (3)
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    Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Ω has been achieved with expansions of 20×20 μm2. However, expansions of 14×14 μm2 are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1×106 A/cm2 and temperatures up to 270°C were carried out. Materials were analysed with EDX, AES, and SIMS View full abstract»

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  • Soft-programmable bypass switch design for defect-tolerant arrays

    Publication Year: 1990 , Page(s): 236 - 242
    Cited by:  Papers (4)
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    Most wafer-scale processing arrays include bypass switches and wiring to permit signals to be routed around faulty modules. In some cases, the bypass circuitry contains registers to maintain data synchronization. The ideal switch design maximizes routing flexibility and switch yield while minimizing switch area and signal delay. Unfortunately these design goals work at cross-purposes. The goals also vary in importance, depending on the wafer architecture. For example, some architectures can cope with bypass logic failures, while others cannot. The ability to cope with failures may be a function of the failure mode. The author examines a number of bypass switch circuit and layout designs, and how well they meet to the design goals. He uses the DVLASIC distributed catastrophic fault yield simulator to perform yield computations View full abstract»

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