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Displaying Results 1 - 25 of 35
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Design of 24 bit DSP for audio algorithms
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PDF (112 KB)
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Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations
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PDF (137 KB)
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High performance on-chip-network architecture with multiple channels and dual routing
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PDF (352 KB)
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Design of parallel BCH decoder for MLC memory
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PDF (200 KB)
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1.5 MHz, 300 mA step-down switching regulator
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PDF (359 KB)


