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SoC Design Conference, 2008. ISOCC '08. International

Date 24-25 Nov. 2008

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  • 12-bit 80MSPS double folding/interpolation A/D converter

    Publication Year: 2008 , Page(s): III-1 - III-2
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1222 KB) |  | HTML iconHTML  

    In this paper, a CMOS analog-to-digital converter (ADC) with a 12-bit 80 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a double folding and interpolating structure. An even folding circuit technique for the high resolution and high speed ADC are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 um 1-poly 6-metal CMOS technology. The active area is 1.6 mm2 and 195 mw at 1.8 V power supply. The DNL and INL are within plusmn4/plusmn4LSB, respectively. The measured result of SNDR is 46 dB, when Fin=1MHz at Fs=80 MHz. View full abstract»

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  • 10-bit charge redistributed D/A Converter for TFT-LCD driver

    Publication Year: 2008 , Page(s): III-3 - III-4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    In this paper, a 10-bit charge redistributed CMOS D/A Converter is presented for LCD panel driving. The structure of the charge redistributed D/A Converter is consisted of OP-AMP as Unit Gain Sampler, two parallel capacitors, a CMOS switch, and a digital block. In order to solve the capacitor mismatching problem, a compensation method to use alternate capacitors is proposed. Further, the D/A Converter has a digital block to change the digital parallel data into the serial data, which is based on JCCG (Johnson Counter Clock Generator). The chip was fabricated with a 0.35 mum 1-poly 4-metal n-well CMOS technology. The effective chip area is 430 mum times 880 mum and it dissipates about 0.607 mW power consumption at 3.3V power supply. The INL and DNL is within plusmn0.41 LSB and plusmn0.11 LSB, respectively. View full abstract»

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  • Automatic red-eye detection and correction system for mobile sevices

    Publication Year: 2008 , Page(s): III-5 - III-6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    This paper presents an automatic red-eye detection and correction system. In order to detect red eye, we propose to use two information sources: color around the eyes and eye's round shape. The color information is from the red, highlight, and skin masks. Eye-shape is from our proposed real-time 2-dimensional grouping algorithm called ARTS. Our correction method promises to a natural-looking result. We designed the hardware using Verilog HDL, and successfully built and tested it using an FPGA device, a USB interface board, and a two-megapixel CMOS sensor. With a TSMC 0.25-mum ASIC library, the gate count was 325,167 gates, and the maximum data arrival time was 41.8 [MHz]. View full abstract»

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  • Design of rasterization unit applicable to mobile graphics system

    Publication Year: 2008 , Page(s): III-7 - III-8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    This paper describes rasterization unit that converts triangle represented three vertices to pixel data including screen coordinates, depth coordinates and color. The rasterization unit consists of about 21,400 gates and can operate about 80 Mhz at 0.35 um CMOS technology. The rate of pixel generation is maximum 80 Mpixels/sec so that applicable to mobile graphics system. View full abstract»

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  • Design of 24 bit DSP for audio algorithms

    Publication Year: 2008 , Page(s): III-9 - III-10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB) |  | HTML iconHTML  

    This paper describes the architecture and design procedure of a DSP (Digital Signal Processor) for the digital audio applications. The suggested DSP has fixed 24 bit data structure, 6 stage pipeline, and 125 instructions. Some of the instructions are specially designed for the audio signal processing. Almost instructions are completed within a single cycle. The designed DSP has been verified by comparing the results from CBS (Cycle based Simulator) and those of HDL simulation through the single instruction set test, the instruction combination test, and real audio applications. Finally, we confirm by the HDL simulation that the DSP carried out successfully out ADPCM and MPEG-2 AAC decoding algorithm. The DSP core is implemented in 0.18 mum CMOS process and operates at 120 MHz. View full abstract»

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  • Design of On-Chip Debug System for embedded processor

    Publication Year: 2008 , Page(s): III-11 - III-12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (137 KB) |  | HTML iconHTML  

    In this paper, we introduce on-chip debug system (OCDS) which supports symbolic debugging at c-level using OCD integrated Debug-logic into target processor. The OCDS consist of SW debugger that supports a functionality of symbolic debugging, OCD (on-chip debugger) serving as a debugger of internal state of target processor, and Interface & Control block interfacing SW debugger and OCD. After OCD block is interfaced with 32 bit RISC processor core and then implemented with FPGA, OCD is connected by Interface & Control block, and SW debugger. The verification of the design is carried out through device recognition, carrying-out instructions of JTAG(joint test action group), reading and writing the internal registers of the processor and memory, and checking the emulation functions such as setting break-points and watch points. View full abstract»

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  • Design & verification of 16 bit RISC processor

    Publication Year: 2008 , Page(s): III-13 - III-14
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (230 KB) |  | HTML iconHTML  

    The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA. View full abstract»

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  • Implementation of the Levinson algorithm for MMSE equalizer

    Publication Year: 2008 , Page(s): III-15 - III-16
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (78 KB) |  | HTML iconHTML  

    In wireless communication system applying the minimum mean square error (MMSE) as its equalization algorithm, the equalizer is one of the most critical part in terms of the computational complexity of the baseband signal processing. Hence more efficient algorithm implementing MMSE equalizer is needed to save power consumption and reduce the hardware complexity. In this paper, we implement the recursive Levinson algorithm which is to solve the linear system solution in MMSE equalizer. The Levinson algorithm can be implemented with reduced hardware complexity and better operation speed compared to Cholesky decomposition which is one of linear system solution algorithm. In addition, the recursive algorithm has flexibility on the service quality due to the trade-off between performance and complexity which can be determined by the threshold value. View full abstract»

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  • A 8 Gb/s 4-PAM transmitter in 0.18 μm CMOS technology

    Publication Year: 2008 , Page(s): III-17 - III-18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB) |  | HTML iconHTML  

    A low power 8 Gb/s multilevel pulse amplitude modulation (PAM) transmitter is proposed. 4-PAM enables transmitter to transmit data twice more than binary signaling. Also pre-switching the output driver's current sources decrease the glitches of the output, which helps transmitter to operate at a high speed. The transmitter transmits output by current-mode instead of voltage-mode to increase switching speed of driver. The transmitter is composed of output driver, 4:1 multiplexer, and encoder. Also 27-1 pseudo random bit sequence (PRBS) generator was designed on-chip to provide built-in self test (BIST) operation. The transmitter is designed in 0.18mum CMOS technology and achieves 8 Gb/s, a data eye opening with a height Gt 160 mV with 1.8 V supply voltage. The output driver and entire transmitter consume only 98 mW at 8 Gb/s. View full abstract»

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  • Efficient implementation of linear system solution block using LDLT factorization

    Publication Year: 2008 , Page(s): III-19 - III-20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (82 KB) |  | HTML iconHTML  

    Two implementation forms of linear system solution are described in this paper. Cholesky LLT decomposition require square roots, whereas LDLT decomposition can avoid taking square roots by one more forward-substitute computation. Through computational complexity and hardware size analysis, it is shown that matrix inversion using LDLT decomposition is faster than cholesky decomposition using square root function. Moreover the LDLT decomposition has better performance of 31.4% in hardware size. View full abstract»

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  • High performance IPC hardware accelerator and communication network for MPSoCs

    Publication Year: 2008 , Page(s): III-21 - III-22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (103 KB) |  | HTML iconHTML  

    In this paper, we explain a configurable IPC module for multimedia MPSoCs, which was implemented in a MPW chip that include three ARM7 CPU cores. According to the test results for an M-JPEG and a H.264 decoder, its IPC synchronization overheads are not more than 1% when the synchronization period is about 5000 cycles. View full abstract»

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  • Multi-channel capacitive readout IC for MEMS inertial sensors

    Publication Year: 2008 , Page(s): III-23 - III-24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    A multi-channel capacitive readout IC (integrated-circuit) for MEMS (microelectromechanical systems) inertial sensor is presented. A fully differential, chopper-stabilized SC (switched capacitor) 3-channel charge amplifier is designed. A digital demodulator and a decimator are used to prevent problems of conventional analog multipliers. Performance of the fabricated IC is evaluated with MEMS sensing elements. View full abstract»

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  • ODALRISC: A small, low power, and configurable 32-bit RISC processor

    Publication Year: 2008 , Page(s): III-25 - III-26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB) |  | HTML iconHTML  

    Configurable processor has become popular recently, since it can be easily configured and extended to increase the performance without losing the flexibility of the programmable processor. In the era of MP-SoC, the base versions of configurable processors need to be small and low power consuming because many processors are extended and placed on a single chip and so each processor should be as efficient as possible containing only the functional units and instructions necessary for carrying out the specific task assigned to the processor. In this paper, we present the ODALRISC processor, which is an ultra small and low power consuming configurable 32-bit RISC processor. The base version is synthesized using 0.18 mum technology, taking less than 16 k gates and consuming power less than 0.1 mW/MHz. View full abstract»

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  • A concurrent dual-band CMOS low-noise amplifier for ISM-band application

    Publication Year: 2008 , Page(s): III-27 - III-28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (682 KB) |  | HTML iconHTML  

    A dual-band CMOS low-noise amplifier (LNA) for ISM-band application is reported. For low power and dual band operation, the designed LNA adopts a positive-feedback LC-ladder network. Moreover, for cost effective approach, the LNA has been fabricated using a 0.18-mum mixed-signal CMOS process. The implemented LNA shows gain of 8.3 dB and 11.2 dB, and noise figure (NF) of 6.1 dB and 6.6 dB at 19 GHz and 25 GHz, respectively. The proposed LNA exhibits 8.1 mW power consumption from 0.8 V supply and the active chip area including pad is about 720 times 460 mum2. View full abstract»

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  • Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations

    Publication Year: 2008 , Page(s): III-29 - III-30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (137 KB) |  | HTML iconHTML  

    This paper presents coarse-grained reconfigurable architecture supporting floating-point operations, where each integer processing element is paired with its neighbor to perform floating point operations. One processing element in a pair is in charge of the mantissa part, and the other is in charge of the exponent part. With an 8 times 2 array of processing elements, 8 floating-point operations can be performed at the same time. The chip is fabricated in MagnaChip/Hynix 0.18 mum technology with the gate count of 363,013 and clock frequency of 116.8 MHz in the typical case. View full abstract»

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  • High speed 3D acquisition chip design for robot applications

    Publication Year: 2008 , Page(s): III-31 - III-32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB) |  | HTML iconHTML  

    Obtaining automatic 3D profile of object is one of the most important issues in a robot vision system. We adopt one of the signal separation coding methods called hierarchically orthogonal code (HOC) based on structured light in order to obtain robust depth imaging. To realize this algorithm, high-speed image processing is essential. Because this algorithm requires 17 raw-data pictures to get a picture containing depth information. Therefore, this paper introduces a high-speed hardware platform to perform 3D modeling. Firstly, we implement the platform using FPGA to verify the functionality of our design. Then, our design is fabricated using Samsung 0.18 um CMOS technology. For the chip test, FPGA-based testing board was connected with components for image sensing. The results show that it requires 58 ms to generate one 3D image in realtime. This processing time is 14.5 times faster than the same implementation using software. View full abstract»

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  • High performance on-chip-network architecture with multiple channels and dual routing

    Publication Year: 2008 , Page(s): III-33 - III-34
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB) |  | HTML iconHTML  

    We design and implement an high performance on-chip-network, which is composed of Soc network architecture (SNA) and eXtended SoC Network Protocol (XSNP). The SNA is a hardware architecture for on-chip-buses, which provide simultaneous multiple channels and dual routing. The XSNP is an interface protocol for the SNA which provides compatibility with the AHB protocol. The SNA system is adequate for parallel processing systems with multiple processors. FIR filter systems are designed to verify the performance of the on-chip-bus using 1-, 2-layer AHB and the SNA. The performance is compared using simulation and implementing using FPGAs. View full abstract»

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  • A/D converter using Iterative Divide-by-Two Reference for CMOS image sensor

    Publication Year: 2008 , Page(s): III-35 - III-36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    This paper proposes an ADC using Iterative Divide-by-Two Reference. Using and sharing a single voltage divider reduces silicon area for a column compared with the conventional SA-ADC. An offset-cancelled integrator and a capacitor error averaging method are implemented to decrease the impact of nonlinearities. The ADC is designed in 0.18-mum CMOS process and consumes 0.35-mW of power per ADC, and the active die area is 0.012-mm2. View full abstract»

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  • Design of a flash A/D converter with dual-bootstrapped THA circuit

    Publication Year: 2008 , Page(s): III-37 - III-38
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    This paper describes a 6 bit 1 GS/s CMOS flash A/D converter using dual-bootstrapped THA circuit. The proposed flash architecture employs bootstrap technique in the track and hold circuit for low bit error ratio and high linearity. The measurement result shows a conversion rate of 1Gs/s, SNDR of 35.1dB, DNL/INL of plusmn0.65LSB/plusmn0.80LSB, and power dissipation of 228 mW at 1.8 V. The chip is implemented in a 0.18 mum CMOS 1-poly 6-metal technology and occupies an active area of 0.7 mm2. View full abstract»

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  • Design of memory controller Design of general purpose memory controller

    Publication Year: 2008 , Page(s): III-39 - III-41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (173 KB) |  | HTML iconHTML  

    For memory (RAM or ROM) to store data as memory cells use it. The processor which this element needs certainly needs control, and you shall set up approach relation with memory Algorithm Approach regarding sram Approaching memory shall be controlled according to kinds of memory and processor data so as to be different. A control signal is , so to speak, different in every each memory, this with an address, data, control signals in detail so as to draw it to memory. And a processor does an input and output to any data as go, control it so as to be different. We use a memory controller, and we make it for this so as to control effectively approach between a processor and memory, we will explain the signal control between a processor regarding sound signal data and memory View full abstract»

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  • Varactor tunned high-Q aictive inductor with broadband tuning range

    Publication Year: 2008 , Page(s): III-42 - III-43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB) |  | HTML iconHTML  

    This paper presents a novel high-Q inductor using conventional grounded active inductor and feedback parallel resonance circuit. The proposed high-Q inductor using tunable LC resonance circuit (HITR) consists of the conventional active grounded inductor and feedback parallel resonance circuit which is composed of low-Q spiral inductor and MOS varactor. The novelty of the proposed structure is based on the increase of Q-factor by feeding parallel resonance circuit into gyrator structure. The high-Q inductor is fabricated by 0.18 mum Hynix CMOS technology. The fabricated inductor shows inductance of above 45 nH and Q-factor of over 640 around 5.4 GHz. View full abstract»

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  • Design of low-power and high-speed receiver for mobile display module

    Publication Year: 2008 , Page(s): III-44 - III-45
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (114 KB) |  | HTML iconHTML  

    We newly proposed a low-power and high-speed mobile display digital interface (MDDI) client receiver in this paper. The receiver was designed as a low-power circuit which had a constant current dissipation over variations of the common-mode voltage (VCM) and power supply voltage, and was able to operate at a rate of 450 Mbps or above under the conditions of a power supply of 3.3 V and a temperature range of -40 to 85degC. A test chip was manufactured with the 0.35 mum CMOS process. When a test was done with a function generator, the data receiver and data recovery circuit were functioning normally. View full abstract»

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  • Design of parallel BCH decoder for MLC memory

    Publication Year: 2008 , Page(s): III-46 - III-47
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to correct a small bit error. But the code length n is longer such as a game program stored in a MLC (multi-level cell) flash memory, the decoding circuits takes a lot of computation time. This paper presents a parallel decoding architecture of BCH coding aiming to speed up that guarantees 2-bit error correction. It allows one word data can be fed into the BCH decoder at a time and decoded in parallel. The experimental results show that the proposed (4122, 4096, 2) BCH decoder runs about 7.5 times faster than the binary counterpart even though it has 1.2 times area overhead. View full abstract»

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  • SoC platform design with multi-channel bus architecture

    Publication Year: 2008 , Page(s): III-48 - III-49
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (143 KB) |  | HTML iconHTML  

    We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. The proposed platform is implemented on Altera's EP2C70F672 FPGA device. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus. View full abstract»

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  • 1.5 MHz, 300 mA step-down switching regulator

    Publication Year: 2008 , Page(s): III-50 - III-51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB) |  | HTML iconHTML  

    A switching regulator yields high efficiency and provides a good current driving capability, making it appropriate as a DC-DC converter for mobile devices. The battery voltage can be converted into the operating voltage of the internal circuit. Furthermore, a negative feedback loop can be constructed to restrict change in dc voltage for a stable supply. A current-mode switching regulator adjusts the inductor current to stabilize the output voltage. The designed 1.5 MHz 300 mA step-down switching regulator is implemented in a standard 0.18-mum CMOS process. View full abstract»

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