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2008 3rd International Design and Test Workshop

20-22 Dec. 2008

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Displaying Results 1 - 25 of 87
  • IDTProgram

    Publication Year: 2008, Page(s):I - IV
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  • [Title page]

    Publication Year: 2008, Page(s): i
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  • [Copyright notice]

    Publication Year: 2008, Page(s): ii
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  • Table of contents

    Publication Year: 2008, Page(s):iii - vii
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  • Committees

    Publication Year: 2008, Page(s):viii - x
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  • Welcome to the IDT 2008 Workshop

    Publication Year: 2008, Page(s): xi
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  • Panel session: “Can global economic recession and its possible impact on high tech be considered as opportunity for emerging countries ?”

    Publication Year: 2008, Page(s): xii
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  • Keynote address 1: “built-in-self-test and digital self calibration of RFICs”

    Publication Year: 2008, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    To achieve the highest performance/price ratios of handheld wireless devices, the current trends in wireless chip set development call for multi-standard nanometer CMOS radios integrated on a single chip. This represents a grand challenge to the “yield” of such chip sets and typically requires several silicon spins which will increase the NRE development costs and may result in signi... View full abstract»

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  • Keynote address 2: “Advances in boolean satisfiability and its application in EDA”

    Publication Year: 2008, Page(s): 2
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB)

    In this talk, an overview of the latest advances in SAT technology will be provided. Specifically, the input format of SAT solvers and the common SAT algorithms used to solve decision/optimization problems will be described. In addition, the speaker will highlight the use of SAT algorithms in solving a variety of EDA decision and optimization problems. This should guide researchers in solving thei... View full abstract»

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  • Keynote address 3: “From MARTE to SystemC/VHDL”

    Publication Year: 2008, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB)

    This keynote will present the Gaspard2 model driven engineering framework for the co-design of component-based intensive signal processing applications on multiprocessor systems-on-chip. This framework is implemented as an Eclipse-based application using the Eclipse Modeling Framework. The input language of this framework is a subset of the MARTE standard UML profile with a clearly defined semanti... View full abstract»

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  • Session A1: Networks-on-chip

    Publication Year: 2008, Page(s): 4
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  • Norma: A hierarchical interconnection architecture for Network on Chip

    Publication Year: 2008, Page(s):5 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (215 KB) | HTML iconHTML

    NoC is a potent solution to address design complexity and productivity problems whose its key component is the interconnect architecture which directly affects both cost and performance parameters. The purpose of this paper is to present the basic ideas behind the development of our new hierarchical network-on-chip (NoC) architecture, called ldquoNormardquo that its most distinguished characterist... View full abstract»

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  • Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA

    Publication Year: 2008, Page(s):11 - 16
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6597 KB) | HTML iconHTML

    Multiprocessor system on chip is a concept that aims to integrate multiple hardware and software in a chip. multistage interconnection network is considered as a promising solution for applications which use parallel architectures integrating a large number of processors and memories. in this paper, we present a model of multistage interconnection network and a design of prototyping on FPGA. This ... View full abstract»

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  • Design and implementation of MIC@R router for on-chip networks

    Publication Year: 2008, Page(s):17 - 21
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2915 KB) | HTML iconHTML

    The paper presents a design and implementation of router architecture suitable for Networks-on-Chip (NoC) design. This architecture offers lowest routing latency (1 cycle) and allows supporting several adaptive routing algorithms. Latency reduction is obtained by using Fast Parallel Routing (FPR) arbitration that consists in parallel processing and in one stage the routing decisions and arbitratio... View full abstract»

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  • QSYN: Queueing networks synthesis for system on chip

    Publication Year: 2008, Page(s):22 - 27
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB) | HTML iconHTML

    Queueing networks represent a powerful model of computation (MOC) with strong theoretical foundations and a wide range of applications. Design productivity for system on chip (SOC) requires increasing the level of abstraction for the design of SOC. However, achieving better productivity through raising the level of abstraction can only be obtained with the help of automatic MOC transformation tech... View full abstract»

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  • A combined packet and circuit switching routing algorithm for networks-on-chips

    Publication Year: 2008, Page(s):28 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    A new dynamic switching theme is proposed for networks-on-chips to provide adaptive routing to guarantee a lower packet latency at different injection rates. Router architecture and packet format are developed to support our routing algorithm. Modeling of the router and the routing algorithm was done using SystemC and applied on 2-D mesh network. A new combined switching mode is proposed that dyna... View full abstract»

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  • Networks-on-Chip topology generation techniques: Area and delay evaluation

    Publication Year: 2008, Page(s):33 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB) | HTML iconHTML

    Networks-on-Chip (NoC) topology generation faces a trade-off between cost and performance. In this paper, we evaluate different custom and standard NoC topology generation techniques with respect to area and delay. The area needed for the topologies generated by these techniques is evaluated according to their routers area and number of global links. The delay is compared in terms of average inter... View full abstract»

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  • Session B1: Test issues

    Publication Year: 2008, Page(s): 39
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    Freely Available from IEEE
  • Increasing testability in QCA circuits using a new test method

    Publication Year: 2008, Page(s):40 - 44
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    Recently testing of quantum-dot cellular automata circuits has attracted a lot of attention. This paper proposes a novel method for testing QCA circuits. The method is based on circuit partitioning capability and multi-layer feature of QCA circuits. It can be useful for testing large circuits with many inputs. The proposed test method has potential to increase observability and controllability of ... View full abstract»

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  • QoS testing of service-based applications

    Publication Year: 2008, Page(s):45 - 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB) | HTML iconHTML

    Web services (WSs) are becoming increasingly popular because of their potential in several application domains including e-Enterprise, e-Business, e-Government, and e-Science. Based on open XML standards, WS technology allows the construction of massively distributed and loosely coupled applications. A service composition mechanism should satisfy not only functional properties but also non-functio... View full abstract»

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  • Universal test set for bridging fault detection in reversible circuit

    Publication Year: 2008, Page(s):51 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (188 KB) | HTML iconHTML

    Detection of bridging faults plays a significant role in a reversible circuit. The single and multiple inputs bridging faults model of a reversible circuit is considered here. The paper proposes that only n (number of inputs) number of universal test vectors are sufficient for detection of all single and multiple input bridging faults and all input stuck-at faults of any n-input and n-output rever... View full abstract»

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  • Soundness test cases generation for duration systems

    Publication Year: 2008, Page(s):57 - 62
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1311 KB) | HTML iconHTML

    In this paper, we are interested in testing duration systems. Duration systems are an extension of real-time systems for which delays that separate events depend on the accumulated times spent by the computation at some particular locations of the system. We present an automatic testing method for duration systems that uses the approximation method. This method extends a model using an over approx... View full abstract»

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  • Session A2: Applications design I

    Publication Year: 2008, Page(s): 63
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  • Study of different pulse waveforms and analytical probability of error in TH-PAM ultra wideband systems

    Publication Year: 2008, Page(s):64 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB) | HTML iconHTML

    This paper presents a method for the evaluation of the bit error probability of a time hopping binary pulse amplitude ultra-wideband modulation scheme. We will also study different pulse waveforms applicable in the context of UWB to see the characteristics of each one and the contribution they can provide when used in UWB applications. View full abstract»

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  • A SDR interconnection architecture proposal for SATCOM applications

    Publication Year: 2008, Page(s):69 - 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2376 KB) | HTML iconHTML

    Software defined radio (SDR) is gaining much attention in many application fields, e.g. satellite communication (SATCOM). In this paper, the requirements of SDR architecture for SATCOM application are discussed and a novel network on chip (NoC) architecture proposal are presented in order to achieve these requirements. Compared with several common NoC architectures, the proposed NoC can reduce the... View full abstract»

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