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Proceedings 1997 27th International Symposium on Multiple- Valued Logic

28-30 May 1997

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  • Proceedings 1997 27th International Symposium on Multiple- Valued Logic

    Publication Year: 1997
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    Freely Available from IEEE
  • Decomposition of multiple-valued relations

    Publication Year: 1997, Page(s):13 - 18
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (630 KB)

    This paper presents a new decomposition problem: decomposition of multi-valued (MV) relations, and a method of its solution. Decomposition is non-disjoint and multi-level. A fundamental difference in decomposition of MV functions and MV relations is discussed: the column (cofactor) pair compatibility translates to the group compatibility for functions, but not for relations. This makes the decompo... View full abstract»

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  • Author index

    Publication Year: 1997, Page(s): 293
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    Freely Available from IEEE
  • On the synthesis of MVL functions using input and output phase assignments

    Publication Year: 1997, Page(s):253 - 258
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    In this paper, a number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimization is obtained by constructing a matching-count matrix. The entries of the matching-count matrix MCi,j represent the number of entry matches between the input variable number i in the... View full abstract»

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  • Multiple-valued product-of-sums expression with truncated sum

    Publication Year: 1997, Page(s):103 - 107
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Truncated sum (TSUM for short) can be useful for MV-PLAs realization. This paper introduces multiple-valued product-of-sums expressions where sum refers to TSUM and product does MIN. We investigate the multiple-valued product-of-sums expressions and show the minimization method and the simulation results. We describe the minimization method based on binary Quine-McCluskey algorithm. It is proved t... View full abstract»

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  • Ternary decision diagrams. Survey

    Publication Year: 1997, Page(s):241 - 250
    Cited by:  Papers (22)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (764 KB)

    This paper surveys seven types of TDDs: General-TDD, SOP-TDD, ESOP-TDD, AND-TDD, prime-TDD, EXOR-TDD, and Kleene-TDD. We give new definitions for SOP-TDDs and ESOP-TDDs and introduce unifying terminology. After showing some theorems on complexities, we compare the sizes of these TDDs using benchmark functions. Finally, we review important works on TDDs View full abstract»

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  • Multiple-valued logic minimization by genetic algorithms

    Publication Year: 1997, Page(s):97 - 102
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    This paper describes an approach to minimize multiple-valued logic expressions by genetic algorithms. We encode a multiple-valued logic expression as a “chromosome” whose length allows to change and corresponds to the number of implicants of the expression. Our fitness function evaluates the following three items. 1. How may outputs does the logic expression represent correctly? 2. How... View full abstract»

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  • Sympathy-MV: Fast exact minimization of fixed polarity multi-valued linear expressions

    Publication Year: 1997, Page(s):66 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    In this paper a polynomial time algorithm for the minimization of fixed polarity multi-valued linear expressions (FPMVLs) for totally symmetric functions based on an extension of binary moment diagrams (BMDs) is presented. A generalization to partially symmetric functions is investigated View full abstract»

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  • Multiple-junction surface tunnel transistors for multiple-valued logic circuits

    Publication Year: 1997, Page(s):41 - 46
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    Multiple-junction surface tunnel transistors (MJ-STTs), in which gate-controlled multiple p-/n- tunnel-junctions are connected in series between the source and drain, are proposed for application as multiple-valued logic circuits. The transistor operation with four negative-differential-resistance characteristics is confirmed by fabricating a GaAs-based four-tunnel-junction M... View full abstract»

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  • Multiple-valued immune network model and its simulations

    Publication Year: 1997, Page(s):233 - 238
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    This paper describes a new model of multiple-valued immune network based on biological immune response network. The model of multiple-valued immune network is formulated based on the analogy with the interaction between B cells and T cells in immune system. The model has a property that resembles immune response quite well. The immunity of the network is simulated and makes several experimentally ... View full abstract»

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  • Mixed discrete optimization of multiple-valued systems

    Publication Year: 1997, Page(s):259 - 264
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    In this paper, a cutting-plane method is presented that has been applied to mixed multiple-valued optimization problems. In practice, the approach is faster than transforming mixed multiple-valued programs to mixed integer or zero-one integer programs. The approach can be used for fuzzy sets and industrial applications involving discrete intervals of feasible solutions. It has been applied to indu... View full abstract»

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  • Circuit design from Kronecker Galois field decision diagrams for multiple-valued functions

    Publication Year: 1997, Page(s):275 - 280
    Cited by:  Papers (19)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    In this paper we define the Kronecker Galois field decision diagrams (KGFDDs), a generalization of Kronecker decision diagrams (KDDs) to the representation of multiple-valued (MV) functions. Starting from the multi-place decision diagrams (MDDs) and Galois field decision diagrams (GFDDs) we give a generalization that allows more compact representation with respect to the nodes needed. Based on KGF... View full abstract»

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  • Properties and applications of unified complex Hadamard transforms

    Publication Year: 1997, Page(s):131 - 136
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (580 KB)

    A family of Unified Complex Hadamard Transforms derived from Walsh functions is defined. Newly developed direct matrix operator is introduced which is able to generate different types of Complex Hadamard matrices. Higher dimension matrices of the transforms may also be generated recursively by means of Kronecker product from basic matrices. Sparse matrix factorization or matrix partitioning of the... View full abstract»

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  • What is many-valued logic?

    Publication Year: 1997, Page(s):117 - 121
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    Firstly we examine the definition of many-valued logic within the framework of (logical) matrix theory. Secondly we discuss the general result, challenging the existence of many-valued logic, according to which every logic may be seen as two-valued. Thirdly we analyze the principle of bivalence and show that it appears at a deeper level than one usually thinks View full abstract»

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  • Set-valued functions and regularity

    Publication Year: 1997, Page(s):89 - 94
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB)

    In this paper, we focus on regularity and set-valued functions. The regularity was first introduced by S.C. Kleene (1952) into the propositional connectives of a ternary logic. Then, M. Mukaidono (1986) expanded the regularity of Kleene into n-variable ternary functions, and a ternary function which is regular is called a regular ternary logic function. Some studies expanded regular ternary logic ... View full abstract»

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  • Fast algorithm for minimizing Reed-Muller expansions of systems of incompletely specified MVL functions

    Publication Year: 1997, Page(s):61 - 65
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    A problem of the optimal implementation of multi-valued logic (MVL) functions on the basis of multivalued EXOR gates is considered. In this paper, we are concerned with the question of representing systems of MVL functions by minimum Reed-Muller expansions. A specific class of such representations, called superoptimal, is regarded. For the superoptimal solutions the number of different conjunction... View full abstract»

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  • Application of resonant-tunneling quaternary quantizer to ultrahigh-speed A/D converter

    Publication Year: 1997, Page(s):35 - 40
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    An analog-to-quaternary quantizer using resonant-tunneling (RT) devices is applied to an ultrahigh-speed analog-to-digital (A/D) converter. First, transient analysis results for the quaternary quantizer, which consists of six RT diodes and one HEMT, are presented. A 4-bit A/D converter employing this quantizer with multiple-valued logic encoding circuits is then described. The number of transistor... View full abstract»

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  • Multiple-valued logic as a programming language

    Publication Year: 1997, Page(s):227 - 232
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A method for specifying the computable functions using multiple-valued logics is described. The logics in question provide a uniform environment both for specifying computable functions on the natural numbers and for proving theorems about such specifications. They arise via a generalisation to the countable-valued case of techniques that may be used in specifying multiple-valued switching circuit... View full abstract»

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  • Multiple-valued programmable logic arrays with universal literals

    Publication Year: 1997, Page(s):163 - 168
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (408 KB)

    A universal literal is a single-variable function and has an ability to manipulate more information than a set literal. The array size therefore could be eliminated by using universal literal generators (ULGs for short) in programmable logic arrays (PLAs), compared to PLAs with set literals. This paper discusses what operator is the most suitable in the term of eliminating the array size. We find ... View full abstract»

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  • Design of ternary CCD circuits referencing to current-mode CMOS circuits

    Publication Year: 1997, Page(s):209 - 214
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper investigates the relationship between current-mode and charge-mode circuits. In particular, it shows that four basic CCD logic elements have their counterparts in the current-mode circuits. This is in turn used to show how to apply design principles used for current-mode CMOS circuits to the design of charge-mode CCD circuits View full abstract»

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  • Representation of uncertain belief using interval probability

    Publication Year: 1997, Page(s):111 - 116
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    In this paper, uncertain belief representation by using probability is investigated. The representation equivalence between interval probability suggested by D.D. Phan (1990) and convex set of probability distribution by H. Kyburg (1990) is proved. Probabilistic closures using classical and relevant consequence relations are defined and compared. Their agreement on a non-tautological fragment is p... View full abstract»

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  • Completeness criteria in set-valued logic under compositions with union and intersection

    Publication Year: 1997, Page(s):75 - 82
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    This paper discusses the Boolean completeness problems in r-valued set logic, which is the logic of functions mapping n-tuples of subsets into subsets over r values. Boolean functions are convenient choice as building blocks in the design of set logic circuits. Given a set S of Boolean functions, a set of functions F is S-complete if any set logic function can be composed from F once all Boolean f... View full abstract»

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  • Enzyme transistor circuits for biomolecular computing

    Publication Year: 1997, Page(s):47 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    A model of an enzyme transistor, a three-terminal biomolecular switching device, is proposed. Ideally, an enzyme transistor can be regarded as an artificial enzyme whose catalytic activity is controlled by some effector molecule. In this paper, we show that various biomolecular circuits can be constructed with enzyme transistors. Also, a possible approach to the implementation based on electrical ... View full abstract»

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  • Design of an asynchronous digital system with B-ternary logic

    Publication Year: 1997, Page(s):265 - 271
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    Some of the recent digital systems have a serious clock skew problem which comes from huge hardware implementations and high speed operations in VLSI's. To overcome this problem, clock distribution techniques and more notably, asynchronous system design methodologies, have been investigated. Since, the latest asynchronous digital systems use two-rail logic with two-phase data transfer manner, more... View full abstract»

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  • Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm

    Publication Year: 1997, Page(s):139 - 144
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays View full abstract»

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