Scheduled System Maintenance:
Some services will be unavailable Sunday, March 29th through Monday, March 30th. We apologize for the inconvenience.
By Topic

Electronic Materials and Packaging, 2008. EMAP 2008. International Conference on

Date 22-24 Oct. 2008

Filter Results

Displaying Results 1 - 25 of 91
  • Main Menu

    Publication Year: 2008 , Page(s): i
    Save to Project icon | Request Permissions | PDF file iconPDF (163 KB)  
    Freely Available from IEEE
  • 2008 EMAP Conference

    Publication Year: 2008 , Page(s): ii
    Save to Project icon | Request Permissions | PDF file iconPDF (141 KB)  
    Freely Available from IEEE
  • 2008 EMAP Conference

    Publication Year: 2008 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (581 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2008 , Page(s): 2
    Save to Project icon | Request Permissions | PDF file iconPDF (413 KB)  
    Freely Available from IEEE
  • Welcome message from Shen-Li Fu, conference general chair

    Publication Year: 2008 , Page(s): 3
    Save to Project icon | Request Permissions | PDF file iconPDF (555 KB)  
    Freely Available from IEEE
  • Welcome message from K. N. Chiang, conference co-chair

    Publication Year: 2008 , Page(s): 4
    Save to Project icon | Request Permissions | PDF file iconPDF (574 KB)  
    Freely Available from IEEE
  • Welcome message from Yi-Jen Chan, conference co-chair

    Publication Year: 2008 , Page(s): 5
    Save to Project icon | Request Permissions | PDF file iconPDF (243 KB)  
    Freely Available from IEEE
  • Welcome message from Simon Chen, conference co-chair

    Publication Year: 2008 , Page(s): 6
    Save to Project icon | Request Permissions | PDF file iconPDF (235 KB)  
    Freely Available from IEEE
  • Keynote address

    Publication Year: 2008 , Page(s): 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (218 KB)  

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Index [table of contents]

    Publication Year: 2008 , Page(s): 8 - 19
    Save to Project icon | Request Permissions | PDF file iconPDF (1170 KB)  
    Freely Available from IEEE
  • The effects of the degree of cure of anisotropic conductive films (ACFs) on the contraction stress build-up of ACFs and ACF joints stability for ACF flip-chip interconnection

    Publication Year: 2008 , Page(s): 20 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7243 KB) |  | HTML iconHTML  

    In this paper, the effects of the degree of cure of an Anisotropic Conductive Film (ACF) on the material properties and the contraction stress build-up of the ACF and ACF joints stability were investigated. The degrees of cure of the ACF as a function of bonding times were quantitatively obtained by a dynamic DSC study and an Attenuated Total Reflectance/Fourier transform infrared (ATR/FT-IR) analysis. According to the results, the thickness expansion rate of the ACF as a function of temperature decreased and the storage modulus increased as the degree of cure increased. In addition, the contraction stress of partially cured ACF with the degree of cure below 40% was much smaller than that of fully cured ACF. The ACF contact resistances decreased and the ACF peel adhesion strengths increased as the degree of cure of the ACF increased. In particular, the ACF rebound resulting in poor electrical contact was observed when the degree of cure was below 40%. Furthermore, the ACF joints with the degree of cure below 40% were more unstable than those with the degree of cure over 90% during 85degC and 85% relative humidity test (85degC/85% RH). View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fluorine thermal stability of ZnO:F films investigated by thermal desorption spectroscopy

    Publication Year: 2008 , Page(s): 25 - 28
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1234 KB) |  | HTML iconHTML  

    To estimate the fluorine thermal stability of fluorine doped zinc oxide (ZnO:F) films, ZnO:F films were prepared by co-sputtering zinc oxide(ZnO) and magnesium fluoride (MgF2) targets under different sputtering powers. The prepared films were tested with a thermal desorption system heated from room temperature to 500degC. Four elements: zinc (Zn), oxygen (O), magnesium (Mg) and fluorine (F) from ZnO:F films exhibit clear and similar thermal desorption behavior. The result indicates prepared ZnO:F films will desorb corresponding to low bound strength under 100degC heat treatment, and exhibit multilayer instead of layer by layer desorption behavior based on Polanyi-Wigner model. Fluorine is thermally unstable for ZnO:F films evidenced by thermal desorption test. Electrical and optical properties of ZnO:F films after thermal desorption test become negative. This work contributes to display or solar industry if ZnO:F films are considered to be the transparent conductive oxide films. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New halogen-free laminate for advanced package substrate

    Publication Year: 2008 , Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5425 KB)  

    Nowadays, the demand for the printed wiring board (PWB) of the environment harmony type is rising rapidly. We have developed a new halogen-free material with low coefficients of thermal expansion (CTE), which will be applied to the plastic packages such as FC-BGA and CSP. The original resin system and filler treatment technique named FICS (filler interphase control system) were applied to the material. The newly developed halogen-free material named MCL-E-679FG(S) has a higher glass transition temperature (Tg), peel strength, and heat resistance than the conventional halogen-free materials. Their properties are advantageous to the melting temperature rise of the lead-free solder. Another newly developed halogen-free material named MCL-E-679GT has the lower CTE combined with standard glass fabric (E-glass). It has been developed by new resin system. Its advantage is to reduce of PKG warpage, such as package on package (PoP), during the heat process for the chip mounting. In order to meet fine-line formation, we developed profile-free copper foil. With the copper foil of 18 mum thickness, we have formed the fine line of 60 mum or less pitch by the conventional subtractive method. It will be effective for advanced package substrate such as high density CSP. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Alloying design of Sn-Ag-Cu solders for the improvement in drop test performance

    Publication Year: 2008 , Page(s): 33 - 36
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5036 KB) |  | HTML iconHTML  

    In addition to a reduced Ag content, it has been demonstrated that significant improvement of drop test performance of Sn-Ag-Cu solder joints can be achieved by alloying with Mn and Ti. This study aims to investigate the effects of Mn and Ti additives on the microstructure and solidification behavior of Sn-1.0Ag-0.5Cu alloys, as well as mechanical properties and thus to explain how the alloying elements affect drop test results. Results show that alloying of Mn and Ti results in coarse eutectic structure and greater amount of pro eutectic Sn of which the size was refined. The microstructural changes leads to a reduction in elastic modulus, which plays an important role for the enhancement of drop impact reliability. However, there exists an optimal value for the alloying content, since excess addition of Mn or Ti gives rise to the formation of massive intermetallic compounds (IMCs), MnSn2 and Ti2Sn3. Those heterogeneous IMCs are harder than the inherent IMCs, Ag3Sn and Cu6Sn5, according to the nanoindentation results and may cause the degradation in drop performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interfacial behavior between copper foil and tin upon thermal aging

    Publication Year: 2008 , Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8736 KB)  

    This study investigated the thermal effect on the interfacial IMC (Cu3Sn and Cu6Sn5) formation at the interface between pure tin and a copper substrate at 125degC. During thermal aging, the morphology of Cu6Sn5 transformed from a scallop to a layer shape. The thickness of IMCs (Cu3Sn, Cu6Sn5) changed with an increase in aging time. It was observed that scallop Cu6Sn5 decomposed during heat aging for up to 420 hours; in contrast, upper Cu3Sn grew rapidly. Between 420 hours and 2693 hours, both Cu3Sn and Cu6Sn5 increased with increasing aging time. However, between 2693 hours and 2854 hours of thermal aging, the shrinkage of Cu3Sn and the growth of Cu6Sn5 were induced as a result of the segregation of voids formed at the Cu3Sn/Cu interface. On a free surface, Cu6Sn5 and Cu3Sn tended to grow in the X-Y and Z planes, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fatigue strength of electroplated copper thin films under uni-axial stress

    Publication Year: 2008 , Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4154 KB) |  | HTML iconHTML  

    Fatigue strength of electroplated copper thin films was measured under uni-axial stress. Two kinds of electroplated films were prepared for the fatigue test. One was a commercial film mainly used for interconnections in printed wiring boards. The other film was grown on a stainless steel substrate by using acid copper sulfate bath without any additive agent. The micro texture of each film was observed by using SEM (Scanning Electro Microscope) and SIM (Scanning Ion Microscope). It was found that the micro texture of each film was quite different with each other. The mechanical properties such as the yield stress, fracture elongation and Young's modulus of each film changed significantly from those of bulk copper depending on their micro structure. The low-cycle fatigue strength also varied drastically with each other, while the high-cycle fatigue strength was almost same. The fracture surfaces were observed by SEM after the fatigue test. It was found that there were two fracture modes under the fatigue test. One was a typical ductile fracture, and another was brittle one even under the fatigue load higher than its yield stress. The crack seemed to propagate through the grains when the ductile fracture occurred. On the other, the crack seemed to propagate along grain boundaries of columnar grains when the brittle fracture occurred. These results clearly indicated that the fatigue strength of electroplated copper thin films varies depending on their micro structure. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recent progress in copper-based wafer bonding for 3-D ICs application

    Publication Year: 2008 , Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1538 KB) |  | HTML iconHTML  

    This article discusses thermo-compression bonding (also known as diffusion bonding) of metallic copper and its application in 3-D stacking of ICs. Bonding process is described and characterization results are presented. A survey on recent progress of copper-based wafer bonding, particularly low temperature process, and its application for on wafer 3-D ICs are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Flexible opto-electrical interconnect module for consumer electronic application

    Publication Year: 2008 , Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5771 KB) |  | HTML iconHTML  

    In this paper, we performed a 4 Ch times 2.5 Gbps flexible opto-electrical interconnect module integrated with two silicon optical benchs (SiOBs), four fibers and one rigid-flexible PCB, which provided with capability of optical and electrical data transmission simultaneously. The high-speed data transmission interconnects through fiber, and the electrical transmission interconnects through the circuit of flexible PCB. The SiOB is used for optical coupling between optoelectronics and waveguide, and optical coupling from VCSEL sources to the lightwave circuit is accomplished by 45deg end-mirrors is formed using silicon etching and fibers. A similar optical coupling arrangement is used for the PD array. In this architecture, the assembly tolerances of system are larger than 10 mum. The eye diagram of the electrical output signal from the receiver is tested compliant with SONET OC-48 eye mask. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parameter extractions and a new calibration methodology for MOSFET sensors

    Publication Year: 2008 , Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2479 KB) |  | HTML iconHTML  

    In this work, we studied the availability of p-type MOSFET with 1 mum channel width and 0.15 mum channel length as a stress sensor. Under mechanical, thermal, and thermo-mechanical coupling effects, parameters of the MOSFET devices were extracted based on a new measurement methodology, and linear relationships between drain current variation and stress and/or thermal effects were obtained. According to the measurement data, the extremely important thermal effect was also noted. It is concluded in this work that the newly experimental design and the extracted parameters are useful for MOSFET stress sensor's design and applications. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-temperature fabrication method of carbon nanotubes-based gas sensor

    Publication Year: 2008 , Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7646 KB) |  | HTML iconHTML  

    Low temperature processes are the better ways to integrate carbon nanotubes (CNTs) with CMOS chips into array-type gas sensors. Almost the metal used in CMOS is Al-Si-Cu alloy, which make the sustainable temperature of CMOS structures be in the range of 400- 500degC. We offer a new fabrication method of CNTs-based gas sensors at low temperature. The oxidized silicon substrate was modified with 3-aminopropyltriethoxysilane (APTS) to form aminoterminated (-NH2) self-assembled monolayer (SAM) on the surface. The chemical adhesion of CNTs to surface treated is due to the presence of positive charges or amine groups on the surface. After CNTs adhered to SiO2 surface, we deposited interdigitated electrode (IDE) on the SiO2 surface. We experimentally found that the resistances of CNT electronic devices at room temperature typically ranged from several hundreds Omega to several of kOmega, depending on the density of the MWCNTs across the IDE fingers. An array-type CNTs-based gas sensor was made up of many CNTs-based gas sensors. The initial resistance values of these sensors were not the same; therefore we tuned the resistance value of gas sensor equally by trimming. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low cost through silicon via solution suitable compatible with existing assembly infrastructure and suitable for single die and die stacked packages

    Publication Year: 2008 , Page(s): 61 - 64
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1154 KB) |  | HTML iconHTML  

    In portable electronics products, where area is at a premium, there has been a move to three dimensional solutions, achieved by either package stacking or die stacking. Package stacking allows the parts to be tested before stacking to maintain high compound yields, but is volume and cost inefficient because each die has its own enclosure. Die stacking using wire bond interconnects is low cost, but is still volume inefficient because die must be either offset or spacer layers included to allow access to the bond pads. Die stacking using wire bonds is also incompatible with high-volume manufacture because of the serial nature of the stacking and interconnect processes. Die stacking using through silicon vias potentially offers the thinnest product solution. Despite many years of endeavour TSVs have failed to achieve widespread commercial acceptance. There are several reasons for this notable amongst which is the high capital cost of the equipment required, the slow etch rate of silicon, which curtails throughput, and the complexity of the additional process steps to fabricate conductive pipes that are insulated from the silicon through which they pass. There are also issues of reliability that have not yet been satisfactorily solved. Points of weaknesses in the design include dielectric and conductive coating of the side walls of a high aspect ratio pipe; the 90 degree bends at the top and base of the pipe that the redistribution layer must traverse and maintain connectivity during thermal cycling; and the difficulty of cleaning the back of the bond pad so the redistribution layer can make an Ohmic contact to it, when the bond pad is the bottom of a long narrow pipe. This paper will present a new through silicon via solution suitable for both single die and stacked die wafer-level packages. So-called dasiavia-through-padpsila interconnects are a novel form of interconnect that superficially resemble a TSV but the differences are important and have profound implication- - s for the product cost and reliability. Unusually, the materials of the package construction are sourced from the automotive industry. This is done to keep costs as low as possible. The process technology is wholly scaleable so the same tool set can be used irrespective of the silicon wafer diameter. The via-through-pad interconnects and stacked package are fabricated at the wafer level to leverage the cost and throughput advantage of wafer-scale processing. Because only tested die are incorporated in the structure, high-compound yield can be realised. Data will be presented showing via-through-pad interconnects are able to surpass by a wide margin, the exacting reliability requirements of the automotive industry, both at the package and board level. Examples of application based on image sensors and muSD cards containing stacks of flash memory will be presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optical density measurement of TFT-LCD by PMT coupled monochrome LED

    Publication Year: 2008 , Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3909 KB) |  | HTML iconHTML  

    A fast and innovative method using a monochromatic red LED to measure the optical density of black matrix is developed in this study. The results show that the 3-Watt monochromatic red LED performs better than that of the currently used 100-Watt halogen lamp by reducing the pumping speed by 40% and the 3-sigma standard deviation of the test samples is also superior by 40%. The measurement difference for average OD values is within 1% between both light sources. In addition, using standard glass, the monochromatic red LED demonstrates accuracy within 1.58%. Therefore, the monochromatic red LED can substitute the halogen lamp currently used the TFT-LCD industry to measure the optical density of BM layer. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unique dry film solution for Through Silicon Via Process

    Publication Year: 2008 , Page(s): 69 - 71
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2401 KB) |  | HTML iconHTML  

    ldquoThrough Silicon Via (TSV) technology has gained a lot of attention lately as a packaging solution meeting the needs for higher device performance and lower cost of ownership. The semiconductor and packaging industry is looking for new technology and alternative materials to meet the goal of true 3D integration. One of the major challenges in implementing 3D packaging is the formation of high aspect ratio interconnects with sufficient via density and uniformity using an efficient process that results in low cost of ownership. This paper demonstrates a novel cost effective dry film photoresist process meeting the technology requirements in terms of via diameter, shape and geometry using resist formulations with high etch selectivity and plating performance for via filling. Further results are presented showing advantages of this photoresist process for TSV ldquovia protectionrdquo using the unique tenting capability of dry film.rdquo View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The contact stress analysis of the ferrule-hub assembly used in the photonic device packaging

    Publication Year: 2008 , Page(s): 72 - 75
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2332 KB) |  | HTML iconHTML  

    Fiber-to-the-premise architectures, by their nature, require numerous fiber connections for distribution of services to multiple home and business locations. The higher performance of angle-polished connection (APCs) in the outside plant (OSP) environment has widely used in FTTP network. The APC ferrule-hub assembly is an essential part in the device components, such as connectors and transceivers in the optical network. The defect modes in such ferrule-hub include epoxy leakage, contact surface crack, ferrule drop out, which result in device failure and optical signal disconnection. In this study, we first investigated on ferrule stress distribution which caused by the hub design and interference tolerance. The commercial available MSC.Marc program was used in this contact stress analysis. We further demonstrate that fixture and hub designs, apply force velocity and ferrule geometric imperfection can greatly alter the contact stress in the ferrule tip. Such optimal parameters were integrated into our automatic machine to show the good agreement between theoretical study and experimental work. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minor Fe, Co, and Ni additions to SnAgCu solders for retarding Cu3Sn growth

    Publication Year: 2008 , Page(s): 76 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4022 KB) |  | HTML iconHTML  

    The solders used for this study are Sn2.5Ag0.8Cu doped with 0.03 wt.% Fe, Co, or Ni and 0, 0.005, 0.01, 0.06, or 0.1 wt.% Ni. Reaction conditions included multiple reflows for up to 10 times and solid-state aging at 160degC for up to 2000 hrs. In multiple reflow study, Cu6Sn5 was the only reaction product observed for all the different solders used. Reflows using the solder without doping produced a thin, dense layer of Cu6Sn5. The additions of Fe, Co, or Ni transformed this microstructure into a much thicker Cu6Sn5 with many small trapped solder regions between the Cu6Sn5 grains. In solid state aging study, both Cu6Sn5 and Cu3Sn formed, but the additions of Fe, Co, or Ni produced a much thinner Cu3Sn layer. Specifically, Ni concentration higher than 0.01 wt.% could effectively retard the Cu3Sn growth even after 2000 hrs of aging, and accordingly 0.01 wt.% can be considered the minimum effective Ni addition. Because the Cu3Sn growth had been linked to the formation of micro voids, which in turn increased the potential for a brittle interfacial fracture, thinner Cu3Sn layers might translate into better solder joint strength. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.