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Systolic Arrays, 1988., Proceedings of the International Conference on

Date 25-27 May 1988

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Displaying Results 1 - 25 of 67
  • Proceedings of the International Conference on Systolic Arrays (Cat. No.88CH2603-9)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • An efficient systolic array for MVDR beamforming

    Publication Year: 1988, Page(s):11 - 20
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    An efficient systolic array for computing the minimum variance distortionless response (MVDR) from an adaptive antennas array is described. The MVDR beamforming problem amounts to minimizing, in a least-squares sense, the combined output from an antenna array subject of K independent linear equality constraints each of which corresponds to a chosen 'look direction'. The array is fully pipelined an... View full abstract»

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  • Implementation of synthetic aperture radar algorithms on a systolic/cellular architecture

    Publication Year: 1988, Page(s):21 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Two sequences of operations necessary for implementation of high-resolution image formation in strip and spotlight modes of the synthetic-aperture radar (SAR) are presented. The sequences are mapped onto a systolic/cellular architecture. The mapping includes parallel implementation of all the basic operations and the pertinent data communication. Detailed estimates of the computation times are pro... View full abstract»

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  • Synthesizing optimal family of linear systolic arrays for matrix computations

    Publication Year: 1988, Page(s):51 - 60
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (383 KB)

    A method is proposed for designing a family of linear systolic arrays for matrix-oriented problems for which two-dimensional arrays have been designed. The design exhibits a tradeoff between local storage, s, and number of processing elements, n. The arrays are linear, with each processor having storage O(s),1 View full abstract»

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  • Theory for systolizing global computational problems

    Publication Year: 1988, Page(s):61 - 71
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A theory is presented for rasterizing a class of two-dimensional problems including signal/image processing, computer vision, and linear algebra. The rasterization theory is steered by an isomorphic relationship between the multidimensional shuffle-exchange network (mDSE) and the multidimensional butterfly network (mDBN). Many important multidimensional signal-processing problems can be solved on ... View full abstract»

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  • New architectures for systolic hashing

    Publication Year: 1988, Page(s):73 - 82
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    Two- and three-dimensional systolic architectures are proposed for the hash table data structure (hashing). The parallel systolic hashing architecture provides the facility for implementing the hash operations of Insert, Delete, and Member in a constant time complexity. The importance and advantages of extending sequential hashing to a parallelized form are discussed. An implementation is presente... View full abstract»

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  • Linear systolic array for least-squares estimation

    Publication Year: 1988, Page(s):83 - 92
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB)

    The use of square-root-free linear systolic array structure to perform the QR decomposition needed in the solution of least-squares (LS) problems is proposed. A form of the Kalman filter algorithm is applied to perform the recursive LS estimation. Compared with the conventional triangular systolic array structure for LS estimation, the linear array has the advantage of requiring less area and bein... View full abstract»

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  • A cellular algorithm for straight line extraction

    Publication Year: 1988, Page(s):93 - 102
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Straight-line-edge extraction can be carried out in two successive phases: identifying the pixels that belong to edges and conducting straight-line segments from these edge pixels. A parallel approach based on a cellular algorithm is proposed for the second phase. Each cell sends a message that compiles distances between a pattern segment and the real segment on the image. The value of the message... View full abstract»

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  • A one dimensional systolic array for solving arbitrarily large least mean square problems

    Publication Year: 1988, Page(s):103 - 112
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (461 KB)

    The design is presented of a one-dimensional systolic array for solving arbitrarily large least-mean-square problems involving QR decomposition and a triangular system of equations. The main characteristics of this array are maximization of array utilization, thus achieving a minimum global computation time, and low complexity of the resulting array, which can also be used in problems such as matr... View full abstract»

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  • Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks

    Publication Year: 1988, Page(s):113 - 124
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The performance of the various parts of the HERMES multiprocessor vision system is evaluated. HERMES is an autonomous, hierarchical, heterogenic vision processing system, consisting of N/sup 2//4/sup i/, 0 View full abstract»

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  • On partitioning the Faddeev algorithm

    Publication Year: 1988, Page(s):125 - 134
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB)

    Partitioned schemes for computing the Faddeev algorithm are derived, using a graph-based methodology. Such implementations are obtained by performing transformations on the fully parallel dependence graph of the algorithm. Linear and two-dimensional structures are derived and evaluated in terms of throughput, I/O bandwidth, utilization of processing elements, and overhead due to partitioning. The ... View full abstract»

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  • A systolic architecture for the symmetric tridiagonal eigenvalue problem

    Publication Year: 1988, Page(s):145 - 150
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    The first step in the development of a chip set to support eigenvalue-eigenvector-based estimation algorithms is presented. It is based on the assumption that an averaging technique will produce a symmetric covariance matrix. Such a matrix can be reduced to a symmetric tridiagonal matrix, and hence the eigenvalues and eigenvectors can be found by successive iterations involving QR decomposition. T... View full abstract»

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  • Stereo matching of satellite images with transputers

    Publication Year: 1988, Page(s):175 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (355 KB)

    A demanding problem involving several algorithmic phases with varying degrees of regularity and data dependence is used to show that a network of transputers programmed in OCCAM has all the attributes needed to explore several processing paradigms. Two alternative organizations of the problem on a network of 21 transputers are compared from the standpoints of speed, hardware efficiency, and ease o... View full abstract»

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  • A million transistor systolic array graphics engine

    Publication Year: 1988, Page(s):193 - 202
    Cited by:  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (621 KB)

    A description is given of a million transistor systolic array graphics engine (SAGE) that can render a horizontal 3-D span in every clock cycle at the rate of 25 million spans/s, independent of the pixel length of the span. For the average span length in the 10-32 pixel range, this translates into 250-800 million pixels/s. Assuming that the front end of the system can generate a span in every cloc... View full abstract»

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  • A massively parallel systolic array processor system

    Publication Year: 1988, Page(s):217 - 225
    Cited by:  Papers (2)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    The design of a massively parallel processor, comprised of 2304-bit-serial processor elements arranged in a 48 by 48 systolic array, is described. The system consists of the processor array, a microstore controller, and a host computer interface. Program development tools are available on the host computer. The processor array uses 32 NCR GAPP (Geometric Arithmetic Parallel Processor) microprocess... View full abstract»

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  • Implementation of array structured maximum likelihood decoders

    Publication Year: 1988, Page(s):227 - 236
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Efficient VLSI array processor architectures for maximum-likelihood decoding (MLD) have been developed to meet the high throughput and data processing requirements of modern communication systems. Both 1-D and 2-D MLD processors with large constraint length (>8) have been derived. Radix-4p processing elements and delay commutating switching processors for MLD have been concatenated to construct a ... View full abstract»

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  • Regular processor arrays for matrix algorithms with pivoting

    Publication Year: 1988, Page(s):237 - 246
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB)

    It is shown how to obtain regular (though nonsystolic) processor arrays for algorithms with pivoting. First, the fact that pivoting algorithms cannot be systolic is established. Then it is shown how regular iterative algorithms can be formulated for the Gaussian elimination algorithm with partial pivoting and how the algorithm can then be implemented on the so-called regular iterative arrays (loca... View full abstract»

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  • Systolic algorithms for some scheduling and graph problems

    Publication Year: 1988, Page(s):247 - 256
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A simple model of a linear systolic array with serial input/output and one-way data communication is considered. It is shown that such an array can be used to solve some scheduling and graph problems efficiently. The systolic algorithms are developed in two stages. First an algorithm on a restricted type of sequential machine is constructed. Then the sequential machine algorithm is transformed int... View full abstract»

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  • The design of a systolic array system for linear state equations

    Publication Year: 1988, Page(s):275 - 284
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB)

    The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-schedulin... View full abstract»

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  • Mapping strategy for automatic design of systolic arrays

    Publication Year: 1988, Page(s):285 - 294
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB)

    A mapping strategy for automatic design of systolic arrays is presented. Algorithms are specified in terms of data dependency and identity, and implementations are specified in terms of data propagation and sequence behavior. By establishing a relation between data propagation and sequence, an optimal mapping strategy is formulated as a problem of finding an integer solution of a set of linear equ... View full abstract»

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  • The derivation of regular synchronous circuits

    Publication Year: 1988, Page(s):305 - 314
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (405 KB)

    An approach to derive parameterized representations of regular synchronous circuits from their specification is presented. The derivation of designs consists of two steps: rewriting the specification in terms of predefined structures to obtain a draft architecture, and optimizing that architecture by successive correctness-preserving transformations using algebraic theorems. These steps can be rep... View full abstract»

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  • Systolic arrays for group explicit methods for solving parabolic partial differential equations

    Publication Year: 1988, Page(s):315 - 329
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (369 KB)

    A systolic array implementation for solving parabolic equations numerically is presented. The finite-difference methods used are stable asymmetric approximations to the partial differential equations, which when coupled in groups of two adjacent points on the grid result in implicit equations that are easily converted to explicit form, thus offering many advantages suitable for solution by VLSI te... View full abstract»

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  • Parallel algorithms and systolic array designs for RSA cryptosystem

    Publication Year: 1988, Page(s):341 - 350
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    Two algorithms for computing very large integer modular exponentiation are proposed. One is based on a recording technique that significantly reduces the total number of modular multiplications. The second is parallel algorithm that can be implemented by two parallel processors and achieves optimal performance. Two corresponding systolic array designs are developed. The main advantage of these sys... View full abstract»

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  • A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix

    Publication Year: 1988, Page(s):361 - 371
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB)

    A parallel block-iterative algorithm for solving sets of linear equations with a positive multiband coefficient matrix is presented. The parallel structure is obtained by decoupling the sets of equations into subsets instead of partitioning the coefficient matrix into a lower and upper (block) triangular matrix. An important feature of the algorithm is that the coefficient matrices of the decouple... View full abstract»

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  • Scheduling a system of affine recurrence equations onto a systolic array

    Publication Year: 1988, Page(s):373 - 382
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB)

    Most work on the problem of scheduling computations on a systolic array is restricted to systems of uniform recurrence equations. This restriction is relaxed to include systems of affine recurrence equations. In this broader class, a sufficient condition is given for the system to be computable. Necessary and sufficient conditions are given for the existence of an affine schedule, along with a pro... View full abstract»

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