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Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

28-31 Jan. 1997

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  • Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

    Publication Year: 1997
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    Freely Available from IEEE
  • Collaboration between university and industry

    Publication Year: 1997, Page(s): 433
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (30 KB)

    Summary form only given, as follows. Rapid growth in semiconductor technology has greatly changed the situation of research and development between companies from one of competition to collaboration. With so much cooperation between enterprises, what role, if any, should universities play? What do companies expect of universities? How and what do universities contribute to society ? In this sessio... View full abstract»

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  • Not necessarily more switches more routability [sic.]

    Publication Year: 1997, Page(s):579 - 584
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (725 KB)

    It has been observed experimentally that the mapping of global to detailed routing in a conventional FPGA routing architecture (2D array) yields unpredictable results. A different class of FPGA structures called greedy routing architectures (GRAs), where a locally optimal switch box routing can be extended to an optimal entire-chip routing, were investigated by Wu et al. (1994), Takashima et al. (... View full abstract»

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  • Conference Author Index

    Publication Year: 1997, Page(s):687 - 690
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    Freely Available from IEEE
  • An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits

    Publication Year: 1997, Page(s):107 - 112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper presents an enhanced iterative improvement method with multiple pins (EIIMP) to evaluate the maximum number of simultaneous switching gates. Although the iterative improvement method is a simple algorithm, it is powerful to this purpose. Keeping this advantage, we enhance it by two points. The first one is to change values for multiple successive primary inputs at a time. The second one... View full abstract»

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  • An entropy measure for power estimation of Boolean functions

    Publication Year: 1997, Page(s):101 - 106
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    In this paper, we present a study on the relationship between entropy and the average power consumption, of circuits generated from Boolean functions. Based on a general-delay model, an entropy-based formulation for power estimation is derived from a large set of experimental data. The study shows that the entropy measure provides an effective power estimate for single-output and fully-correlated ... View full abstract»

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  • Statistical estimation of combinational and sequential CMOS digital circuit activity considering uncertainty of gate delays

    Publication Year: 1997, Page(s):95 - 100
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    While estimating glitches or spurious transitions is challenging due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational and sequential CMOS logic circuits considering uncertainty of gate delays. The methodology is base... View full abstract»

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  • Structural approach for performance driven ECC circuit synthesis

    Publication Year: 1997, Page(s):89 - 94
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    ECCGen is a logic synthesizer for error control coding circuits. It takes H matrices as inputs and produces circuit schematics in two steps, literal minimization, and gate/pin assignment. Different from conventional logic synthesis tools, it takes a structural approach to avoid the combinatorial explosion problem in Boolean function and/or true table representations of ECC circuits. Moreover, the ... View full abstract»

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  • An efficient hierarchical clustering method for the multiple constant multiplication problem

    Publication Year: 1997, Page(s):83 - 88
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    In this paper, we propose an efficient solution for the Multiple Constant Multiplication (MCM) problem. The method exploits common subexpressions among constants based on hierarchical clustering and reduce the number of shifts, additions, and subtractions. The algorithm defines appropriate weights which indicate the operation priorities and selects the common subexpressions which results in the le... View full abstract»

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  • Hardware-software co-design: Tools for architecting systems-on-a-chip

    Publication Year: 1997, Page(s):285 - 289
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper examines the issues and progress in the design of highly integrated microelectronic systems. These microsystems rely on an array of diverse components such as processors, memory, network interfaces, graphics and DSP `cores'. In particular, we discuss problems in the combined design of hardware and software for these systems. We present a decomposition of the co-design problem, and ident... View full abstract»

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  • A high performance FIR filter dedicated to digital video transmission

    Publication Year: 1997, Page(s):77 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. Even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of... View full abstract»

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  • AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks

    Publication Year: 1997, Page(s):529 - 538
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtrackin... View full abstract»

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  • VEAP: Global optimization based efficient algorithm for VLSI placement

    Publication Year: 1997, Page(s):277 - 280
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    In this paper we present a very simple, efficient while effective placement algorithm for Row-based VLSIs. This algorithm is based on strict mathematical analysis, and provably can find the global optima. From our experiments, this algorithm is one of the fastest algorithms, especially for very large scale circuits. Another point desired to point out is that our algorithm can be run in both wirele... View full abstract»

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  • Power consumption in CMOS combinational logic blocks at high frequencies

    Publication Year: 1997, Page(s):195 - 200
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    A new model for estimating dynamic power dissipation in CMOS combinational circuits at differing voltages is presented. The proposed model deals with power dissipation of circuits at saturation frequencies, where the output voltage does not reach 100% of the supply voltage and the output voltage waveform is almost a triangular waveform. We show that the dynamic power consumption at saturation freq... View full abstract»

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  • A programmable application-specific VLSI architecture and implementation for speech word-recognizer

    Publication Year: 1997, Page(s):71 - 75
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    In this paper, the efficient and flexible VLSI architecture and implementation for the voice word-recognizer processor are presented. In order to achieve a flexible and efficient VLSI realization, we use a programmable with specific core design strategy which incorporates the best aspects of both programmable and application specific signal processors to achieve high speed, high accuracy and effic... View full abstract»

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  • Statistical design of macro-models for RT-level power evaluation

    Publication Year: 1997, Page(s):523 - 528
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (632 KB)

    This paper introduces the notion of cycle-accurate macro-models for RT-level power evaluation. These macro-models provide us with the capability to estimate the circuit power dissipation cycle by cycle at RT-level without the need to invoke low level simulations. The statistical framework allows us to compute the error interval for the predicted value from the user specified confidence level. The ... View full abstract»

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  • An improved objective for cell placement

    Publication Year: 1997, Page(s):281 - 284
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    To estimate the wiring area needed by the router to connect a signal net, most placement tools measure one half of the perimeter of the minimum rectangle enclosing all terminals of the net. In the past, this approach is reasonable because the half-perimeter value correlates well with the wiring area. As we are entering the deep-submicron era, the approach is no longer appropriate because the wirin... View full abstract»

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  • Super low power 8-bit CPU with pass-transistor logic

    Publication Year: 1997, Page(s):663 - 664
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    A very low power 8-bit CPU core has been designed based on an original pass-transistor logic family, the SPL (single-rail pass-transistor logic) and SPHL (single-rail pass-transistor and holders logic). The instruction set and external timings are compatible with the Zilog Z80. The average supply current is 740 μA at 3 V with a 10 MHz-clock, equivalent to 26% of that of the commercial CMOS Z80 ... View full abstract»

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  • Efficient routability checking for global wires in planar layouts

    Publication Year: 1997, Page(s):641 - 644
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for the efficient routability checking View full abstract»

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  • Bit-serial pipeline synthesis and layout for large-scale configurable systems

    Publication Year: 1997, Page(s):441 - 446
    Cited by:  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner View full abstract»

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  • Evaluating cost-performance tradeoffs for system level applications

    Publication Year: 1997, Page(s):233 - 238
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    Evaluation of design cost and performance is indispensable to system partitioning. In the absence of a system-level estimation and analysis tool, system partitioning is difficult to perform in an efficient and accurate manner because design evaluation can only be done after the final results are achieved. Furthermore, without cost-performance tradeoff information relating to different design alter... View full abstract»

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  • Computing brokerage and its application in VLSI design

    Publication Year: 1997, Page(s):65 - 69
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    With Internet access available to virtually every one in this community it is interesting to investigate on how Internet will affect the future of VLSI design and CAD. We will describe an experimental WWW-based computing broker. Theoretically, the broker is capable of providing every user with access to any hardware platforms and any software over the Internet. It makes possible pay-per-use of bot... View full abstract»

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  • RT level power analysis

    Publication Year: 1997, Page(s):517 - 522
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    Elevating power estimation to architectural and behavioral level is essential for design exploration beyond logic level. In contrast with purely statistical approach, an analytical model is presented to estimate the power consumption in datapath and controller for a given RT level design. Experimental result shows that order of magnitude speed-up over low level tools as well as satisfactory accura... View full abstract»

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  • Block-level fault isolation using partition theory and logic minimization techniques

    Publication Year: 1997, Page(s):319 - 324
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (572 KB)

    Multichip modules are emerging as a key packaging technology for mixed-signal circuits and systems. In this paper, we consider how to localize a failure within a chip boundary as rapidly as possible in order to expedite the rework process and to minimize its overall impact on manufacturing throughput and cycle time. A key contribution of this paper is to provide a unified block-level fault isolati... View full abstract»

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  • Self-timed 1-D ICT processor

    Publication Year: 1997, Page(s):669 - 670
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    This paper describes a LSI implementation of 1-D order-8 integer cosine transform (ICT) which can calculate either forward or reverse transformation. It is a standard-cell based design using 0.7 μm CMOS SLP DLM process. The chip's performance is maximized with the fast computation algorithm and self-timed circuit technique. It consists of eight parallel self-timed pipelines. Each self-timed blo... View full abstract»

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