Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific

28-31 Jan. 1997

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  • Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

    Publication Year: 1997
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    Freely Available from IEEE
  • Collaboration between university and industry

    Publication Year: 1997, Page(s): 433
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (30 KB)

    Summary form only given, as follows. Rapid growth in semiconductor technology has greatly changed the situation of research and development between companies from one of competition to collaboration. With so much cooperation between enterprises, what role, if any, should universities play? What do companies expect of universities? How and what do universities contribute to society ? In this sessio... View full abstract»

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  • Not necessarily more switches more routability [sic.]

    Publication Year: 1997, Page(s):579 - 584
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (725 KB)

    It has been observed experimentally that the mapping of global to detailed routing in a conventional FPGA routing architecture (2D array) yields unpredictable results. A different class of FPGA structures called greedy routing architectures (GRAs), where a locally optimal switch box routing can be extended to an optimal entire-chip routing, were investigated by Wu et al. (1994), Takashima et al. (... View full abstract»

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  • Conference Author Index

    Publication Year: 1997, Page(s):687 - 690
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    Freely Available from IEEE
  • Choosing a digital simulator

    Publication Year: 1997, Page(s):371 - 376
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    This paper summarises the second in a series of benchmarking efforts conducted by DA Solutions between August 1995 and April 1996, for VHDL and Verilog simulators. The paper discusses the methodology used and the results of an independent public benchmark for leading VHDL and Verilog simulators, for RTL, Gate, VITAL and Co-simulations products. The paper also makes performance comparisons between ... View full abstract»

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  • VLSI Design and Education Center (VDEC) current status and future plan

    Publication Year: 1997, Page(s):365 - 369
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    VDEC (VLSI Design and Education Center) is an inter-university center placed in the University of Tokyo, which has a mission to continuously promote and support VLSI education programs in Japanese universities, including the nationals and the privates. After briefly reviewing a history of VDEC, its functions and facilities are summarized, followed by future plans of chip implementation along with ... View full abstract»

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  • Multi-project chip service for university and industry in Taiwan

    Publication Year: 1997, Page(s):359 - 363
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    Acting as the bridge between the designers and manufacturing companies, the Chip Implementation Center (CIC), founded in 1992 under the National Science Council, aims at the services for the fabrication of multi-project chips, the procurement/integration of software CAD tools, and the promotion of IC design/testing/CAD software technology. To date, 2000 academic licenses of software CAD tools have... View full abstract»

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  • Multi-project chip activities in Korea-IDEC perspective

    Publication Year: 1997, Page(s):353 - 357
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    This paper describes the current status of multi-project chip (MPC) services in Korea to promote full-custom and semi-custom IC design activities in universities. Although MPC foundry services for IC designs were started in a lesser scale more than 10 years ago, it is only recently that systematic and effective education has developed. The MPC foundry services program called IDEC (IC design educat... View full abstract»

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  • The EUROPRACTICE MPC service

    Publication Year: 1997, Page(s):349 - 351
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    IMEC has been involved in MPC services for universities and industry since 1984. In the beginning these services were set up to support the local educational programme. Later on in 1989, IMEC was coordinator of the European wide MPC services in the EC funded project EUROCHIP. Today since October 1995, IMEC has been coordinator of the IC Manufacturing Service in the EC funded project EUROPRACTICE. ... View full abstract»

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  • Delay estimation for technology independent synthesis

    Publication Year: 1997, Page(s):31 - 36
    Cited by:  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper proposes path mapping, a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using the common ideas of tree covering technology mapping. First, path mapping performs technology mapping for all paths in the circuit with minimum delay. Then, it finds the most critical path among all the paths in the circuit... View full abstract»

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  • An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits

    Publication Year: 1997, Page(s):107 - 112
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    This paper presents an enhanced iterative improvement method with multiple pins (EIIMP) to evaluate the maximum number of simultaneous switching gates. Although the iterative improvement method is a simple algorithm, it is powerful to this purpose. Keeping this advantage, we enhance it by two points. The first one is to change values for multiple successive primary inputs at a time. The second one... View full abstract»

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  • Fuzzy-based circuit partitioning in built-in current testing

    Publication Year: 1997, Page(s):397 - 400
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Partitioning a digital circuit into modules before implementing it on a single chip is key to balancing between the test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistical analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible, since IDDQ testing requires the measurement of an anal... View full abstract»

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  • Fault coverage improvement based on error signal analysis

    Publication Year: 1997, Page(s):409 - 412
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Fault-tolerant design of analog circuits is more difficult than that of digital circuits. Chatterjee (1993) has proposed a continuous checksum-based technique to design fault-tolerant linear analog circuits. However, some faults in the passive elements cannot be detected if the checker has not been designed appropriately. This paper addresses the fault coverage issue in the continuous checksum bas... View full abstract»

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  • Delay estimation and optimization of logic circuits: a survey

    Publication Year: 1997, Page(s):25 - 30
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Logic synthesis has two stages of optimization: technology-independent and technology-dependent. This paper surveys state-of-the-art methods for estimation and optimization of delays of logic circuits at the technology-independent stage. Although at this stage we cannot completely predict final delays after technology mapping, there exist reasonably accurate estimation techniques. Final delays can... View full abstract»

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  • Simulation of gate switching characteristics of a miniaturized MOSFET based on a non-isothermal non-equilibrium transport model

    Publication Year: 1997, Page(s):345 - 348
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Our device simulator is developed for the analysis of a MOSFET based on a thermally coupled energy transport model (TCETM). The simulator has the ability to calculate not only steady-state characteristics but also transient characteristics of a MOSFET. It solves basic semiconductor device equations including the Poisson equation, current continuity equations for electrons and holes, energy balance... View full abstract»

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  • A testability analysis method for register-transfer level descriptions

    Publication Year: 1997, Page(s):307 - 312
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    In this paper, we propose a new testability analysis method for Register-Transfer Level (RTL) descriptions. The proposed method is based on the idea of testability analysis in terms of data-flow and control structure which can be extracted from RTL designs. We analyze testability of RTL descriptions with more testability measures than those of conventional gate-level testability, so that the metho... View full abstract»

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  • An entropy measure for power estimation of Boolean functions

    Publication Year: 1997, Page(s):101 - 106
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (540 KB)

    In this paper, we present a study on the relationship between entropy and the average power consumption, of circuits generated from Boolean functions. Based on a general-delay model, an entropy-based formulation for power estimation is derived from a large set of experimental data. The study shows that the entropy measure provides an effective power estimate for single-output and fully-correlated ... View full abstract»

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  • ±1.5 V CMOS four-quadrant multiplier

    Publication Year: 1997, Page(s):429 - 432
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified bi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of ±1.5 V. For a differential input voltage range up to ±0.8 V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB ba... View full abstract»

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  • Modeling and detection of dynamic errors due to reflection- and crosstalk-noise

    Publication Year: 1997, Page(s):405 - 408
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    A new algorithm for the generation of test sequences to detect dynamic errors due to reflection and crosstalk noise in combinational circuits is presented. Based on the circuit level a new approach for error modeling including the duration of reflection and crosstalk errors, is described. The presented algorithm takes the high influence of error durations as well as gate and transmission line dela... View full abstract»

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  • Performance test of Viterbi decoder for wideband CDMA system

    Publication Year: 1997, Page(s):19 - 23
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (388 KB)

    This paper describes the design, the implementation, and the performance test of the Serial Viterbi decoder (SVD) using VHDL and FPGAs. The decoding scheme assumes the transmitted symbols were coded with a K=9, 32 Kbps, and rate 1/2 convolutional encoder with generator function g0=(753)8 and g1=(561)8 as defined in the JTC TAG-7 W-CDMA PCS standard. The... View full abstract»

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  • A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit

    Publication Year: 1997, Page(s):685 - 686
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB)

    A new current-mode, low-power, low-voltage and high-speed CMOS sample-and-hold circuit has been designed and fabricated. A new current-mode differential switching scheme has been adopted to eliminate errors caused by feedthrough injection from the sample switches. The experimental result yields 9-bit resolution in 9 mW power dissipation, in a 20 MHz clock frequency from a 3 V power supply View full abstract»

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  • Design driven partitioning

    Publication Year: 1997, Page(s):49 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    A new approach for partitioning VLSI digital integrated circuits is presented. In contrast to known approaches, which use only topological information, the presented method also exploits specific information about design modules and higher-level design structure. Based on this knowledge, the design-driven procedure creates a cluster structure that incorporates the inherent design relationships (e.... View full abstract»

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  • Statistical estimation of combinational and sequential CMOS digital circuit activity considering uncertainty of gate delays

    Publication Year: 1997, Page(s):95 - 100
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    While estimating glitches or spurious transitions is challenging due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational and sequential CMOS logic circuits considering uncertainty of gate delays. The methodology is base... View full abstract»

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  • A functional memory type parallel processor for vector quantization

    Publication Year: 1997, Page(s):665 - 666
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    We propose a memory-based parallel processor for vector quantization, called a functional memory type parallel processor for vector quantization (FMPP-VQ). It accelerates the nearest neighbour search of vector quantization. All distances between an input vector and reference vectors in a codebook are computed simultaneously in all PEs. The minimum value of all distances is searched in parallel. Th... View full abstract»

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  • Efficient synthesis of AND/XOR networks

    Publication Year: 1997, Page(s):539 - 544
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (552 KB)

    A new graph-based synthesis method for general Exclusive Sum-of-Product forms (ESOP) is presented in this paper. Previous research has largely concentrated on a class of ESOP's, the Canonical Restricted Fixed/Mixed Polarity Reed-Muller form, also known as Generalized Reed-Muller (GRM) form. However, for many functions, the minimum GRM can be much worse than the ESOP. We have defined a Shared Multi... View full abstract»

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