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2008 IEEE International Conference on Semiconductor Electronics

25-27 Nov. 2008

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Displaying Results 1 - 25 of 162
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • [Spine]

    Publication Year: 2008, Page(s): c1
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  • [Back cover]

    Publication Year: 2008, Page(s): c4
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  • [Title page]

    Publication Year: 2008, Page(s): i
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  • [Copyright notice]

    Publication Year: 2008, Page(s): ii
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  • International advisory committee

    Publication Year: 2008, Page(s): iii
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  • Organizing Committee

    Publication Year: 2008, Page(s): iv
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  • Scope of conference

    Publication Year: 2008, Page(s): v
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  • Message from ICSE2008 conference chair

    Publication Year: 2008, Page(s): vi
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  • Table of contents

    Publication Year: 2008, Page(s):vii - xix
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  • Plenary invited papers

    Publication Year: 2008, Page(s): xx
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  • Quantum nanoelectronics: Challenges and opportunities

    Publication Year: 2008, Page(s):A1 - A6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (978 KB) | HTML iconHTML

    After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of mic... View full abstract»

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  • Germanium nanostructures for electronic memory application

    Publication Year: 2008, Page(s):A7 - A11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1477 KB) | HTML iconHTML

    The increasing use of portable electronics and embedded systems has resulted in the need for low-voltage, high-density nonvolatile memory devices. Nanocrystal memories, utilizing the Coulomb blockade effect, have the potential to satisfy such a requirement. The primary motivation in the use of nanocrystal memories is the potential to scale the tunnel dielectric thickness to a small dimension, resu... View full abstract»

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  • Low noise avalanche photodiodes

    Publication Year: 2008, Page(s): A12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB) | HTML iconHTML

    Avalanche photodiodes (APDs) are used in many applications when conventional unit y gain photodiodes cannot provide enough sensitivity and the extra amplification provided by the impact ionization process gives it an advantage. Unfortunately this amplification or gain of the incoming optical signal is always accompanied by some 'excess noise' due to the stochastic nature of the ionization process ... View full abstract»

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  • Carbon-based electrical interconnect and thermal interface materials

    Publication Year: 2008, Page(s): A13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    Summary form only given. As integrated circuit (IC) technology continues the trend towards sub-45 nanometer feature sizes, it is imperative to retain performance of back-end features such as on-chip interconnects while gaining the cost benefit of scaling. Some major barriers to achieving continuous downward scaling include high resistance and questionable reliability of nanoscale copper lines, and... View full abstract»

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  • Design and Optimization of 40V, 0.18μm versatile HVL-DMOS device with DOE

    Publication Year: 2008, Page(s):1 - 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1367 KB) | HTML iconHTML

    In this paper, a 40 V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both... View full abstract»

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  • Design of 0.18um high voltage LDMOS for automotive application

    Publication Year: 2008, Page(s):6 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8295 KB) | HTML iconHTML

    Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80 V. The electrical behaviors of the designed high voltage LDMOS for both on state and of... View full abstract»

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  • Switching converter with highly stable delta-sigma modulator

    Publication Year: 2008, Page(s):11 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5533 KB) | HTML iconHTML

    The switching converter with the existing second order, single stage, single bit, unity gain, discrete Delta-Sigma modulator (DSM) cannot be used for full range (-1 to +1) of input signals. The DSM becomes unstable when the input signal is above plusmn0.7. The output of the second integrator saturates the operational amplifier which is used as comparator in the quantizer and hence, the switching c... View full abstract»

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  • Design and simulation of one-port SAW resonator for wireless and high temperature application

    Publication Year: 2008, Page(s):18 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3118 KB) | HTML iconHTML

    This paper present the full design consideration, operational principle, structure and frequency response simulation of one-port Surface Acoustic Wave (SAW) Resonator using Micro Wave Office (MWO) and MATLAB used for passive wireless sensing of various measurands. Since SAW Resonators are widely used in radio frequency sensing application, the development and evolution of present day SAW devices h... View full abstract»

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  • Hybrid clock network for altera structure ASIC devices

    Publication Year: 2008, Page(s):23 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5291 KB) | HTML iconHTML

    Clock performance becomes a challenge in Structure ASIC world when system performance requirement keep increasing and logic density grows rapidly. In general, clock performance is evaluated through the clock skew and the clock integrity. The difficulty in ensuring minimum clock skew while maintaining clock integrity becomes more challenging when the device size grows and clock frequency increases.... View full abstract»

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  • High performance configurable distributed hybrid memory in structured ASIC

    Publication Year: 2008, Page(s):27 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8354 KB) | HTML iconHTML

    Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is... View full abstract»

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  • Pre-silicon MOSFET mismatch modeling for early circuit simulations

    Publication Year: 2008, Page(s):33 - 37
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (805 KB) | HTML iconHTML

    The continuing scaling down of CMOS technologies contributes to the important of having early circuit simulations even before any real silicon data are available. This paper presents a methodology to extract a pre-silicon MOSFET mismatch model using backward propagation of variance (BPV) technique. All the required steps such as the correlation of process and electrical parameters through BSIM3v3 ... View full abstract»

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  • Time optimized implantation modeling for accurate process simulation

    Publication Year: 2008, Page(s):38 - 39
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2794 KB) | HTML iconHTML

    In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced. View full abstract»

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  • Low-power high-tuning range CMOS ring oscillator VCOs

    Publication Year: 2008, Page(s):40 - 44
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB) | HTML iconHTML

    This paper presents the design of two new ring oscillators based on differential and single-ended topologies using a 0.13 mum 1P8M CMOS technology. The differential oscillator utilizes feed-forward technique and a new composite load with inductive impedance, reducing the delay per stage and widening the tuning range. The output frequency ranges from 0.5 to 9.5 GHz and the circuit consumes only 9 m... View full abstract»

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  • Optimum quad band DCO in DS method for WCDMA transmitter in 90nm CMOS

    Publication Year: 2008, Page(s):45 - 48
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6109 KB) | HTML iconHTML

    We try to optimize the fully integrated phase path for a 3G polar transmitter in deep sub micron CMOS. It includes a single quad band digitally controlled oscillator (DCO)[1] providing modulation capability to handle the wide bandwidth of the WCDMA phase (frequency) data with using a nonlinearity cancellation technique, DS [3] compensator network and a switched inverter divider with interpolating ... View full abstract»

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