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Proceedings., 2nd Symposium on the Frontiers of Massively Parallel Computation

10-12 Oct. 1988

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Displaying Results 1 - 25 of 125
  • How to cluster in parallel with neural networks

    Publication Year: 1988, Page(s):31 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (619 KB)

    It is shown that the problem of partitioning a net of N patterns in a d-dimensional metric space into K clusters can, in spite of its exponential complexity, be formulated as an optimization problem for which very good, but not necessary optimal, solutions can be found by using a neural network. The network starts from many randomly selected initial states. The network is simulated on the MPP (a 1... View full abstract»

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  • Proceedings. The 2nd Symposium on the Frontiers of Massively Parallel Computation (Cat. No.88CH2649-2)

    Publication Year: 1988
    Request permission for commercial reuse | PDF file iconPDF (46 KB)
    Freely Available from IEEE
  • Load balancing for massively-parallel soft real-time systems

    Publication Year: 1988, Page(s):159 - 163
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (468 KB)

    An approach to decentralized load balancing based on statistical time-series analysis is proposed. Each site estimates the system-wide average load using information about past loads of individual sites and attempts to equal that average. This estimation process is practical because the soft-real-time systems of interest naturally exhibit loads that are periodic, in a statistical sense akin to sea... View full abstract»

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  • Fault tolerant message routing on large parallel systems

    Publication Year: 1988, Page(s):155 - 158
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    The problem of designing massively fault-tolerant message routing schemes for large parallel systems is considered. The notion of faults is extremely flexible and applies to all situations where a component is unavailable to participate in message communications. Attention is focused on the performance of schemes which use only local information to make local decisions. A framework for the analysi... View full abstract»

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  • The design of a bit-serial coprocessor to perform multiplication and division on a massively parallel architecture

    Publication Year: 1988, Page(s):419 - 422
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The design of a VLSI coprocessor element (COPE) that uses a parallel adder to achieve the increased speed needed by the many multiplications and divisions required by fast Fourier transforms (FFTs), convolutions, and other common operations is discussed. It accepts operands of variable length (N⩽16), and produces a 2N bit product. The overall process takes 4N cycles,... View full abstract»

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  • The APx accelerator

    Publication Year: 1988, Page(s):413 - 417
    Cited by:  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The architectural and implementational features that work together in the APx accelerator to achieve high sustained system performance for a significant set of compute-intensive functions are presented. The features include VLSI integration, memory bandwidth, concurrency of operations, interprocessor communications, processor selection mechanisms, and I/O bandwidth. The APx is an expandable system... View full abstract»

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  • Fingerprint identification on a massively parallel architecture

    Publication Year: 1988, Page(s):331 - 334
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    A feature-based recognition scheme for fingerprint identification on a massively parallel system is presented. The algorithm provides an orientation-independent recognition system that utilizes the features offered by massively parallel architectures. Implementation of this algorithm on the GAM I pyramid to extract the different features is discussed. The use of an adder pyramid that is incorporat... View full abstract»

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  • Massively parallel computing system for research and development applications

    Publication Year: 1988, Page(s):407 - 411
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A description of a SIMD (single-instruction multiple-data) processor development system (SPDS) is presented. The SPDS is designed to provide a cost-effective, turn-key solution to users desiring to explore massively parallel computing applications. The SPDS, which is based upon the geometric-arithmetic parallel processor (GAPP) integrated circuit, contains a two-dimensional array of between 2304 a... View full abstract»

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  • Scan line graphics generation on the massively parallel processor

    Publication Year: 1988, Page(s):327 - 329
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    The author describes the implementation of a scan line graphics generation algorithm on the massively parallel processor MPP. Pixels are computed in parallel and their results are applied to the Z buffer in large groups. To perform pixel value calculations, facilitate load balancing across the processors and apply the results to the Z buffer efficiently in parallel requires special virtue routing ... View full abstract»

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  • The Martin Marietta advanced systolic array processor

    Publication Year: 1988, Page(s):367 - 372
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    An overview of the Martin Marietta Advanced Systolic Array Processor (ASAP) is presented. The modular design of the ASAP allows a user to build as large a processor as desired by concatenating multiple, independently programmable unit arrays. Each unit array, housed on a single VME card, is composed of a two-dimensional grid of 256 bit serial nearest-neighbor connected single-instruction multiple-... View full abstract»

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  • BLITZEN: a highly integrated massively parallel machine

    Publication Year: 1988, Page(s):399 - 406
    Cited by:  Papers (6)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The design of BLITZEN, a highly integrated chip with 128 processing elements (PEs) is presented. The bit serial processing element is described, and some comparisons with the massively parallel processor (MPP) and the Connection Machine are provided. Local control features and methods for memory access are emphasized. The organization of PEs on the custom chip, with emphasis on interconnection and... View full abstract»

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  • A homogeneous computational model for spatial inference on massively-parallel architectures

    Publication Year: 1988, Page(s):323 - 326
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    A computational model for two-dimensional spatial inference on massively parallel single-instruction multiple-data (SIMD) architectures is described. In the model, spatial information is represented by three basic types of parallel variable or pvar: label maps which assign unique numbers to sets of related processors (e.g. the largest cube address of the set of processors representing a connected ... View full abstract»

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  • Parallel and pipelined VLSI design for the histogramming operation

    Publication Year: 1988, Page(s):451 - 454
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    The authors describe the design of a VLSI processing unit for the histogramming operation. The processing unit is composed of several bit-serial processing elements (PEs) connected according to the odd-even network topology. In this approach, histogramming is divided into the counting process and the filtering process. The filtering process is shown to be computationally inexpensive compared to th... View full abstract»

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  • Efficient scan operators for bit-serial processor arrays

    Publication Year: 1988, Page(s):105 - 111
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A fast algorithm is presented for broadcasting a word of length w on an n×n single-instruction multiple-data (SIMD) array of bit-serial processing elements, in time O( n+w). Data-skewing problems caused by SIMD restrictions are solved by assuming that each processing element contains a shift register and an activity flag that allows each processin... View full abstract»

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  • The performance of the Image Understanding Architecture on The DARPA integrated image understanding benchmark

    Publication Year: 1988, Page(s):361 - 364
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The author presents an overview of the DARPA integrated image understanding benchmark and of the Image Understanding Architecture (IUA). The performance of the architecture on various portions of the benchmark is discussed. A discussion of lessons that have been learned as a result of the experience, both in terms of the design of the architecture and of the benchmark, is included. With regard to ... View full abstract»

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  • Fault tolerance of allocation schemes in massively parallel computers

    Publication Year: 1988, Page(s):491 - 494
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    The author examines the problem of locating and allocating large fault-free subsystems in multiuser massively parallel computer systems. Since the allocation schemes used in such large systems cannot allocate all possible subsystems a reduction in fault tolerance is experienced. The effects of different allocation methods, including the buddy and Gray-coded buddy schemes for the allocation of subs... View full abstract»

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  • The fast Fourier transform as a test case for a systolic data flow machine

    Publication Year: 1988, Page(s):223 - 226
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    A fast Fourier transform (FFT) algorithm is mapped onto a suggested processing element topology in order to demonstrate the utility of the systolic data flow machine (SDFM) approach. The SDFM is based on the partitioning of dataflow programs (graphs) into subgraphs that are small enough that they can be loaded into programmable systolic arrays, called processing elements. Mapability and performanc... View full abstract»

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  • Portable parallel algorithms for geometric problems

    Publication Year: 1988, Page(s):195 - 198
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The development of algorithms which can be ported among different fine-grain, massively parallel architectures and yield reasonably good implementations on each is discussed. The approach is to write algorithms in terms of general data movement operations and then implement the data movement operations on the target architecture. Efficient implementation of the data movement operations requires ca... View full abstract»

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  • Generalization of orthogonal multiprocessor for massively parallel computation

    Publication Year: 1988, Page(s):391 - 398
    Cited by:  Papers (7)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    The authors present a multidimensional orthogonal multiprocessor (OMP) conceived for massively parallel computation. The OMP compares favorably with the generalized hypercube and spanning-bus hypercube. All three architectures extend the original concept of binary n-cube. Among the three, the OMP requires equal or less hardware and yet presents some interesting application potentials in m... View full abstract»

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  • Languages for massively parallel computers

    Publication Year: 1988, Page(s):3 - 13
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    The author discusses languages for massively parallel computers. Common themes seen in the organization of control structures, data, and communication patterns are discussed. Three different programming languages are presented and compared. It is shown how the themes fit in and how various aspects of these languages can be compared according to these themes View full abstract»

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  • Neurocomputing with optical pipeline networks

    Publication Year: 1988, Page(s):545 - 548
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    The authors present techniques for realizing connectionist-style neurocomputations on Opcom, an optical computer architecture based on the pipeline networking concept. The primary operation mode of Opcom is massively parallel and pipeline processing at the gate level. Special attention is paid to the implementation of the two most important functions of any neural network: learning and search (ret... View full abstract»

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  • MPP Pascal

    Publication Year: 1988, Page(s):595 - 599
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The massively parallel processor (MPP) Pascal language is presented, and the implementation decisions pertinent to mapping parallel constructs onto the MPP are discussed. MPP Pascal is a subset of the language Parallel Pascal, which extends the Pascal language by providing constructs for explicitly expressing parallelism in the form of array operations and functions. Access to several of the MPP's... View full abstract»

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  • Parallel algorithms for direct solution of large systems of equations

    Publication Year: 1988, Page(s):231 - 234
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A number of direct solution algorithms are parallelized for use in conjunction with finite-element analysis of large engineering problems. Parallel solution algorithms based on the Gauss-Jordan and Gauss elimination are implemented and compared. These parallel solvers are applied to large, dense or banded systems of equations arising from the finite-element analysis of two and three-dimensional el... View full abstract»

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  • Sort computation

    Publication Year: 1988, Page(s):137 - 141
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    A simple sort computation technique which allows some types of computation to be performed during the sort is presented. Sort aggregation and sort distribution are the two basic forms of sort computation discussed. Sort aggregation generates an accumulative or aggregate result for each group of records and places this result in one of the records. An aggregate operation can be any operation that i... View full abstract»

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  • Usefulness of the massively parallel processor for study of electronic properties of atomic and condensed matter systems

    Publication Year: 1988, Page(s):671 - 674
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    An investigation is presented into the possible increase in the efficiency of computations of electronic structures and properties of atomic, molecular, and condensed matter systems when one uses the massively parallel processor (MPP). The usefulness of MPP in improving the speed of evaluation of two-center electronic integrals and formation of Fock matrix elements necessary in electronic structur... View full abstract»

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