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ICECE Technology, 2008. FPT 2008. International Conference on

Date 8-10 Dec. 2008

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  • [CD label]

    Publication Year: 2008, Page(s): c1
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  • [Title page]

    Publication Year: 2008, Page(s): c2
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  • Hub page

    Publication Year: 2008, Page(s): i
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  • Session list

    Publication Year: 2008, Page(s): ii
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  • Table of contents

    Publication Year: 2008, Page(s):iii - xiii
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  • Brief author index

    Publication Year: 2008, Page(s):xiv - xviii
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  • Detailed author index

    Publication Year: 2008, Page(s):xix - liii
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  • The end of indexes

    Publication Year: 2008, Page(s): liv
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  • Information for authors

    Publication Year: 2008, Page(s): lv
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  • Frequently asked questions

    Publication Year: 2008, Page(s):lvi - lviii
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  • [PDF Reader FAQ and support]

    Publication Year: 2008, Page(s): lix
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  • [Title page]

    Publication Year: 2008, Page(s): lx
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  • Foreword

    Publication Year: 2008, Page(s): lxi
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  • Organizing Committee

    Publication Year: 2008, Page(s): lxii
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  • Technical Program Committee

    Publication Year: 2008, Page(s):lxiii - lxiv
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  • Re-visiting the challenges of programmable concurrent architectures

    Publication Year: 2008, Page(s): lxv
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    Summary form only given.FPGAs are the most successful example to date of programmable concurrent architectures. The 1980s saw the introduction of several kinds of concurrent processing arrays, ranging from fine-grained FPGAs to systolic arrays, to arrays of microprocessors. Of these, only FPGAs have enjoyed continuous commercial success. Now, however, with the end of the four-decade-old trend towa... View full abstract»

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  • FPGA timing, power, signal integrity and other challenges at 65 and 45 nm

    Publication Year: 2008, Page(s): lxvi
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    Summary form only given. The steady march towards smaller feature sizes has made ASIC design, modeling and verification increasingly more challenging. FPGAs present an even greater challenge, since this analysis work must be performed on the user desktop, at the push of a button and for any design, without over-burdening users with the details. In this talk, I will present a brief overview of a fe... View full abstract»

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  • FPGA design productivity a discussion of the state of the art and a research agenda

    Publication Year: 2008, Page(s): lxvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    Summary form only given. As configurable computing matures there is continued interest in design productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC design tools and processes than with conventi... View full abstract»

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  • Co-optimisation of datapath and memory in outer loop pipelining

    Publication Year: 2008, Page(s):1 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (153 KB) | HTML iconHTML

    When targeting algorithms to FPGAs both the array to memory assignment and the selection of data reuse structures should be considered to maximise performance. In this work we present an integer linear programming formulation for the combined problem of array to memory assignment and data reuse selection. We include a number of cost functions to minimise during memory optimisation and show how the... View full abstract»

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  • Wave-pipelined signaling for on-FPGA communication

    Publication Year: 2008, Page(s):9 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB) | HTML iconHTML

    On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by presenting a new wave-pipelined signaling scheme to achieve high-throughput communication in FPGA. The throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional sync... View full abstract»

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  • Portable and scalable FPGA-based acceleration of a direct linear system solver

    Publication Year: 2008, Page(s):17 - 24
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (155 KB) | HTML iconHTML

    FPGAs are becoming an attractive platform for accelerating many computations including scientific applications. However, their adoption has been limited by the large development cost and short life span of FPGA designs. We believe that FPGA-based scientific computation would become far more practical if there were hardware libraries that were portable to any FPGA with performance that could scale ... View full abstract»

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  • A system-level stochastic circuit generator for FPGA architecture evaluation

    Publication Year: 2008, Page(s):25 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (149 KB) | HTML iconHTML

    We describe a stochastic circuit generator that can be used to automatically create benchmark circuits for use in FPGA architecture studies. The circuits consist of a hierarchy of interconnected modules, reflecting the structure of circuits designed using a system-on-chip design flow. Within each level of hierarchy, modules can be connected in a bus, star, or dataflow configuration. Our circuit ge... View full abstract»

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  • An FPGA-specific approach to floating-point accumulation and sum-of-products

    Publication Year: 2008, Page(s):33 - 40
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (163 KB) | HTML iconHTML

    This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical re... View full abstract»

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  • Optimizing residue arithmetic on FPGAs

    Publication Year: 2008, Page(s):41 - 48
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB) | HTML iconHTML

    Residue number system (RNS), which originates from the Chinese remainder theorem, is regarded as a promising number representation in the domain of digital signal processing (DSP). This paper describes our work on optimizing residue arithmetic units on the platform of reconfigurable devices, such as FPGAs. First, we provide improved designs for residue arithmetic units. For reverse converters from... View full abstract»

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  • Reconfigurable array for transcendental functions calculation

    Publication Year: 2008, Page(s):49 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (211 KB) | HTML iconHTML

    Expanding transcendental functions in a series of Shift-and-Add operations is an alternative to Taylor or Chebyshev series expansions when fixed-point arithmetic with reduced wordlength is required. Typically, reconfigurable arrays do not provide architectural support for shift operations. Instead, shift operations are emulated by either multiplexing logic or multiplication by a power of 2. In thi... View full abstract»

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